-
Ultra-Fast Charging Station for Electric Vehicles with
integrated split Grid Storage
Daniel Christen, Felix Jauch, Jürgen BielaLaboratory for High
Power Electronic Systems, ETH Zurich
Email: [email protected]:
http://www.hpe.ee.ethz.ch/
Keywords
>, ,, ,
Abstract
This paper presents the detailed analysis, optimisation and
hardware realisation of an ultra-fast charging stationwith a split
grid storage battery which enables to recharge electric vehicles
(EVs) in less than 10 minutes. Thestation consists of a T-type
AC-DC grid interface connected to the 400 V low voltage AC grid, a
DC-DC dualactive bridge (DAB) isolation stage, a stationary storage
battery and a high power multi-phase interleaved buckconverter for
charging operation. The operating principle of the converter
systems is briefly explained and theanalytical loss models of the
components are derived which are used in an optimisation procedure
to evaluate thepareto front limits in terms of efficiency and power
density for the DAB isolation stage and the high power charger.By
introducing a split storage battery, beneficial conditions for the
semiconductor devices are achieved so that thelosses of the high
power charger can be reduced by approximately 35 % with respect to
a standard solution withouta split as will be shown in the
paper.
1 Introduction
In recent years, the interest in electric vehicles (EVs)
strongly grew due to ecological aspects. However, the longcharging
times, which usually exceed 30 minutes for a full charge, as well
as the range limitation of EV’s due tothe available battery
technologies are still challenging problems.
To overcome the charging and range limitation, ultra-fast
charging stations are a promising solution which allowto recharge
the EVs batteries within a few minutes. With the ultra-fast
charging, the vehicle battery is designedonly for a limited range
of 100-200 km, so that the volume and the weight of the battery
could be reduced and thedriving range is extended by the short
recharging duration. Battery technologies suitable for ultra-fast
charging arebased on lithium titanate and enable charging rates of
up to 10-12 C as well as high cycle numbers in the range ofseveral
thousands [1].
Table I: Specifications of the investigated ultra-fast charg-ing
station for electric vehicles.
Grid 3Φ400Vrms
AC-DC Input StageBidirectionalIsolatedLow power (≈ 22 kW)
Storage Battery
Directly connected DC-busVariable DC voltageDischarge current
3-4 CEnergy-capacity ≈25kWh
High Power DC-DCUnidirectionalNon-isolatedHigh power (≈ 220
kW)
DC
DC
ElectricMotor
DC
DC
DC
AC
VehicleBattery
Electric Vehicle
StationaryStorageBattery
Low Voltage AC GridVN,ll = 400V
AC
DC
DC
DC
AC
DC
PV-Array
DC
DC
DC-BusVDC = variable VPV
Bidirectional isolated AC-DC converter system
High Power DC-DC Converter
Figure 1: Charging station concept with an isolated AC-DC input
stage connecting a variable DC-bus to the grid,an intermediate
storage battery as energy buffer and ahigh power DC-DC converter
for fast charging.
In order to achieve such a short charging time, charger concepts
with a high output power are required. Forexample, for a vehicle
battery with a stored energy of 20 kWh, a charger with an output
power higher than 200 kWis required in order to achieve charging
times significantly lower than 10 minutes. With this high output
power,such chargers fall into category Level III charging station
(standard J1772), which defines charging systems up to240 kW peak
power besides the low power Level I and II charging systems with a
maximum power level of 14.4kW [2, 3], that are well suited for
on-board and overnight charging.
-
In literature, many concepts for charging stations with a
constant DC-bus are described [2, 3, 4]. In this paper a newfast
charging station concept (specifications given in Table I) with a
variable DC-bus connected to an intermediatesplit storage battery
[5, 6] is investigated by which beneficial conditions for the
semiconductor devices are achievedand the efficiency is increased.
The optimal design of the power electronic converters the proposed
charging stationare presented and compared to a standard charging
station without split with respect to efficiency and power
densitybased on a pareto front optimisation (see Fig. 2).
In the first section, the concept of the charging station with a
split stationary storage battery is discussed. In thefollowing,
different power electronic converters on the grid side (section
2.1) as well as the fast charger (section 2.2)are described. The
power electronic systems are analysed and compared in η− ρ pareto
front, whereas a briefoverview of the optimisation procedure and
the loss models is given in section 3. The theoretical results and
theimplemented prototype systems are discussed in the last
section.
2 Charging Station Concept
The charging station consists of a bidirectional isolated AC-DC
grid interface, which allows to charge the stationarystorage system
as well as to feed back energy to the grid, and an unidirectional
high power DC-DC converterfor ultra-fast charging of EVs (see Fig.
2). For safety reasons and to avoid having the transformers in the
highcurrent path of the high power charger, the galvanic isolation
is realized in the low power input stage. With theintermediate
storage battery, the energy necessary for the ultra-fast charging
is provided, so that a pulsating powertransfer from the grid is
avoided. Furthermore, the intermediate storage battery can be used
in the context of smartgrid applications (e.g. power shaping) as
well as to buffer energy harvested for example from PV panels. Due
tothe high energy capacity of the intermediate storage battery
compared to the vehicle battery, the ultra-fast chargingprocess of
the vehicle battery only results in a maximum discharge current not
higher than 0.5- 1 C per cell of thestationary storage battery
while the recharge current stays well below 0.5 C. In this way, a
long life time of thestationary battery can be achieved.
Low Voltage AC GridVN,ll = 400V
AC
DC
AC
DC
Low Voltage DC-BusVDC = variable
Bidirectional isolated AC-DC Grid Interface
High Power DC-DC Converter
Split Storage Battery+-
+-
DC
DC
AC
DC
AC
DC
Low Voltage DC-BusVDC = variable
Bidirectional isolated AC-DC Grid Interface
High Power DC-DC Converter
ACElectric Vehicle
ElectricMotor
DCBattery
AC
Storage Battery
+-
a) Concept without Split b) Concept with Split
ACDC
AC
DC
DCDC
DC
AC
ACElectric Vehicle
ElectricMotor
DCBattery
AC
AC
DC
DC
AC
Low Voltage AC GridVN,ll = 400V
Figure 2: Charging station concept a) without and b) with split
storage battery.
The investigated AC-DC grid interface consists of two stages,
where the first stage is a non-isolated three-phaseAC-DC rectifier
(e.g. T-type or NPC converter) followed by an isolated DC-DC
converter (e.g. a dual activebridge converter) [6] Fig. 2a). The
high power DC-DC converter for charging the EV is realized by
interleavedbuck converters with synchronous rectification [5].Since
the battery voltages of the car as well as of the storage battery
only vary within a certain range (see Fig. 5a),a split of the
stationary storage battery (see Fig. 2b) allows to increase the
efficiency of the high power chargerwhile the voltage stress of the
semiconductor devices and the power transfer requirement for each
module arereduced. The negative rail of the storage battery is
directly connected to the vehicle battery while the chargingcurrent
on the positive rail is controlled by the interleaved buck
converters. But the introduction of the split resultsin an
unequally stressed storage battery. While the lower battery split
always carries the full charging current, theupper split only
carries the duty-cycle dependent part according to the buck
converter operated on it as describedin [5]. Therefore, the
complexity of the grid interface increases since the unequally
stressed split batteries haveto be balanced and recharged
individually. For the balancing an AC-DC rectifier with two
subsequent dual activebridges with a shared full bridge on the
primary side and two transformers is chosen (3-port DAB, see Fig.
3).The AC-DC rectifier in both concepts (see Fig. 3) is the same,
thus the following analysis focuses on the optimisa-tion of the
dual active bridges and the high power charger and compares these
concepts with respect to efficiencyand power density to a standard
solution.
2.1 AC-DC Grid Interface
While the high power charger allows to recharge an EV in a short
time, the storage battery can be rechargedcontinuously under low
power conditions (≈ 20kW) from the grid. As mentioned in the
previous section, a splitbattery leads to advantageous conditions
concerning voltage stresses and efficiency of the high power
charger, butalso requires a more complex input stage, since the
split storage batteries are not equally stressed.The considered
AC-DC grid interface consists of two stages, whereas the first
stage is a non-isolated AC-DC T-type rectifier followed by two DAB
with shared input H-bridge (3-port DAB). These two converter
systems can beanalysed separately due to the large DC-link
capacitor in between the two systems.
-
S14
S12S11 S13
S22 S23
S32 S33
S24
S21
S34
S31LR
LS
LT
vR
vS
vT
C1
C2
VDCCDC
vBat,nom= 600V
Lout
Cout
S22S21S12S11
S13 S14
+-
+-
+-
+-
+-
+-
+-
+-
vBat,1,nom= 400V
vBat,Cell
L1,out
L2,out
vBat,2,nom= 200V
C1,out
C2,outS32S31
S33 S34
S22S21
S23 S24
S12S11
S13 S14
S24S23
VDC
VDC
3-Port DAB
DAB
Figure 3: Converter system consisting of a T-type AC-DC
converter with a subsequent dual active bridge for the grid
interfacewith and without battery split.
The three-phase AC-DC T-type rectifier has been identified as
suitable topology for this application due to its highefficiency at
a relatively small switching frequency [7] and its low complexity
compared to other topologies. Forboth considered concepts the
rectifier topology is the same, which is operated with an optimal
clamping strategy[8].
I1p
V1 vp
t
t
Tp½TpTp Tp
I0p iLp
nV2 n vs
0
0
0
Figure 4: Current and voltage waveforms on thetransformer with
respect to the primary side forphase-shift modulation of a DAB.
The main difference between the grid interfaces (see Fig. 3) is
therealization of the isolating DC-DC converter. For both
conceptsthe well-known DAB [9] as standard version or the 3-port
DABrespectively (see Fig. 3) are evaluated in terms of efficiency
andpower density. In both concepts the DAB is operated with a
phase-shift modulation scheme to reach highest efficiencies. The
keywaveforms of the transformer voltages and currents are shown
inFig. 4. The required leakage inductance Lσ of the transformers
isdetermined by the minimal power Pmin ≈ 60%Pmax, which has tobe
transferred to the output, with a minimal phase-shift φmin ≈ 5%(see
Eq.1) to avoid a high reactive power circulation within thesystem
and still allows to transfer the maximal power Pmax. Forlower
part-load conditions other modulation schemes are applied[9].
Lσ =TpVinnVoutφmin(1−2φmin)
Pmin; Pmax <
TpVinnVout8Lσ
(1)
Based on Lσ, the applied voltages, the output power and
theswitching frequency, the current / voltage waveforms of the
trans-formers (see Fig. 4) and the semiconductor devices can be
deter-mined. The loss models and the optimisation procedure are
dis-cussed in section 3.
2.2 High Power DC-DC Charger
High-power charging is a challenging task due to the high
currents of several hundred amperes as well as a wideoutput voltage
range due to the battery. Since the isolation to the grid is
realised in the AC-DC stage (see Fig. 2b)non-isolated DC-DC
converters are the most suitable topologies to simultaneously
achieve a high efficiency and ahigh power density.
V
Charging
vBat, Car
v1,min
v1b,maxv1b
v1
SoC10% 90%
Discharging
+-
+-
+-
+-
S1L
v1
v1b
+-
vBat, Car
v1a
S2
LF,1
CF,1
CF,2
a) b)
Vehicle Battery Operating Area
Figure 5: a) Operating area of the converter system with respect
to EV’s battery voltage vbat and of the battery splits v1 and
v1b.The EV’s battery voltage has to be within the voltage range
defined by v1b and v1. b) Proposed converter system for the
highpower charger with a split battery storage [5].
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In [10], several bidirectional non-isolated DC-DC converters are
compared, including cascaded buck-boost, halfbridge, Cuk and SEPIC
converters. Due to the low number and size of the passive
components and the lowconduction losses in the semiconductor
devices, the half-bridge converter achieves the highest efficiency
of theevaluated topologies.To reduce the size of the passive
components and to achieve soft-switching conditions for the
semiconductordevices in [11, 12, 13, 14] multi-phase converter
systems are proposed. By interleaving the phase currents of
thedifferent modules, which are operated in triangular current mode
(TCM [15], see Fig. 6), a smooth output currentcan be achieved. The
total volume of the inductors is reduced by a factor of 1/N and due
to the small output currentripple the size of the input and output
filter is minimised as well. Furthermore, a modular multi-phase
convertersystem has also the advantage of achieving high
efficiencies under part load conditions by adapting the number
ofactive phases (also called power shedding).
The efficiency can further be increased by reducing the required
blocking voltage of the semiconductor devices.There are several
strategies to reduce the voltage stress of the semiconductor
devices. Different kinds of three-levelconverters like the neutral
point clamped and the flying capacitor converter are presented in
[16, 17]. In [18] a novelstrategy by introducing a splitting of the
input voltages as for example shown in Fig. 5 is proposed. The
reducedoperating voltage enables using switching devices with a
lower blocking voltage. This results in a reduction ofthe
conduction and switching losses, so that the power density can be
increased. One drawback of this conceptis, that the EV’s battery
voltage vBat has always to be within the voltage range limited by
the storage battery split(v1b < vBat < v1) to avoid a direct
connection / short-circuit between the lower battery split and the
EV’s battery.
iL,iImax
IL,min
Ioutn
t1 t2t0 t3 t4 t5 t6
Iout
vL,i
v1-vBat
v1b-vBat
t
t
ton
Figure 6: Current and voltage waveforms in the in-ductor of the
interleaved high-power dc-dc chargerwith a TCM modulation
scheme.
The half-bridge converter operates in triangular current
mode(TCM, [15]) to achieve soft-switching for all semiconductor
de-vices. In the following, the operating principle is briefly
reviewedand the current and voltage waveforms during one switching
pe-riod are shown in Fig. 6. Referring to Fig. 6 one switching
periodof one module can be divided into six intervals which are
relevantfor the control and to determine the losses.In the first
phase [t0..t1], the high side switch S1 is conducting andthus a
positive voltage is applied across the inductor L (see Fig. 5).The
current is rising during a predefined time interval ton. At
t1,switch S1 is turned off and a resonant transition defined by the
par-asitic drain-source capacitors (Coss) of the switches and the
induc-tor L starts. When the voltage across S2 becomes zero, the
bodydiode of S2 starts conducting at t2. Thus S2 can be turned on
underzero voltage conditions (ZVS). Now a negative voltage is
appliedacross L and the current decreases till it becomes zero at
t3 whatis detected by a zero-crossing detection circuit [14]. To
achievezero voltage switching conditions also for the high side
switch S1,the current has to further decrease until the energy
stored in theparasitic capacitors equals the energy stored in the
output induc-tor, where the minimal inductor current to fullfill
this condition isdetermined by Eq.2. At t4 the minimal current
IL,min to initiate thetransition is reached. S2 can be turned off
and the resonant transi-tion starts till at t5 the body diode of S1
starts conducting. SwitchS1 is now turned-on until a zero-crossing
is detected again (t6).Obviously, an increasing number of
paralleled MOSFETs nSW in-creases Coss and thus also increases
IL,min , the rms and the peakcurrent values. Hence, the losses in
the inductor are increased tooand depend on nSW . Further
information is given in [5].
IL,min =−√
2 ·QcL
· (2 · (vbat − v1b)− v1a); Qc(v1a) =∫ v1a
0Coss(v)dv (2)
3 Optimisation Procedure & Analytical Loss Models
The pareto front of a converter system with efficiency and power
density as key performance indicators allowsto identify the maximum
achievable power density and the maximum efficiency of the system
in dependence ofa given set of design parameters (e.g. core
materials, semiconductor devices) and thus enables a direct
compar-ison of the presented concepts. Fig. 7 shows the employed
optimisation procedure to calculate the pareto frontof the
considered converter systems. Based on the design parameters and
system specifications (Lσ, Pout , volt-ages etc.) the
characteristic current and voltage waveforms of the converter
system can be determined. Withthe calculated waveforms, the
semiconductor chip area and the magnetic components (transformer,
inductor) canbe optimised with respect to their efficiency and
power density. Furthermore, the volume and power losses ofthe
filter capacitors, the control electronic and the fans are directly
determined. The component related paretofronts of the
semiconductors and the magnetic components are combined to a 3-D
pareto surface. With the 3-Dpareto front the optimal volume/loss
distribution can be identified and results in a system pareto
front. It hasto be mentioned that the semiconductor losses and the
losses in the magnetic components are considered to be
-
independent. This is not valid for the high power charger since
the resonant transition and thus the current wave-form in TCM
operation is strongly influenced by the number of semiconductor
devices in parallel nSW and theircapacitance (see section 2.2), for
which reason nSW has to be varied in the system specifications (see
Fig. 7).
Varia
tion
of f s
Technology parameters & material parametersref.
semiconductor, 0, r, i, ...
System specifications & operating pointfs, L , n, Pout1,
Pout2, V1, V21, V22 , ...
Characteristic voltages and currentsiL, iMOS,i, vp, vs ...
Var. of geometry param. (l, w, h, Ac, Aw,...) = f(Vol)
Loss calculation winding losses core losses
Temperature
Volume variation
PV,mag
Volmag
Loss calculation conduction losses switching losses gate drive
losses
Optimisation ofheatsink (volume)
Variation of number of paralleled MOSFETs nsw
PV,MOS
VolMOS
Filter capacitors volume
Optimisation of MOSFETsOptimisation mag. comp.
Calculation of pareto front
v
Control electr. volume losses
Fans volume losses
Add. contributions
Figure 7: Optimisation procedure to calculate the pareto
frontfor the dual active bridge.
The two major loss sources considered in the optimisa-tion of
the converter systems are the magnetic compo-nents (core and
winding losses) and the semiconductorlosses (switching and
conduction losses). In the fol-lowing the loss models are described
in detail.
3.1 Modelling of the Semiconductor Losses
For calculating the switching and the conduction lossesof the
MOSFETs of the identified DC-DC converters,a reference
superjunction MOSFET (IPZ65R045C7)(indicated with ref) is used
whose parameters arescaled with respect to the necessary breakdown
voltagecapability VBD and the considered chip area (number
ofMOSFETs in parallel nsw). With the data available inapplication
notes [19, 20, 21, 22] and datasheet [23],the on-resistance can be
calculated with:
rDSon = rDSon,re f ·1/nsw · (VBD/VBD,re f )1.3 (3)A voltage
reserve of the breakdown voltage VBD of30% with respect to the
maximum working voltage isassumed for the semiconductors. Based on
rDSon theconduction losses can be determined by
PMOS,cond =1Tp
∫ Tp0
i2MOS(t)rDSon dt (4)
The switching losses are only dependent on the switch-ing
instant (ID,VDS) and the provided chip area. Inmost cases the
switching losses are only known for one reference operating point
(ID,re f ,VDS,re f ) and scalinghas to be done according to
measurements provided in datasheets and application notes. Since
ZVS is appliedin the considered topologies where MOSFETs are used,
the turn-on losses are neglected and only the turn-offlosses are
taken into account for the optimisation. Their dependency on the
drain-current ID can be estimated bymeasurements applied on a
reference device at a certain drain-source voltage VDS,re f :
E ′sw,o f f (ID) = (0.005 · I3D −0.0338 · I2D +0.2025 · ID
+9.8120) ·10−6 (5)The influence of the drain-source voltage VDS on
the switching losses is approximated by taking the energy storedin
Coss into account that is provided in most datasheets:
Esw,o f f (VDS, ID) = E ′sw,o f f (ID) · kV DS(VDS) (6)with
kV DS(VDS) =Ecoss(VDS)
Ecoss(VDSre f )and Ecoss(VDS) = (0.1 ·V 2DS +2.2 ·VDS +1286)
·10−8 (7)
With increasing chip area (number of paralleled switches nsw)
the stored energy in the MOSFETs capacitors in-creases. Thus, the
switching losses for an arbitrary switching instant can be
estimated by
PMOS,sw(VDS, ID,nsw) = Esw,o f f (VDS, ID) ·nsw · fs (8)For the
sake of simplicity, the dependency of the switching losses on the
gate resistor is considered to be optimaland thus neglected. The
losses occurring in the gate drive are approximated by
PGD = Qg ·VGS ·nsw · fs (9)In the AC-DC rectifier, IGBTs are
applied. The losses of IGBTs and the reverse conducting diode can
be deter-mined based on datasheet values, where the switching
losses are given as a function of the collector-emitter voltageand
the collector current as well as the conduction losses as a
function of the voltage drop across the IGBT [7].With the presented
equations, the losses in the semiconductor devices can be
calculated and the volume of theheatsink with respect to the
maximum junction temperature Tj,max and the ambient temperature
Tamb can be deter-mined based on a thermal network and the fan
characteristic.Eq. 10 defines the maximum allowable thermal
resistance of the heatsink Rth,hs for the semiconductor
devices.Rth, j−c is the device specific thermal resistance and
Rth,c−hs is the thermal resistance of the insulation
materialbetween the heatsink and the device.
Rth,hs =Tj,max −Tamb −PMOS,tot · (Rth, j−c +Rth,c−hs) ·1/nsw
PMOS,tot(10)
-
whs
lhschs
dhs
helAsemi
Rth,j-cPsemi,totRth,c-hs
Tj Rth,hsTamb
Figure 8: Basic design of a heatsink which is employed forthe
optimisation.
Rm,oRm,sRm,c+_
Rm,c
Rm,airN IL
a) b)1
2
Figure 9: Reluctance model for the transformer (a) and
theinductor design (b).
It is assumed that the semiconductors are placed on the top of
the heatsink whereas the total chip area (Asemi definesthe required
area to mount the semiconductor devices for a TO-247 package on the
heatsink, see Fig. 8) definesthe surface area of the heatsink (see
Fig.8). By varying the geometry, a minimal volume of the heatsink
for a giventhermal resistance can be determined as presented in
[24].To limit the degree of freedom a fixed fin geometry (fin &
air-gap width) and baseplate thickness dhs are assumed.Additional
volumes for the fans, air distribution and the control electronics
of the semiconductor devices are takeninto account as presented in
Eq. 11.
Vf an = whs(chs +dhs)l f an with l f an = 20mm Vel = Asemihel
with hel = 15mm (11)
3.2 Losses of the Magnetic Components
Besides the semiconductors, the magnetic components are the main
source of losses. Depending on the operatingpoint, the number of
turns, the core material and the core geometry, the losses in the
transformer and the inductorscan be determined.
wc
lc
hc
vc
½ bc
½ bc
bc
wc
½ bcbc
Copper-Bar
Primary WindingSecondary Winding
Spacer
Figure 10: Transformer design in the DAB with heatsink.
wc
lc
bc
bc
hc
vind
Figure 11: Inductor design for theconsidered optimisation.
3.2.1 Transformer Losses
The considered transformer is implemented with 2 E-cores where
the primary and secondary winding are placed onthe center leg with
a spacer in between to realize the desired leakage inductance Lσ
(see Fig. 10). The appropriatereluctance model (see Fig. 9) allows
to calculate the flux densities in the parts of the magnetic core
Vcore,i and thecorresponding core losses Pcore,i)in dependence of
the number of turns and the applied voltages with the
materialspecific Steinmetz parameters α, β and k [25]:
Pcore,i =1Tp
∫ Tp0
ki
∣∣∣∣dBdt∣∣∣∣α(ΔB)β−αdt ·Vcore,i with ki = k
(2π)α−1∫ 2π
0 |cos(θ)|α2β−αdθ(12)
The second source of losses are the conduction losses in the
windings. The resistance of the conductor increaseswith increasing
frequency due to skin- and proximity effects. The according losses
can be expressed as a functionof the frequency dependent [26]
scaling factors (FR,i, GR,i) for the calculation of the according
AC-resistance.
Pskin =RDC,s Nw lw
Ns∑
iFR,i · Î2L,i (13)
Pprox,i =RDC,s Nw lwNs
2π2d2w∑
iGR,i · Î2L,i (14)
Pprox,e = RDC,s Nw lw Ns ∑i
GR,i · Ĥ2e,i where He,i is the external magnetic field (15)
The average length of one winding lw and the average current
density is a function of the geometry of the coreand the
corresponding copper fill factor kcu. For the considered designs
the core material N87 [27] is assumed.Based on the design
parameters (operating point, Lσ, Np, Ns, litz wire parameters, core
material) a transformer isoptimised with respect to its volume and
efficiency what results in loss-volume limitation in the design
space [28].
-
3.2.2 Inductor Losses
The inductor is realized as shown in Fig. 11 on a C-core with a
fixed air gap lair = 2.5 mm. The loss mechanismsin the inductors
are the same as in the transformer but the flux density in the core
is calculated with respect to theinductor current.
3.2.3 Thermal Modelling
The thermal model of the magnetic components are estimated
according to [29, 30], where the internal thermalresistances are
approximated as shown in Fig. 12 and a thermal transfer coefficient
of αs=20 W/(m2 K) is assumed.In the winding, there are mainly two
thermal resistances that have to be considered, one is along the
winding(Rth,tan) while the other is between the layers (Rth,orth)
[30]. With the assumption that the losses are equally
Rth,w =(Rth,tan
∥∥Rth,orth) NLNw,L (16)Rth,c−a =
1αs ·Sc ; Rth,w−a =
1αs ·Sw,o (17)
Rth,c =lc
λc ·Ac ; Rth,w−c =diso
λiso ·Sw,i (18)(19)
+_ Tamb
PwPcc
Pc Rth, c-a
Rth, ccRth,w-c
Rth,w-a
½Rth,w
Sc
wSw,o
Sw,i
Sw,o
Sw,iS
Figure 12: Thermal network for the temperature estimationof an
inductor design.
distributed in the windings the simplified expression for Rth,w
(Eq.16) can be derived, where NL is the number oflayers, Nw,L is
the number of turns per layer. On the outer surface of the winding,
the heat is mainly transferredto the ambient while on the inner
surface the heat is mainly transferred to the core. This simplified
model also isapplied to a transformer what is not explained for
sake of brevity.
3.3 Capacitor Modelling
Even though the losses generated in the capacitors are
relatively small, they have an impact on the volume of theprototype
system. The necessary capacitance can be determined by Eq.20 under
the assumption that the AC-partof the input/output current ic is
flowing through the capacitor and the maximum allowed voltage
variation is ΔVc.
C =1
ΔVc12
∫ Tp0
∣∣ic(t)∣∣dt (20)Film capacitors are the best choice due to their
high current ripple capability compared to other types of
capacitors.Based on the reference capacitor EPCOS MKP B32676 series
[27] a quadratic dependency of the capacitance and alinear
dependency of the Resr on the voltage Vc is assumed (see Eq. 21).
Furthermore, a linear scaling law betweenthe capacitance C and the
volume Volc as well as the resistance Resr is assumed.
Cre f ,v =Cre f ·(
1.07 ·(
VcVnom
)2−5.51 ·
(Vc
Vnom
)+7.99
)·10−5 (21)
Vol =Volre f · CCre f ,v ; Resr = Resr,re f ·(
14.55 ·(
VcVnom
)+9.43
)·10−4 · Cre f ,v
C(22)
4 Results & Prototype System
Based on the previously presented loss models and the
characteristic voltage and current waveforms, the paretofronts for
the presented converter systems are determined. In the following,
the results of the optimisation arediscussed and the prototype
systems are presented.
4.1 Grid Interface
To perform a realistic comparison between the two topologies,
the geometries of the transformer, the heatsink andthe number of
switches have to be kept within the boundaries which are listed in
Tab.II.As can be seen in Fig. 13, the achievable efficiencies are
almost the same. The heatsink volume especially forlarge chip areas
is determined by its minimal thickness for mounting and not by the
necessary Rth,hs. Furthermore,the voltage ripple on the output
filter capacitor is limited to ΔVc = 2%Vc, but the AC current is
approximately thesame, what nearly doubles the filter volume for
3-port DAB due to the current capability of the capacitors.The
designed 3-port DAB only achieves an efficiency of 98.0% at a power
density of approximately 2.2 kW/dm3.However, for reasons of costs
only two MOSFETs (IPZ65R019C7) in parallel are used in the
prototype and the
-
Table II: Optimisation BoundariesTransformer
Core Material N87Core Length lc [40mm... 150mm]Core Width wc
[40mm... 150mm]Core Height hc [10mm... 120mm]Core Center Leg Width
bc [10mm... 50mm]Strand Diameter ds [0.1mm]Winding Fill Factor kw
0.7Litz-Wire Fill Factor klitz 0.4Number of primary Turns Np
[4...45]
SemiconductorReference MOSFET IPZ65R045C7Paralleled MOSFETs nsw
[2... 15]
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.598.2%
98.3%
98.4%
98.5%
98.6%
98.7%
98.8%
98.9%
99.0%
99.1%
Power Density P (kW/dm3)
Effic
ienc
y
fS=50 kHzPout=20 kW
3-port DABDAB
Figure 13: pareto front limit for the 3-port DAB within the
de-sign boundaries.
implemented transformer is limited due to standard E-cores and
litz wires which have been employed. Thus, thetransformer is not
pareto optimal and has higher power losses than the theoretical
design. The overall grid interfaceachieves an efficiency of
approximately 96% at a power density of approximately 1 kW/dm3. The
prototypesystems have been tested at full power for more than an
hour to proof the functionality of the concept. In Fig. 16and Fig.
17 the voltage and current waveforms on the transformers are
plotted.
Table III: Converter losses at the nominal operating point ofthe
AC-DC T-type rectifier
Converter SystemOutput Power Pout 20kWDC-Link Voltage VDC
800VAC-Input Voltage Vph 400VTotal Power losses Pv,tot
365.1WEstimated Efficiency η 98.1%
Losses per InductorCopper Losses PLCu 9.5WCore Losses PL,core
8.0W
Semiconductor per BridgeConduction Losses PIGBT,cond
51.2WSwitching Losses PIGBT,s 46.1W
Aux. & Ctrl. (common) Paux,t 20W
Common Mode & Differnetial Mode Filter
Boost Inductors
AC Voltage & Current Measurements
Output Capacitors
Auxilary & Ctrl.-Electronics
485 mm
260 mm
85 mm
Figure 14: Implemented non-isolated AC-DC T-type rectifierfor
the input stage of the prototype system.
Table IV: Converter losses for the 3-port DABConverter
System
Output Power Upper Split (u.s.) Pout1 9kWOutput Power Lower
Split (l.s.) Pout2 11kWDC-Link Voltage VDC 800VOutput Voltage Upper
Split (u.s.) VDC1 400VOutput Voltage Lower Split (l.s.) VDC2
200VTotal Power Losses Pv,tot 397.5WEstimated Efficiency η
98.0%
Transformer LossesCopper Losses Transformer 1/2 PLCu1,2 70.0W/
54.4WCore Losses Transformer 1/2 PL,core1,2 13.2W/ 14.8W
Semiconductor LossesPrimary Side Switches PMOS,p 70.75WSecondary
Side Switches (u.s.) PMOS,s1 60WSecondary Side Switches (l.s.)
PMOS,s2 94.5W
Aux. & Ctrl. (common) Paux,t 20W
Auxilary & Ctrl.-Electronics
Primary Side Full Bridge
Secondary Side Full Bridgelower Split
Secondary Side Full Bridgeupper Split
Transformers
90 mm
253 mm
400 mm
Figure 15: Implemented 3-port DAB converter system.
205 210 215 220 225-200
0
200
400
600
800
1000
-50
-40
-30
-20
-10
0
10
20
30
40
50vp
vs2
ip2
Time ( s)
Volta
ge (V
)
Cur
rent
(A)
Figure 16: Current & voltage measurements on thehigh-side
transformer of the 3-port DAB.
205 210 215 220 225-200
0
200
400
600
800
1000
-50
-40
-30
-20
-10
0
10
20
30
40
50
Time ( s)
Volta
ge (V
)
Cur
rent
(A)
vp
vs1
ip1
Figure 17: Current & voltage measurements on thelow-side
transformer of the 3-port DAB.
-
4.2 High Power DC-DC Charger
For calculating the pareto front of the high power DC-DC charger
the inductor is assumed to be built with a C-core(N87) and a fixed
air gap lair=2.5 mm. To highlight the effect of the reduced
blocking voltage a fixed semiconductorchip area of nsw = 4 is
assumed. With the proposed design the losses in the semiconductor
devices can be decreasedby about 35% and thus also the required
heatsink volume can be reduced. Furthermore, the filter volume
scalesdown with the energy stored in the capacitors. The flat
pareto front indicates a small contribution of the losses ofthe
inductor in the overall losses of the converter system. The thermal
limit of the inductor defines the minimalviable design (indicated
in Fig. 18). Obviously the power density as well as the efficiency
of the converter systemcan be increased (see Fig. 18) by the
applied split grid storage. The prototype system consisting of 6
interleavedmodules was tested during 5 minutes on several operating
points where one measurement is exemplarily shown inFig. 21.
0 5 10 15 20 2599.30%
99.35%
99.40%
99.45%
99.50%
99.55%
99.60%
99.65%
Power Density P (kW/dm3)
Effic
ienc
y
Impl
emen
tatio
n lim
it of
indu
ctor
Impl
emen
tatio
n lim
it of
indu
ctor
High power charger with split battery storageHigh power charger
without split
fS = 50 kHzPout= 200 kWnm =12
35% of PV
Figure 18: pareto front limit for interleaved buck con-verter
with and without split battery storage within thedesign
boundaries.
Table V: Losses of the interleaved buck converter at thenominal
operating point
Converter SystemNumber of Modules N 12Output Power Pout
220kWMaximum Output Current Iout,max 660ATotal Power Losses Pv,tot
943.6WEstimated Efficiency η 99.57%
Inductor (per Mod.)Copper Losses PLCu 9.3WCore Losses PL,core
4.7W
Semiconductor (per Mod.)Conduction Losses PFET,cond
37.4WSwitching Losses PFET,s 22.6W
Input Filter (total) Pf ilt 14.5WOutput Capacitor (total) Pcout
0.1WAux. & Ctrl. (per Mod.) Paux,m 9WAux. & Ctrl. (common)
Paux,t 20W
Output Inductor 9.1 uH5 x E40/16/12 EPCOS
Connection to Output positive RailMOSFET (2
parallel)STY139N65M
Low Power Fan
Auxillary & Control
Zero Crossing Detection Core
Input Power Connections
Output Power Connections
ModulesFPGA Ctrl.-Board
Zero Crossing Detection
300 mm460 mm
60 mm
Figure 19: Prototype system of the interleaved buck converter
with 6 modules.
MOSFET
Zero Crossing Detection Modules
Figure 20: Thermal measurement of the highpower DC-DC converter
after 5 min test.
iout
iL1
iL2
vS2
Figure 21: Measurement of the interleaved currents (exemplarily
two mod-ules im,1 and im,2) during a 5 minutes full load test at an
output current ofiout= 245 A and the voltages v1a= 280 V and
vBat,Car=170 V. vS2 representsthe voltage on the low-side switch S2
of one module.
5 Summary & ConclusionIn this paper, a concept for an
ultra-fast charging station with a split battery is presented and
the different powerelectronic stages are analysed and optimised
with respect to their efficiency and power density. The two
consideredcharging station concepts with and without split storage
battery are compared in a η-ρ pareto front based onmulti-domain
models and optimisations. The grid interface with a battery split
has no disadvantage in terms ofefficiency. However, with the
standard concept a higher power density of the grid-interface can
be achieved due toincreased filter capacitors and heatsink volumes
of the 3-port DAB for recharging the split storage battery. Withthe
integration of the split battery especially the semiconductor
losses in the high-power charger can be reduced byaround 35% what
also results in a higher power density. The single prototype
systems and the charging station areimplemented within the UVCEV
project [31] to proof the functionality of the proposed
concept.
-
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