HIGH PERFORMANCE THREE PHASE AC/DC CONVERTERS FOR DATA CENTERS 1cm

HIGH PERFORMANCE THREE PHASE

AC/DC CONVERTERS FOR DATA

CENTERS

KAWSAR ALI

(B. Tech, NIT Durgapur, India)

A THESIS SUBMITTED

FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2017

Supervisor:

Dr Jimmy Chih-Hsien Peng

Examiners:

Associate Professor Ashwin M Khambadkone

Dr Sahoo Sanjib Kumar

Associate Professor Wilson Eberle, University of British Columbia

DECLARATION

I hereby declare that this thesis is my original work and it has

been written by me in its entirety. I have duly

acknowledged all the sources of information

which have been used in the thesis.

This thesis has also not been submitted for any degree

in any university previously.

________________________________

Kawsar Ali

12 December 2017

Acknowledgements

I owe my sincere gratitude to my supervisor Dr. Jimmy Chih-Hsien Peng for his advice,

encouragement, and continuous support in my research. Not only did he take me in

his team when I was going through a turmoil in my Ph.D., he patiently guided me all

the way to produce a presentable thesis out of my work through numerous sessions of

feedback and discussions. I am extremely grateful to my previous- and co-supervisor

Dr. Pritam Das for introducing me to this research area and supervising my work for

the first three years, during which I finished the major part of my Ph.D. work. I also

express my sincere thanks to my previous co-supervisor Dr. Sanjib Kumar Panda for

his technical inputs, and especially for his kind understanding and support during tough

times.

I am extremely grateful to Dr. Ashwin M. Khambadkone and Dr. Sanjib Kumar

Sahoo for their constructive guidance and critical inputs as Ph.D. thesis committee

members. Also, my sincere thanks to the anonymous reviewers of IEEE transactions

who helped me a lot to improve the quality of my research papers leading to their

eventual acceptance in the journals.

My special thanks to Mr. Y. C. Woo, Lab-in-Charge of Electrical Machines and

Drives Lab, for his persistent support throughout my Ph.D. I am also grateful for the

timely assistance from Mr. M. Chandra, Ms. Nurshaheeda and Mr. H.C. Seow.

The four years experience of my Ph.D. in NUS is something I will cherish for my

entire life. My profound thanks to my fellow research scholars, research engineers and

research fellows in Electrical Machines and Drives Lab for all the help to make my

stay more enjoyable and meaningful. My sincere thanks to Naga, Sindhu, Sandeep,

Subash, Cikai, Dongdong, Jeevan, Rajesh, Jayantika, Saurabh, Binita, Shiva, Ravikiran,

Elango, Ramprakash, Kanakesh, Amit, Kalpani, Carlos, Srinivash, Dr. Priyesh and Dr.

Aravinth. There are several other individuals who have helped me during my Ph.D.

and made me into who I am today. My warmest thanks to all of them. Finally, I am

grateful to Department of Electrical and Computer Engineering, National University of

3

Acknowledgements

Singapore (NUS) for providing me an opportunity to pursue Ph.D. in Singapore.

I owe so much appreciation to many warm-hearted, and wonderful friends inside

and outside of the NUS campus. Thanks to Neha, Naushad, Rusha, Saptak, Tanmay,

Soumya, Shalabh, Rahul, Raj for all the memories we created together in numerous

occasions. My four years flatmate Sai Kishore Ravi deserves a special mention here.

Also, I will cherish the endless phone conversations and online hangouts with my school

friends Taushif, Jahanur, Selim, Hyder and Washim.

I have been deeply touched by the endless love and boundless support of my parents

and my extended family – my brothers, sisters, uncles, aunts and my grandma. My

sincere thanks to all of them for always being on my side and keeping a sweet home

for me no matter what happens. I wish to dedicate to them what I have accomplished

today.

4

Contents

Acknowledgements 3

Summary 9

1 Introduction 30

1.1 Data Centers in Modern Energy Market . . . . . . . . . . . . . . . . . . 30

1.2 Existing Power System Topologies in Data Centers for Powering IT loads 32

1.2.1 AC Powered Data Centers . . . . . . . . . . . . . . . . . . . . . . 32

1.2.2 DC Powered Data Centers . . . . . . . . . . . . . . . . . . . . . . 34

1.2.2.1 48 V DC System . . . . . . . . . . . . . . . . . . . . . . 34

1.2.2.2 380 V DC System . . . . . . . . . . . . . . . . . . . . . 37

1.3 Literature Review of Three-Phase AC-DC Power Conversion for Data

Center Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.3.1 Two Stage Three-Phase AC-DC Power Conversion . . . . . . . . 40

1.3.1.1 Stage 1: Front-end PFC . . . . . . . . . . . . . . . . . . 40

1.3.1.2 Stage 2: Back-end DC-DC converter . . . . . . . . . . . 45

1.3.2 Single Stage Three-Phase AC-DC Power Conversion . . . . . . . 46

1.3.3 Output Voltage Ripple of Three-Phase AC-DC Converters . . . . 50

1.4 Literature Review on DC-DC Power Supplies for the ICT equipment . . 50

1.5 Summary of Literature Review . . . . . . . . . . . . . . . . . . . . . . . 51

1.6 Research Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

1.7 Proposed Single-Stage Three-Phase AC-DC Converter . . . . . . . . . . 54

1.8 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 57

1.9 Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2 The Nine-Switch Converter – Review and Benchmark of Application 62

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5

Contents

2.2 Topology, Modulation and Control of the Nine-switch Converter . . . . 65

2.2.1 Switching constraint . . . . . . . . . . . . . . . . . . . . . . . . . 66

2.2.2 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.2.2.1 AC-AC Common Frequency (AC-AC CF) mode . . . . 69

2.2.2.2 AC-AC Different Frequency (AC-AC DF) mode . . . . 70

2.2.2.3 AC-DC Different Frequency (AC-DC DF) mode . . . . 70

2.2.3 Space Vector PWM . . . . . . . . . . . . . . . . . . . . . . . . . 71

2.2.4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

2.3 LLA of Nine-Switch Converter for Different Modes of Operation . . . . 73

2.4 LLA of Nine-Switch Converter for Load-Source Combination in AC-DC

DF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.4.1 Qualitative Reasoning for Existence of LLAs . . . . . . . . . . . 78

2.4.2 Mathematical Derivation of LLAs . . . . . . . . . . . . . . . . . 80

2.4.3 Efficient Load Sharing . . . . . . . . . . . . . . . . . . . . . . . . 86

2.5 Simulation Results and Discussions . . . . . . . . . . . . . . . . . . . . . 86

2.6 Theoretical Conduction Loss Comparison . . . . . . . . . . . . . . . . . 90

2.7 Experimental Results and Discussions . . . . . . . . . . . . . . . . . . . 91

2.7.1 For ID/IU < 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

2.7.2 For ID/IU > 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.8 Benchmark of Application Criteria of Nine-Switch Converter with Lower

Conduction Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3 An APWM HB Series Resonant Converter with Magnetizing Current

Assisted ZVS 99

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.2 Steady State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.2.1 Topology and Equivalent Circuit Model . . . . . . . . . . . . . . 102

3.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.2.3 Calculation of Input Power . . . . . . . . . . . . . . . . . . . . . 108

3.3 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.4 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.4.1 Calculation of Transformer Turns Ratio . . . . . . . . . . . . . . 110

3.4.2 Design of Magnetizing Inductance . . . . . . . . . . . . . . . . . 110

3.4.3 Design of the Resonant Tank . . . . . . . . . . . . . . . . . . . . 113

3.4.4 Correction Factor and Quality Factor . . . . . . . . . . . . . . . 113

6

Contents

3.4.5 Parameter Variations . . . . . . . . . . . . . . . . . . . . . . . . 114

3.5 Design Implementation in Data Center PoL Converters . . . . . . . . . 116

3.5.1 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.5.2 Proposed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.5.3 Physical Design of Magnetic Components . . . . . . . . . . . . . 118

3.6 Experimental Results and Discussions . . . . . . . . . . . . . . . . . . . 119

3.7 Comparison of Different APWM HB Resonant Topologies . . . . . . . . 126

3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4 A Nine-Switch Interleaved Three-Phase AC-DC Single Stage Isolated

Converter 128

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4.2 Steady State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.2.1 Topology and Equivalent Circuit Model . . . . . . . . . . . . . . 130

4.2.2 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.2.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.3 Design Aspects and Simulation of the Proposed Converter . . . . . . . . 136

4.3.1 Choice of DC-link Voltage . . . . . . . . . . . . . . . . . . . . . . 136

4.3.2 Choice of Switching Frequency . . . . . . . . . . . . . . . . . . . 137

4.3.3 Design of Boost Inductor and DC-link Capacitor . . . . . . . . . 138

4.3.4 Design of Resonant Tank and the High-Frequency Transformers . 138

4.3.5 Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.3.5.1 Controller Design for Boost PFC Part . . . . . . . . . . 139

4.3.5.2 Controller Design for DC-DC Resonant Part . . . . . . 140

4.4 Prototype Implementation and Theoretical Loss Analysis . . . . . . . . 143

4.4.1 Switch RMS Currents . . . . . . . . . . . . . . . . . . . . . . . . 143

4.4.2 Occurrence of Soft Switching . . . . . . . . . . . . . . . . . . . . 145

4.4.3 Selection of Switching Devices . . . . . . . . . . . . . . . . . . . 147

4.4.4 Loss Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.4.4.1 Switch turn-on loss . . . . . . . . . . . . . . . . . . . . 149

4.4.4.2 Switch turn-off loss . . . . . . . . . . . . . . . . . . . . 149

4.4.4.3 Inductor core loss . . . . . . . . . . . . . . . . . . . . . 150

4.4.5 Validation of Choice of Sawtooth Carrier over Triangular Carrier 150

4.5 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.6 Cost Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

4.7 Results with 380V DC Output Voltage . . . . . . . . . . . . . . . . . . . 161

7

Contents

4.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

5 Effect of Three-Carrier Modulation in Input Current Harmonics 166

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.2 For Double-edge Naturally Sampled PWM . . . . . . . . . . . . . . . . . 168

5.3 For Regular Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.3.1 Single-edge Regular Sampled PWM . . . . . . . . . . . . . . . . 171

5.3.2 Symmetrical Regular Sampled PWM . . . . . . . . . . . . . . . . 173

5.4 Validation of the Three-Carrier Modulation in the Proposed Nine-Switch

Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6 Conclusions and Future Works 179

6.1 Summary of Work Done . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.2 Prospective Research Work . . . . . . . . . . . . . . . . . . . . . . . . . 182

6.2.1 Benchmarking of Nine-Switch Converter against BTB Converter 182

6.2.2 Bi-directional Battery Charger . . . . . . . . . . . . . . . . . . . 183

6.2.3 Study on Phase-Shedding . . . . . . . . . . . . . . . . . . . . . . 183

6.2.4 Reliability Study of the Converters . . . . . . . . . . . . . . . . . 184

6.2.5 Improvement of DC Bus Utilization . . . . . . . . . . . . . . . . 184

6.2.6 Hold Up Time (HUT) Analysis . . . . . . . . . . . . . . . . . . . 184

Appendix A High Step-up APWMConverter for Integration of PV Mod-

ule to Data Center 186

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

A.2 Converter Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

A.3 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

A.3.1 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

A.3.2 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

A.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Appendix B Implementation of Control in TI DSP F28335 198

B.1 The Problem with Generation of XOR-ed Pulses . . . . . . . . . . . . . 198

B.2 Indirect XOR-ed Pulses from F28335 Microcontroller . . . . . . . . . . . 199

B.3 The Controller Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

B.3.1 Sinusoidal PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

B.3.2 Space Vector PWM . . . . . . . . . . . . . . . . . . . . . . . . . 214

8

Summary

To improve the efficiency of the MW level power consumption in data centers and

to achieve a Power Usage Effectiveness (PUE) closer to 1.0~1.2, cooling has by far

become the most important aspect of modern day data center operations. Apart from

improvement of the cooling technology itself, focus is being given on reduction of heat

generation, especially from the power systems inside the data center. Migration towards

a DC based power architecture has proven to be promising in this regard mainly because

of reduction of number of conversion stages and the absence of phase balancing or

harmonic issues. While 48 V DC has already been in place in most telecom central

offices, modern data centers are shifting towards the more efficient 380 V DC system.

The common practice for converting the utility three-phase AC to regulated and

isolated DC is a two stage conversion scheme, which also ensures unity power factor and

less than 5% Total Harmonic Distortion (THD) of the input currents. In order to reduce

the cost, size, and complexity associated with two-stage AC-DC power conversion, active

research is ongoing to come up with single-stage converters that integrate the functions

of Power Factor Correction (PFC) and isolated AC-DC conversion in a single power

converter. However, obtaining a regulated and isolated DC voltage from three-phase AC

supply in a single stage comes at the cost of the inefficient Discontinuous Conduction

Mode (DCM) of the input currents. Finding a solution for a single-stage conversion with

Continuous Conduction Mode (CCM) of the input currents is the need of the hour.

This thesis proposes a novel Silicon Carbide (SiC) based nine-switch single-stage

isolated three-phase AC-DC converter, which integrates a three-phase Active Front-End

(AFE) boost PFC rectifier and three phase-interleaved half-bridge DC-DC resonant

converters in a single stage. In a conventional two-stage configuration this integration

requires twelve switches, which means the proposed converter yields a 25% saving in

active switch count. A novel modulation scheme using three separate 120 phase shifted

high frequency carriers for the three legs of the converter is developed to drive the

switches. It is shown that such modulation scheme leads to interleaved operation of

9

Summary

the three DC-DC resonant converters integrated within the proposed topology resulting

in 67% lower output DC voltage ripple than the conventional two-stage configuration.

Most importantly, despite being a single-stage topology, the proposed converter operates

in CCM, and thus eliminates all the issues related to DCM.

This thesis also proposes a novel Asymmetrical Pulse-Width Modulated half-bridge

(APWM HB) DC-DC resonant converter with naturally extended range of zero-voltage

switching (ZVS), applicable for the Point-of-Load (PoL) converters of data centers to

improve their efficiency. The novelty of this converter is in its design, which uses the

magnetizing current and eliminates the need of extra components (like LC network)

that are otherwise used in APWM HB resonant converter for ensuring ZVS over wide

range of line and load variation. Empirical formulae are derived to design the resonant

network systematically in a flow-chart based manner. A new optimal method of design

of the magnetizing inductance of the high-frequency transformer is also presented, which

is equally applicable to a standard LLC converter.

Finally, while reviewing and discussing about the nine-switch converter, this thesis

also benchmarks, both analytically and experimentally, the application criteria of the

nine-switch converter for having lower conduction loss than the twelve-switch back-to-

back (BTB) converter.

All the analytical works in this thesis have been validated with appropriate experi-

mental prototypes, and their measured efficiencies are compared with relevant existing

works.

10

List of Tables

2.1 Application Criteria of Nine-Switch Converter for Existence of LLA as

per QIN et al. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.2 Switching States of BTB Converter . . . . . . . . . . . . . . . . . . . . 66

2.3 Switching States of Nine-Switch Converter . . . . . . . . . . . . . . . . 66

2.4 Design Parameters for Comparison of Nine-switch Converter and BTB

Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.5 Calculated Conduction Losses for the Two Converters . . . . . . . . . . 91

2.6 Updated List of Application Criteria of Nine-Switch Converter for Exis-

tence of LLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.1 Specifications for Design of the Proposed APWM HB Resonant Converter 116

3.2 Design Comparison of the Proposed APWM HB Converter and the Ref-

erence Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.3 Important Components Used for the Two Converter Prototypes . . . . 117

3.4 Details of Magnetic Components Used for the Two Converter Prototypes 119

3.5 Comparison of Different APWM HB Resonant Topologies . . . . . . . . 127

4.1 Converter Parameters for Design of the Proposed Single-Stage Nine-Switch

Converter with 48 V Output . . . . . . . . . . . . . . . . . . . . . . . . 144

4.2 Comparison of Switching Devices for Design of the Proposed Single-Stage

Nine-Switch Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

4.3 Important Components Used for the Proposed Single-Stage Nine-Switch

Converter Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

4.4 Details of Magnetic Components Used for the Proposed Single-Stage

Nine-Switch Converter Prototype . . . . . . . . . . . . . . . . . . . . . 148

4.5 Comparison of Manufacturing Cost between the Nine-Switch Converter

and the Twelve-Switch Converter . . . . . . . . . . . . . . . . . . . . . 161

11

List of Tables

4.6 Converter Parameters for Design of the Proposed Single-Stage Nine-Switch

Converter with 380 V Output . . . . . . . . . . . . . . . . . . . . . . . 162

A.1 Specifications for the Converter Interfacing PV Module . . . . . . . . . 188

A.2 Design Values for the Converter Interfacing PV Module . . . . . . . . . 188

A.3 Key Components used for the Prototype of the Converter Interfacing PV

Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

A.4 Details of Magnetic Components used for the Prototype of the Converter

Interfacing PV Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

A.5 Different efficiencies of the Converter Interfacing PV Module . . . . . . 195

A.6 Comparison of the Proposed PV Interfacing Converter with a Reference

Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

12

List of Figures

1.1 Growing energy usage in US Data Centers. . . . . . . . . . . . . . . . . 30

1.2 Energy profile of a typical Data Center in Singapore. . . . . . . . . . . . 31

1.3 Typical configuration of the power supply architecture for conventional

AC data centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4 (a) Typical configuration of the power supply architecture for DC data

centers, (b) 48 V DC power as typically implemented in telecommunica-

tions central offices, and (c) Typical configuration of the power supply

architecture for a 380V DC powered data center. . . . . . . . . . . . . . 35

1.5 Typical architecture of 48V-rack-power-distribution for AC data centers. 36

1.6 Google’s 48V-rack-power-distribution for AC data center. . . . . . . . . 37

1.7 Two stage AC-DC power conversion scheme. . . . . . . . . . . . . . . . 39

1.8 Limits of DC link voltage for PFC rectifiers. . . . . . . . . . . . . . . . . 41

1.9 Some of the industrially popular buck type PFC rectifiers. . . . . . . . 42

1.10 Some of the industrially popular boost type PFC rectifiers. . . . . . . . 44

1.11 Some of the industrially popular isolated DC-DC converters. . . . . . . 47

1.12 Some of the single-stage three-phase AC-DC converters. . . . . . . . . . 48

1.13 Typical DC-DC conversions inside an ICT equipment (rack). . . . . . . 51

1.14 Proposed DC based power system architecture for data centers. . . . . . 52

1.15 Proposed nine-switch converter based single-stage three-phase AC-DC

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.16 Two-stage twelve-switch back-to-back (BTB) equivalent of the proposed

nine-switch converter based single-stage three-phase AC-DC converter. 55

1.17 Proposed single-stage AC-DC converter and its decomposition into a

three-phase boost PFC rectifier and three half-bridge DC-DC resonant

converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.1 Schematic of a nine-switch converter. . . . . . . . . . . . . . . . . . . . 65

13

List of Figures

2.2 Schematic of a twelve-switch back-to-back (BTB) converter. . . . . . . 65

2.3 Generation of gate pulses for one leg of the nine-switch converter. In-

sertion of dead times to protect the nine-switch converter against any

accidental short-circuit of DC-link is also automatically taken care of by

the XOR-ing process, as long as proper dead times are inserted to vg,A1,

vg,A1′and vg,A3, vg,A3′, as per controlling a normal Voltage Source

Inverter (VSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.4 Different modes of operation of the nine-switch converter based on the

load/source connected to the terminals. . . . . . . . . . . . . . . . . . . 69

2.5 SPWM scheme for CF-mode operation of the nine-switch converter. . . 70

2.6 SPWM scheme for DF-mode operation of the nine-switch converter. . . 71

2.7 SPWM scheme for AC-DC-DF mode operation of the nine-switch converter. 71

2.8 Modular Space Vector Modulation (SVM) for the nine-switch converter. 72

2.9 Modulation of the nine-switch converter. . . . . . . . . . . . . . . . . . 73

2.10 Instantaneous switch currents of the nine-switch converter and the twelve-

switch converter for different switching states. . . . . . . . . . . . . . . 74

2.11 LLAs of nine-switch converter for AC-AC CF mode with a load-source

combination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

2.12 LLAs of nine-switch converter for AC-DC DF mode with a source-source

combination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2.13 The special load-source combination of the nine-switch converter and the

BTB converter under study. . . . . . . . . . . . . . . . . . . . . . . . . 79

2.14 Currents through SA1 of the nine-switch converter and SA1′ of the BTB

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.15 LLAs of nine-switch converter for AC-DC DF mode based on RMS switch

current, when the upper terminal is connected to a DC load and the lower

terminal is connected to an AC source. . . . . . . . . . . . . . . . . . . 84

2.16 LLAs of nine-switch converter for AC-DC DF mode based on AVERAGE

switch current, when the upper terminal is connected to a DC load and

the lower terminal is connected to an AC source. . . . . . . . . . . . . . 84

2.17 LLA conditions M > 2 and (ID/IU ) < 2 of nine-switch converter for AC-

DC DF mode based on RMS switch current, when the upper terminal is

connected to a DC load and the lower terminal is connected to an AC

source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

14

List of Figures

2.18 Comparative periodic average of total conduction losses in the nine-switch

converter and the twelve-switch converter. . . . . . . . . . . . . . . . . 88

2.19 Comparative periodic average of conduction losses in the first leg of the

nine-switch converter and the twelve-switch converter for ID = 0.5A and

IU = 0.88A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.20 Thermal simulation set-up of the nine-switch converter and the twelve-

switch converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.21 Comparison of steady-state heat flow for the nine-switch converter and

the twelve-switch converter for IU = IU = 0.88A. . . . . . . . . . . . . 90

2.22 Experimental prototype of the nine-switch converter. Two such proto-

types were used to realize the BTB topology with the middle-switches of

all legs removed and their footprints shorted. . . . . . . . . . . . . . . . 92

2.23 Key input and output waveforms of the nine-switch converter at the rated

power of Pload = 1kW with ID = 1A and IU = 0.88A. Note that Pac =

254W < 0.5× Pload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

2.24 Three-phase balanced ac currents at lower terminal with ID = 1A, and

the load current at upper terminal with IU = 0.88A. . . . . . . . . . . 93

2.25 Current through the top switch SA1 of the nine-switch converter during

POSITIVE half-cycle of phase-a voltage va with ID = 1A and IU =

0.88A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93


NEGATIVE half-cycle of phase-a voltage va with ID = 1A and IU =

0.88A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2.27 Current through the top switch SA1′ of the BTB converter during POS-

ITIVE half-cycle of phase-a voltage va with ID = 1A and IU = 0.88A.

It remains same during NEGATIVE half-cycle of va. Also, it does not

change for the other case of ID = 2.5A, as long as IU is maintained at

0.88A. Note that vg,A3′ does not have any particular significance in this

figure; it is shown to maintain similarity with Figs.2.25 and 2.26. . . . 94

2.28 Key input and output waveforms of the nine-switch converter at the rated

power of Pload = 1kW with ID = 2.5A and IU = 0.88A. Note that

Pac = 636W > 0.5× Pload. . . . . . . . . . . . . . . . . . . . . . . . . . 94

2.29 Three-phase balanced ac currents at lower terminal with ID = 2.5A, and

the load current at upper terminal with ID = 2.5A and IU = 0.88A. . . 95

15

List of Figures


POSITIVE half-cycle of phase-a voltage va with ID = 2.5A and IU =

0.88A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95


NEGATIVE half-cycle of phase-a voltage va with ID = 2.5A and IU =

0.88A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.32 Full-load experimental efficiency plots of the nine-switch converter and

the twelve-switch converter for variation of Pac,in/Pload with Pload =

1000W . Note that the horizontal axis does not indicate load power vari-

ation; it indicates the fraction of load power being supplied by the lower

terminal AC source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.1 Schematic of the standard Asymmetrical Pulse Width Modulated (APWM)

half-bridge resonant converter. Note that vs is the pole voltage incident

on the series resonant tank. . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.2 Schematic of the reference converter: modified series-resonant APWM

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.3 Schematic of the proposed APWM HB series resonant converter with

magnetizing current assisted ZVS. . . . . . . . . . . . . . . . . . . . . . 102

3.4 Equivalent circuit of the resonant network of the APWM HB series reso-

nant converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.5 Key waveforms of the proposed APWM HB series resonant converter: (a)

Switching pulses for top switch (vg1) and bottom switch (vg2); (b) Pole

voltage (vs), its fundamental ac component (vs1) and intended resonant

tank current (i′

Lr); (c) Voltage across resonant capacitor (vCr ) and voltage

across transformer primary winding (vpri); (d) Voltage across resonant

inductor (vLr ); (e) Resonant tank current (iLr ), intended resonant tank

current (i′

Lr) and magnetizing current (iLm); (f) Currents through output

diodes D1 and D2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.6 (a) Equivalent circuit of the primary side during the deadtime. (b) Key

waveforms for calculation of magnetizing inductance and deadtime. . . . 111

3.7 Variation of maximum achievable quality factor Q0 with respect to max-

imum allowable duty Dmax. . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.8 Flowchart of design procedure of the proposed APWM HB resonant con-

verter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

16

List of Figures

3.9 Laboratory prototypes of the proposed APWM HB converter and the

reference converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.10 Comparison of different currents (RMS) of the two converters. . . . . . 120

3.11 Comparison of different losses in the two converters. . . . . . . . . . . . 120

3.12 Experimental demonstration of ZVS of top switch S1 of the reference

converter at full load for different input voltages. . . . . . . . . . . . . 121

3.13 Experimental demonstration of ZVS of top switch S1 of the reference

converter at 10% load for different input voltages. . . . . . . . . . . . . 122

3.14 Experimental demonstration of ZVS of top switch S1 of the proposed

converter at full load for different input voltages. . . . . . . . . . . . . 123


converter at 10% load for different input voltages. . . . . . . . . . . . . 123

3.16 Comparative experimental efficiency plots of the two converters. . . . . 124


converter for ±20% variation of resonant inductor. . . . . . . . . . . . . 125

3.18 Capacitor voltage vCr and transformer primary voltage vpri along with

the resonant tank current iLr at full load condition of the experimental

set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.19 Capacitor voltage vCr and transformer primary voltage vpri along with

the resonant tank current iLr at full load condition of the simulated sys-

tem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.1 Proposed nine-switch converter based single-stage three-phase AC-DC

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.2 Proposed single-stage AC-DC converter and its decomposition into a

three-phase boost PFC rectifier and three half-bridge DC-DC resonant

converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4.3 Proposed three-carrier modulation scheme for the nine-switch converter.

Note that in practice, carrier frequency is much higher than the modula-

tion reference frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.4 Generation of gate pulses for the switches of the first leg and the key

terminal voltages and currents of the same leg for – (a) sawtooth carrier,

and (b) triangular carrier. It is apparent that with triangular carrier, the

middle switch operates at twice the switching frequency (2fs). . . . . . 133

4.5 Overall control scheme for the proposed nine-switch converter. . . . . . 135

4.6 PLECS simulation of the proposed control and modulation scheme. . . 136

17

List of Figures

4.7 Simulated THD variations of input currents w.r.t. switching frequency

for single-carrier vs. proposed three-carrier modulation. . . . . . . . . . 137

4.8 Bode plots of d-loop current controller for 100% and 10% loads. . . . . 141

4.9 Bode plots of q-loop current controller for 100% and 10% loads. . . . . 141

4.10 Bode plots of DC-link voltage controller for 100% and 10% loads. . . . 142

4.11 (a) Transformer equivalent circuit along with output rectifier, and (b)

Low frequency variations in rectifier currents and output voltage with

varying duty ratio mlo for a constant load. . . . . . . . . . . . . . . . . 142

4.12 Bode plots of output voltage controller for 100% and 10% loads. . . . . 143

4.13 Instantaneous currents through the switches of the first leg of the pro-

posed nine-switch converter at different switching states. . . . . . . . . 145

4.14 Identification of soft-switching areas of the switches of the first leg of the

proposed nine-switch converter within a line-cycle of the phase current ia. 146

4.15 Comparison of theoretical losses in the switches of a leg for the two devices

considered in this work. . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

4.16 Theoretical loss calculated for various components of the proposed nine-

switch converter at the rated power of 1.5 kW. . . . . . . . . . . . . . . 149

4.17 Comparison of switching losses in the middle switch of a leg for the two

types of carrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.18 Laboratory prototype of the proposed converter (boost inductors not

shown). Dimensions without heat-sink: 17cm× 14cm× 5cm. . . . . . . 151

4.19 Key input and output waveforms of the proposed nine-switch converter

at the rated power of 1.5 kW. . . . . . . . . . . . . . . . . . . . . . . . 152

4.20 Three phase balanced input currents and phase-a voltage of the proposed

nine-switch converter at full-load condition. . . . . . . . . . . . . . . . 153

4.21 Harmonic spectrum of input current at full-load condition. . . . . . . . 154

4.22 Harmonic spectrum of input current at 50% load condition. . . . . . . 154

4.23 Key experimental waveforms under load transient from – (a) 100% to

50% of rated power, and (b) 50% to 100% of rated power. . . . . . . . 155

4.24 Occurrence of ZVS for the three switches of the first leg of the converter

at different points of the phase-a current at full-load. . . . . . . . . . . . 156

4.25 (Continuation of the previous figure) Occurrence of ZVS for the three

switches of the first leg of the converter at different points of the phase-a

current at full-load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

18

List of Figures

4.26 ZVS of top and bottom switch at ω0t = π/2 of input current (Simulation).

Note that the gate voltages (vgs) have been scaled up 50 times. . . . . 158

4.27 Operation of the converter at 20% load. The middle and bottom switches

of the leg achieve ZVS even at the worst cases. . . . . . . . . . . . . . . 159

4.28 Resonant tank currents showing interleaved operation of the three half-

bridge DC-DC resonant converters. . . . . . . . . . . . . . . . . . . . . 160

4.29 Comparison of output voltage ripple for proposed three-carrier modula-

tion vs. standard single-carrier modulation. . . . . . . . . . . . . . . . . 160

4.30 Experimental efficiency plot of the proposed nine-switch converter. . . 161

4.31 Key input and output waveforms of the 380 V converter at full-load con-

dition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

4.32 Key input and output waveforms along with three-phase balanced input

currents of the 380 V converter at full-load condition. . . . . . . . . . . 163

4.33 Harmonic spectrum of input current of the 380 V converter at full-load

condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

5.1 Simulated three-phase inverter with M = 1, fc/f0 = 1050/50 = 21,

Vdc = 50V and R = 1Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.2 Bessel functions Jn(ξ) for n = 0, 1, ..., 7. . . . . . . . . . . . . . . . . . . 169

5.3 Harmonics of line-to-line voltage for triangular double-edge naturally sam-

pled PWM with a single-carrier modulation. . . . . . . . . . . . . . . . 170

5.4 Harmonics of line-to-line voltage for triangular double-edge naturally sam-

pled PWM with proposed three-carrier modulation. . . . . . . . . . . . 171

5.5 Harmonics of line-to-line voltage for sawtooth single-edge regular sampled

PWM with a single-carrier modulation. . . . . . . . . . . . . . . . . . . 172

5.6 Harmonics of line-to-line voltage for sawtooth single-edge regular sampled

PWM with the proposed three-carrier modulation. . . . . . . . . . . . 173

5.7 Harmonics of line-to-line voltage for triangular symmetrical regular sam-

pled PWM with a single-carrier modulation. . . . . . . . . . . . . . . . 174

5.8 Harmonics of line-to-line voltage for triangular symmetrical regular sam-

pled PWM with the proposed three-carrier modulation. . . . . . . . . . 175

5.9 FFT of the input current obtained from the simulation of the proposed

nine-switch converter at full load. . . . . . . . . . . . . . . . . . . . . . 176

5.10 FFT of the input current obtained from the experimental set-up of the

proposed nine-switch converter at full load. . . . . . . . . . . . . . . . . 178

19

List of Figures

6.1 Proposed nine-switch single-stage converter and its equivalent twelve-

switch back-to-back (BTB) converter. . . . . . . . . . . . . . . . . . . . 183

A.1 APWM half-bridge series-resonant converter interfacing the PV module

to the 380V bus of the DC data center. . . . . . . . . . . . . . . . . . . 188

A.2 Demonstration of the effect of ringing between the transformer secondary

leakage inductance and the diode capacitance, on the ZVS of primary-side

switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

A.3 Experimental prototype of the proposed APWM half-bridge series-resonant

converter interfacing the PV module. . . . . . . . . . . . . . . . . . . . 191

A.4 Resonant tank impedance characteristic showing the resonant frequency

of 100 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

A.5 Key waveforms showing the operation of the PV interfacing converter at

the rated conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

A.6 ZVS turn-on of top switch of the proposed PV interfacing converter at

full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

A.7 ZVS turn-on of bottom switch of the proposed PV interfacing converter

at full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

A.8 ZVS turn-on of top switch of the proposed PV interfacing converter at

50% load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

A.9 ZVS turn-on of bottom switch of the proposed PV interfacing converter

at 50% load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

A.10 Operation of the of the proposed PV interfacing converter at 40 V input

and full load of 240 W. The output voltage is regulated at 380 V and

both the switches undergo ZVS. Duty ratio required D = 0.3. . . . . . 194

A.11 Voltages across the resonant capacitor (vCr ), resonant inductor (vLr ) and

transformer primary winding (vpri) at full load. Note that the magni-

tude of the negative peak of resonant capacitor voltage is less than the

transformer primary voltage. . . . . . . . . . . . . . . . . . . . . . . . . 194

A.12 Theoretical loss distribution of the proposed PV interfacing converter at

the rated power of 240 W. . . . . . . . . . . . . . . . . . . . . . . . . . 195

A.13 Efficiency plot of the proposed PV interfacing converter with variation of

load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

B.1 Hardware for generation of XOR pulses for the middle switches of the

nine-switch converter: version-1 (left) and version-2 (right). . . . . . . . 199

20

List of Figures

B.2 Switching logic for generation of XOR pulses in F28335 controller with a

down-count mode of the counter (sawtooth carrier). . . . . . . . . . . . 199

21

List of Illustrations

AC Alternating Current

AFE Active Front-End

APWM Asymmetric Pulse Width Modulation

BTB Back-to-Back

CCM Continuous Conduction Mode

CEC California Energy Commission

CF Common Frequency

DC Direct Current

DCM Discontinuous Conduction Mode

DF Different Frequency

DM Difference Mode

DMPPT Distributed Maximum Power Point Tracking

DSP Digital Signal Processor

EU European Union

EV Electric Vehicle

FHA First Harmonic Approximation

GaN Gallium Nitride

HB Half Bridge

HUT Hold Up Time

HVDC High Voltage Direct Current

22


ICT Information and Communication Technology

IGBT Insulated-Gate Bipolar Transistor

IoT Internet of Things

IT Information Technology

LLA Low Loss Area

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

MPPT Maximum Power Point Tracking

PCB Printed Circuit Board

PCM Power Conditioning Module

PDU Power Distribution Unit

PFC Power Factor Correction

PoL Point-of-Load

PSM-FB Phase Shift Modulated Full Bridge

PSU Power Supply Unit

PUE Power Usage Effectiveness

PUPS Point-of-Use Power Supply

PV Photo Voltaic

PWLL Pulse-width Locked Loop

PWM Pulse Width Modulation

RHP Right Half Plane

RMS Root Mean Square

SELV Safety Extra Low Voltage

SiC Silicon Carbide

SPWM Sinusoidal Pulse Width Modulation

SVPWM Space Vector Pulse Width Modulation

THD Total Harmonic Distortion

23


THIPWM Third-Harmonic Injection Pulse Width Modulation

UPS Uninterruptible Power Supply

V2G Vehicle-to-grid

VSI Voltage Source Inverter

WBG Wide Band Gap

ZCS Zero Current Switching

ZVS Zero Voltage Switching

24

List of Symbols

β core loss constant

∆B peak-to-peak variation of flux density inside core

∆iAv difference of the average switch current of the nine-switch converter and

the BTB converter

∆i2RMS difference of the square of the RMS switch current of the nine-switch

converter and the BTB converter

δiL,pp peak-to-peak ripple of the inductor current

ε correction factor

ηcec California Energy Commission efficiency

ηeu European efficiency

ηx% efficiency measured at x% of the rated power

µ0 permeability of free space

ω relative operating frequency (angular)

ωr resonant frequency (angular) of the series resonant tank

ωs switching frequency (angular)

ω0 angular fundamental frequency of input AC voltage/current

ωc angular carrier frequency or switching frequency

φn phase angle of resonant tank current iLr w.r.t. vs1

θ0 phase angle of reference modulation wave

θ1 phase angle of vs1 w.r.t. vs

25

List of Symbols

θc phase angle of carrier wave

ϕ phase angle of lower terminal AC current iD

AC cross-sectional area of core

AW window area of core

Bm maximum flux density inside core

Co output filter capacitance

Ca1, Ca2 auxiliary capacitors

Cdc DC-link capacitance

Coss drain-to-source capacitance or output capacitance of MOSFET

Cr series resonant capacitor

D duty ratio

dd, dq d and q components of the duty ratio of the top switch

Eavailable Energy available in the equivalent resonant inductor during deadtime

Eneeded Energy needed to charge the equivalent resonant capacitor to Vi during

deadtime

fs switching frequency

f0 fundamental frequency of input AC voltage/current

fc carrier frequency or switching frequency

ID amplitude of the lower terminal current

iD lower terminal current

IU amplitude of the upper terminal current

iU upper terminal current

Ia peak of the a-phase current

iD1 current through the output diode D1

iD2 current through the output diode D2

id, iq d and q components of the input current

26

List of Symbols

iLr resonant tank current

iLeq current through the equivalent resonant inductor during deadtime

iLm magnetizing current

IP peak value of inductor current

iRac reflected load current

Irms RMS value of inductor current

iS1 current through the top-switch S1 of the APWM converter

J current density of the conductor

Jn(ξ) standard Bessel function of order n and argument ξ

kfe core loss co-efficient

kw window utilization factor

L inductance value

lm magnetic path length of core

Ls boost inductor

La auxiliary inductor

lg air-gap length in the core

Llk leakage inductance of transformer

Lm magnetizing inductance of the transformer

Lr series resonant inductor

M modulation index

m, n integers representing multiples of carrier frequency and reference frequency

respectively

MD lower terminal modulation index

mi, mlo modulation index for the lower converter

mr, mup modulation index for the upper converter

MoD DC offset applied to RefD

27

List of Symbols

MoU DC offset applied to RefU

N transformer turns ratio

nind number of turns in the inductor winding

nP number of turns in the primary winding of the transformer

nS number of turns in the secondary winding of the transformer

P rated power of the transformer

Pac,in input power supplied by the AC source

Pcore core loss of inductor

Pdc,in input power supplied by the DC source

Pi,fund input power of the APWM converter based on fundamental component

of input current

Pload load power

Poff turn-off loss of switch

Pon turn-on loss of switch

Po output power

Q0 full-load quality factor of the resonant tank

RL load resistance

Rac reflected AC equivalent of the load resistance for analysis of the resonant

tank

RDS,on ON-resistance of MOSFET

RefD lower converter modulating wave

RefU upper converter modulating wave

T switching period

td deadtime between transition of switching states

tf fall-time of switch

th transient duration or hold-up time

28

List of Symbols

Tj junction temperature of MOSFET

Va peak of the phase-a voltage

va phase-a voltage

Vi input DC voltage

vAN upper converter pole-voltage w.r.t. the negative DC bus N

vCeq voltage across the equivalent resonant capacitor during deadtime

vCr voltage across series resonant capacitor

vcarr carrier waveform

Vdc DC-link voltage

vg,A1 gate pulse for the switch SA1

Vl−l line-to-line voltage

vLr voltage across series resonant inductor

vllpk peak amplitude of line to line AC input voltage

Vo output DC voltage

vpri transformer primary voltage

VP peak of primary-side voltage of the transformer

vs1 fundamental AC component of APWM pole voltage vs

VS peak of secondary-side voltage of the transformer

vs pole voltage of half-bridge leg w.r.t. negative terminal of DC source

vXN lower converter pole-voltage w.r.t. the negative DC bus N

Zin impedance of the series resonant tank at full-load condition

29

Chapter 1

Introduction

1.1 Data Centers in Modern Energy Market

With the emergence of Internet of Things (IoT), the demand for web applications and

cloud-hosted services is growing by leaps and bounds, and so is the demand for data

centers to serve them. Data center traffic is predicted to grow rapidly in the next few

years, and with it, data centers are getting larger, to the tune of tens of megawatts

of computing capacity. In some regions, data center capacity is growing at 60% per

year [1, 2].

Today’s large data centers can compete with the industrial production plants in their

functionality and power demand; in some cases carrying a downtime cost of $50,000 per

hour [3]. Globally, data centers draw somewhere near 50 GW of electricity - 40% more

than New York City on the hottest day of the year [1]. The largest of these data

centers can consume up to 20 MW of peak power – equivalent to over 6,000 homes [1].

Therefore, it is imperative to enhance the energy efficiency of the power supply system

in data centers to promote a low-carbon footprint.

Figure 1.1: Growing energy usage in US Data Centers [2].

30

1. Introduction

Figure 1.2: Energy profile of a typical Data Center in Singapore. [9].

In addition to the power supply requirements for the servers themselves, a myriad

systems support them inside a data center, which includes lighting, cooling, air-handling,

humidification, and uninterruptible power supply (UPS) systems. After servers them-

selves, cooling is by far the largest energy end use in a data center as shown in Fig. 1.2 -

it may reach as high as 50%-60% of total input power [3–7]. Not only is cooling required

for the heat generated from the Information Technology (IT) equipment, but it also

must offset the heat generated by power conversion losses. Therefore, the prime focus

of data center operations today is the reduction of its cooling requirement. A befitting

example in this context at the time of writing this thesis is ’Project Natick’ by Microsoft

that demonstrated for the first time a working prototype of sub-sea data-center serving

up data from beneath the Pacific Ocean with little forced cooling requirement [8].

The metric by which all data centers are judged, regardless of size, design, or ge-

ography, is their Power Usage Effectiveness (PUE). This metric conveys the amount of

“extra” energy input required beyond power supplied to servers to sustain a data center

during operation. Mathematically PUE is defined as (1.1).

PUE = Total Data Centre Power Consumption

Power Consumption of IT Equipment(1.1)

In general, PUE is greater than 1.0, but ideally it should be very close to 1.0. Al-

though companies like Facebook claims a PUE of between 1.08-1.10, the prevailing

market average of PUE (1.80-1.89) is way above that and there is a lot of room for

improvement there [1].

Although the level of granularity of PUE varies, the major contributors are cooling

energy and power conversion/distribution losses. Therefore, in order to achieve PUE

closer to 1.0, apart from improvement on the cooling system itself, the heating of a data

center can be reduced by improving the efficiency of the power system, which is a main

source of heat generation. As per Fig. 1.2, almost 12% of the total energy is lost as

heat in the electrical power distribution system. As a rule of thumb, each watt of heat

31

1.2. Existing Power System Topologies in Data Centers for Powering IT loads

generation removed from the data center leads to an additional 1.4 to 2 watts saved in

cooling [10].

But with the state-of-the-art power conversion technologies already implemented

inside the data centers, there is little scope of improvement of efficiency in the existing

Alternating Current (AC) based power systems of the data centers. This has triggered

the researchers to re-evaluate the power system architecture itself and recent literature

[10–17] reports that, with fewer required conversions and greater overall efficiencies,

a DC power system generates less heat than an AC system (as explained in Section

1.2), reducing data center cooling energy consumption. Moreover, with the increasing

penetration of renewable energy sources in the distribution networks, the paradigm is

bound to shift towards DC distribution for data centers as well. The clean energy sources

such as solar, fuel cell and wind can be effectively used in this case as they are easy to

integrate to a DC bus than to an AC bus. This also eliminates the problem of harmonics

since there is no need to interface the renewable sources to the AC grid. Many major

companies like Emerson, ABB, Schnider, NTT, Vicor etc. have already started their

migration from an AC based data center to a DC based data center.

1.2 Existing Power System Topologies in Data Cen-

ters for Powering IT loads

Direct Current (DC) power architecture is already a fundamental part of the IT infras-

tructure: all IT and network server loads consume DC power and all backup sources

generate it. On the contrary, the electric grid distributes AC power. So, the question be-

comes, where is the optimal point at which to convert AC to DC power while providing

suitable protection from outages? If the conversion occurs more towards the front-end,

DC power must be transmitted over long distances, which requires large conductors

to reduce losses. If it occurs in the subsequent stages of power conversion, additional

conversions are necessary which may compromise efficiency and reliability and increase

cost [10]. This section summarizes some existing power system architectures based on

the location of these conversion stages in the system.

1.2.1 AC Powered Data Centers

A typical conventional AC power supply architecture [10, 13, 14] for a data center is

shown in Fig. 1.3. The voltages shown at different stages are not universally same,

rather they vary depending on the country where the data center is located, as well as

32

1. Introduction

Figure 1.3: Typical configuration of the power supply architecture for conventional ACdata centers.

the manufacturer of the different stages of the data center.

AC is the most common type of power distribution system in data centers [4,10,13–

15,18]. The ready availability of server computers with AC adapters boosts the extensive

application of AC power distribution based data centers. However, as analyzed in [13],

the levels of AC voltages which are intermediately distributed in the data center as

shown in Fig. 1.3 can affect the overall power transfer efficiency of the whole data

center. In addition, different distribution voltage levels prompt the use of different

power distribution units (PDU), which are essentially line-frequency transformers, in

the data center distribution system [4,14,15,18]. These PDUs give rise to extra thermal

loss in the distribution systems due to increased copper and core losses.

As shown in Fig. 1.3, the three-phase-three-wire 415 V supply is fed to a double

conversion UPS and converted to a reliable three-phase-three-wire AC voltage supply.

Since each server computer is to be fed with a 240 V AC voltage, the three-phase-three-

wire AC voltage supply is converted to a three-phase-four-wire supply using a line-

frequency transformer (PDU). After this stage, the total server loads (denoted as ICT

equipment or Information and Communication Technology equipment) are distributed in

three different sets and each set is connected to one of the phase-neutral set configuration.

Within each of these ICT equipment the single-phase AC is converted to low voltage

isolated DC (12 V, 5 V, 3.3 V or 1 V) in two stages. Thus, there are four major conversion

stages from incoming AC to final DC. Because of the stochastic computation loading

of the server computers, the three-phase currents are not balanced, resulting in a huge

neutral current in the PDU. Traditionally PDU is a typical line-frequency delta-star

transformer, causing the neutral current to circulate in the delta of the PDU resulting

in unexpected heating of the PDU. It has been reported in [19] that power loss and heat

generated in feeder cables can increase by as much as 600% because of unbalanced loads.

In [7], a three-phase-four-leg UPS-inverter is proposed with a novel control strategy, so

that even in the absence of PDU, the neutral current can be eliminated under the

server IT load unbalance reducing the thermal loss inside the data center power supply.

33


However, no such commercial implementation is reported so far.

1.2.2 DC Powered Data Centers

Having discussed the issues with AC powered data centers in the previous subsection,

this subsection looks into the features of DC based power architectures for data centers.

A typical DC based power architecture is shown in Fig. 1.4(a). As can be seen, in the

DC based system, the AC to DC conversion is performed in the front-end itself.

The main advantage of utilization of DC distribution system over its AC counterpart

as discussed in the previous section is that DC does not require source synchronization as

AC does, and can integrate wind, solar, fuel cell and the grid as and when each source is

available [11]. Moreover, there are no phase balancing or harmonic issues [20] in DC sys-

tems. Most backup-energy sources, such as batteries and flywheels, are inherently DC.

Further, network and server loads run on DC, so there are fewer intermediate, efficiency-

robbing stages, along with greater reliability due to fewer potential points of failure with

a DC-based approach. DC architecture can be seen mainly in two intermediate voltage

levels of 48 V and 380 V as shown in Figs. 1.4(b) and (c) respectively.

1.2.2.1 48 V DC System

48 V DC power has a long history in telecommunication networks [10]. It is inherently

simple and reliable with few conversion stages to the point of use. 48 V DC was chosen

as the standard for two reasons:

1. DC system can be easily integrated to backup batteries during grid outages as

compared to AC system;

2. 48 V was considered the optimal trade-off between transmission distance and hu-

man safety because it is considered safe to touch during maintenance or accidental

exposure.

Today, telephone central offices (exchanges) are still powered by 48 V DC. In most

telecommunications installations, the 48 V DC power system is deployed as three distinct

elements as shown in Fig. 1.4(b):

1. 415 V AC to 48 V DC modular power system

2. Battery banks for extended run time

3. Load distribution cabinets (PDU)

34

1. Introduction

3-p

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utilit

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35


Figure 1.5: Typical architecture of 48V-rack-power-distribution for AC data centers.Source: Maxim Integrated.

These elements are connected with large copper bus bars and wires routed around the

facility to distribute power directly to 48V power supplies at the point of use. The

power supplies step the voltage down to lower DC voltages (12 V, 5 V, 3.3 V or 1 V)

for internal uses. Therefore, we see only two conversion stages in this configuration.

It is easy to see the benefits of this approach when applied to the data center.

Downstream of the AC-DC rectifiers, the power is completely isolated from the mains

and is considered “safety extra low voltage” (SELV) as per IEC/UL 60950 standard and

can be maintained live by trained personnel. In addition, there is no need to derate the

capacity to account for phase balancing or harmonics, which are not a factor with DC

power.

However, unlike telecommunications central offices, data centers are not designed

with large copper bus bars to distribute DC power to racks. A new row-based DC

topology was developed by EMERSON [10], where these large copper runs are not

necessary. In this row-based configuration, power is converted from AC to DC very

close to the point of use, which decreases the conductor size and cost.

Of late, major data center companies like Google and Facebook have come up with

the 48 V rack power architecture for AC data centers as shown in Figs. 1.5 and 1.6.

While today’s two-stage power conversion (48V-to-12V-to-load) inside the rack or the

ICT equipment is a common architecture, its efficiency has peaked at about 90% [2]. The

36

1. Introduction

Figure 1.6: Google’s 48V-rack-power-distribution for AC data center [2].

48V single conversion to the Point-of-Load or PoL (48V-to-load) eliminates one conver-

sion loss and reduces distribution power loss by a factor of 16 in a rack implementation

(connectors, cables, board) and gives up to 30% lower conversion losses, compared with

12V architectures [2]. This is significant in the sense that apart from its direct compat-

ibility to the aforementioned telecom ecosystem, it can also be easily retrofitted to the

existing AC data centers.

Nonetheless, in order to avoid the large copper bars to distribute DC power to the

racks of a data center, manufacturers are choosing an elevated DC voltage of 380 V as

discussed in the next sub-subsection.

1.2.2.2 380 V DC System

The 380 V DC system also has just two major conversion stages as shown in Fig. 1.4(c),

but there is more to the end-to-end performance metric than the number of stages alone,

as the efficiency of each stage is also critical and it has been found that the 380 V DC

approach is a better choice for distribution [20]. The 380 V DC architecture begins with

the line AC rectified to 380 V DC (nominal), with the battery backup also operating at

that voltage. The DC voltage is then distributed throughout the facility and stepped

down by local DC-DC converters to supply the loads. The system can draw on the

outside AC line, batteries, and even onsite renewable sources such as wind and solar

simultaneously or individually, in case there is a failure (such as grid outage).

It is claimed by many manufacturers that 380V DC has the best balance of economics

and safety for standardized components [21]. Intel conducted an analysis, [15] and found

that the highest overall system efficiencies are achieved with a 400 V DC system (380

37

1.3. Literature Review of Three-Phase AC-DC Power Conversion for Data CenterPower Supplies

V nominal/400 V peak); however, this technology is not yet commercially available. As

mentioned in [14], the 380 V DC distribution system in data centers is only feasible if

there are server IT loads available which can be directly connected to the 380 V DC

grid. As specially fabricated DC powered servers are not available readily in the market,

AC powered data centers are still most commonly used throughout the globe.

The good news is, the 380 V DC approach has begun to achieve industry-wide

support from critical component vendors as well as industry consortia which are devel-

oping essential standards and interoperability specifications, such as the DCG+C [DC

Components and Grid] consortium, the ITU [International Telecommunications Union]

via standard L.1200, ETSI [European Telecommunications Standards Institute] via EN

300 132-3-1, the IEC [International Electrotechnical Commission], NTT/Japan [Nippon

Telegraph and Telephone], and the IEEE.

However, it should be noted here that 380 V DC may be best suited only in the

countries using low line AC mains (210 V), like North America, Japan etc. As the line

voltage increase, the advantage of removing one AC-DC converter is diminished by using

a voltage level (~700 V DC) that needs two stage conversions.

Now that it is established that 48 V and 380 V DC are the typical DC distribution

voltages DC based data centers, a deeper look needs to be taken into the two important

converters which form the back-bone of the DC power architecture shown in Fig. 1.4.

These two converters are:

1. Three-phase AC-DC converter for generating the bus voltage of 48 V DC or 380

V DC

2. Point-of-Load (PoL) DC-DC converter inside the ICT equipment to step down the

voltage to the required voltage levels (12 V, 5 V, 3.3 V and 1 V) of the loads like

routers, network switches, microprocessors in the network servers etc.

Following sections present the literature survey on both of these two converters in light

of data center applications.

1.3 Literature Review of Three-Phase AC-DC Power

Conversion for Data Center Power Supplies

The very basic requirement of the ICT equipment (loads) in data centers are a tightly

regulated and isolated DC voltage of 48 V or 380 V. While this can be achieved by

modular implementation of single-phase AC rectification, the large current demand (≈

38

1. Introduction

Figure 1.7: Two stage AC-DC power conversion scheme.

100A per module) of these loads has pushed the industry to move towards three-phase

AC rectification that has higher power density and efficiency as compared to its single-

phase counterpart. Three-phase supply is always preferred for output power of 3 kW or

more [22] and, therefore, this review is also focused on three-phase AC-DC conversion.

Besides the requirement of tightly regulated and isolated DC output voltage, there

are two other major restrictions that are imposed by the supply mains side on the

front-end AC-DC power converter unit:

1. The input power factor should be as close as possible to unity i.e. the shape of

the input current drawn from the supply mains should tightly follow the input

voltage;

2. The Total Harmonic Distortion (THD) of the input current should be as low as

possible. It should meet the IEC/EN61000-3-2 [23] standard regarding the limits

for harmonic current emissions of three-phase rectifier systems. Commonly in the

industry, the requirement is THD<5%.

Such requirements of quality of mains current can be achieved only by means of active

power factor correction (PFC) rectifier systems. Moreover, the regulation of the output

DC voltage is only possible with active controlled rectifier topology. Thus the function

of the PFC rectifier is two-fold – shaping the input current and regulating the output

DC voltage. As for the isolation of the output DC load side from the supply mains,

it is quite obvious that the use of an isolation transformer of line frequency before

the rectification stage is not at all an economic solution. A better alternative is the

use of a DC-DC converter with a high frequency isolation transformer after the PFC

rectifier. This provides the required galvanic isolation with high power density and

superior dynamic performance in regulating the final output DC voltage as per load-side

requirement. Although the PFC rectifier can regulate the DC voltage, this regulation

is largely restricted by the supply voltage level as well as the PFC rectifier topology

used (buck, boost etc.). By introduction of this second stage of DC-DC conversion this

partially regulated DC voltage is then adapted to any load voltage level quite easily.

39


Thus the common practice for converting the utility three-phase AC to regulated

and isolated DC is a two stage conversion scheme separated by a DC link as shown in

Fig. 1.7.

• Stage1: Input PFC based AC-DC converter. This is also called as front-end PFC

rectifier.

• Stage2: High frequency isolation transformer based DC-DC converter. This is

also called as back-end isolated DC-DC converter.

It should be noted here that in order to reduce the cost, size, and complexity associated

with two-stage AC-DC power conversion and input PFC, research is still going on to

propose single-stage converters that integrate the functions of PFC and isolated AC-DC

conversion in a single power converter. Several such single-stage topologies have been

proposed in the literature, which is discussed in the forthcoming subsections of this

review. The focus of this thesis also is to develop such single-stage power solution for

data centers.

1.3.1 Two Stage Three-Phase AC-DC Power Conversion

1.3.1.1 Stage 1: Front-end PFC

Several unidirectional and bidirectional topologies have been reported in literature for

three-phase rectifiers. Bidirectional topology is needed mainly for active loads like drive

applications. The discussion here is focused on unidirectional topologies because for the

supply of purely passive loads like data center equipment, only unidirectional energy

conversion has to be provided [22]. The three-phase AC-DC rectifiers can be broadly

classified in three categories based on the nature of switches used: passive, hybrid and

active. For regulated output DC voltage as well as sinusoidal mains current behavior,

the fully-controlled active topologies are always preferred because they use exclusively

switching frequency passive filters, whereas the other two use low-frequency passive

filters for current shaping [22,24].

Another classification of the systems can be carried out with regard to the generated

DC link voltage range, i.e., fundamentally into circuits with boost-type or buck-type

characteristic. As shown in Fig. 1.8, the lower or upper output voltage limits of the DC

link are defined by the mains line-to-line voltage. Some of the other realizations based

on the DC link voltage level include buck-boost [25], Cuk [26] or SEPIC converters [27].

Extensive literature is available for all the above cases. Some popular topologies are

summarized below.

40

1. Introduction

Figure 1.8: Limits of DC link voltage for PFC rectifiers [22].

It has been elaborately explained in [22] that the direct three-phase realization of

the PFC rectifier can be achieved either by direct control of a three-phase active bridge

or by shaping the output currents of a three-phase diode rectifier on the dc side and

feedback/injection of the current difference always in that phase which would not con-

duct current for conventional passive diode rectification, i.e., as a hybrid rectifier with

third harmonic current injection. Of course both of these two realizations can be again

categorized into buck type or boost type topology with boost being the popular choice

so far.

Buck Topologies:

Some of the available buck topologies are – active six-switch buck-type rectifier [22,

24], active three-switch buck-type rectifier [22] and hybrid current injection buck-type

(SWISS) rectifier [22, 24]. The recently developed SWISS rectifier can be considered as

the buck counterpart of hybrid third harmonic current injection boost PFC rectifier.

The advantage of this circuit topology is that only a single power transistor is lying in

the main current path, resulting in very low conduction loss. In addition, the negative

output voltage terminal is always connected to the mains via a diode of the lower

bridge half of the diode rectifier. Therefore, no output common mode voltage with

switching frequency is generated, and the implementation effort of the common mode

EMI filter is thus reduced. However, neither the SWISS rectifier, nor any of the other

buck topologies has become popular yet in front-end PFC AC-DC power conversion

because of the following disadvantages.

1. For buck type three-phase AC-DC systems, typically, only the output voltage and

41


(a) Six-switch active PFC buck rectifier [22].

(b) SWISS rectifier [24].

Figure 1.9: Some of the industrially popular buck type PFC rectifiers.

42

1. Introduction

the output current is directly controlled and the mains current is not explicitly

included in a feedback loop which results in poorer performance as compared to

the boost topologies [22,28].

2. In order to meet the input current harmonic requirements the link inductor at the

output of a buck rectifier has to be very large to ensure continuous current in it

for a wide load variation.

3. Another major disadvantage of the buck type three-phase rectifier is its incompat-

ibility with universal AC input voltage (210Vrms < Vl−l < 480Vrms). For the 380

V DC power architecture as previously discussed, the buck type front-end rectifier

can be used only if the input AC main corresponds to the high line (≈ 400 V or

more), because there is an upper limit on the DC link voltage as shown in Fig.

1.8.

Boost Topologies:

Among the numerous topologies reported for boost type PFC some of the industrially

popular ones include – hybrid third harmonic current injection PFC rectifier [29,30], the

∆-switch rectifier [31, 32], the VIENNA rectifier [24, 33] and active full-controlled six-

switch rectifier [24, 28]. However, in terms of ease of implementation and performance

parameters, the third harmonic current injection PFC rectifier and the ∆-switch rectifier

cannot compete with the other two i.e. the VIENNA rectifier and the six-switch active

full-bridge rectifier.

The VIENNA rectifier [24, 33] has reduced number of active switches by using a

unique topology of a three level three-phase AC-DC boost rectifier. Also the blocking

voltage stress of the switches are half here as compared to six-switch active full-bridge

rectifier because of the split capacitor and three-level characteristics. The main drawback

of the VIENNA rectifier is the issue of voltage balancing at the common node of the

output capacitor which requires additional controller. Moreover this converter suffers

from additional conduction losses and reverse recovery losses of the increased number of

diodes that the unique topology uses. In fact this topology uses 18 diodes which should

be essentially implemented with SiC Schottky diodes to reduce the reverse recovery

losses, but considering the fact that these diodes have high conduction losses that may

deteriorate the overall efficiency of this topology.

The most common three-phase AC-DC converter is the three-phase AC-DC boost

PFC rectifier. This type of converter allows continuous conduction mode of the input

inductors. But the major drawbacks include requirement of high voltage devices (>650

43


(a) Harmonic current injection active filter rectifier [22].

(b) ∆-switch PFC rectifier [22].

(c) The VIENNA rectifier [22].

(d) Six-switch active PFC boost rectifier [22].

Figure 1.10: Some of the industrially popular boost type PFC rectifiers.

44

1. Introduction

V) for which until recently no MOSFETs were suitable. But the new 1200 V rated SiC

devices provide the enabling technology that have made it possible for these converters

to be implemented by MOSFETs. The main advantage of this approach is that there

exists no power limitation of the overall converter. Moreover the continuous current of

the input inductor simplifies the design of EMI filters.

Comparing the buck and boost topologies, it can be concluded that the conventional

six-switch boost converter is the most suitable topology for active front-end PFC rectifi-

cation. Apart from having all the advantages of a boost topology over a buck topology,

it has the least number of devices in the input current path as compared to other boost

and buck topologies.

As far as the input voltage compatibility is concerned, any three-phase boost PFC

rectifier is compatible with universal three-phase AC input voltage (210Vrms < Vl−l <

480Vrms) since there is no upper limit on the DC link voltage.

1.3.1.2 Stage 2: Back-end DC-DC converter

Since Buck-PFC is not yet industrially popular and Boost-PFC topology has a lower

limit of rectified DC voltage, the DC link voltage between the two stages of the two-stage

conversion topology is significantly high, especially for high-line input (650 V DC for

480 V AC line-to-line RMS input). Also this voltage is not fully controlled and partially

dependent on the input voltage variation. The second stage of the converter, which is

a high-frequency transformer isolated DC-DC converter [34], converts this higher DC

voltage to a regulated and isolated lower DC voltage suitable for the overall ICT loads.

In the primary side of the high-frequency transformer the DC link voltage is con-

verted into high-frequency AC voltage by use of flyback [35], forward [36, 37], half-

bridge [38–43], full-bridge [44–49] or three-level converters [50–52]. The secondary side

high-frequency AC voltage is then rectified into DC by the use of either simple diode

rectifier or synchronous rectifier depending on the maximum output current. Apart

from isolation the transformer also provides necessary step-down of DC voltage level

with appropriate turns-ratio.

The common issue with such Pulse-Width Modulated (PWM) DC-DC converters is

the loss of natural soft-switching (typically Zero-Voltage Switching or ZVS) outside of

a certain input voltage range and/or load range, which essentially limits the operating

frequency and power density of the converters. Active clamp circuits have been added

to flyback and forward PWM topologies to enable them to achieve ZVS through reso-

nance between the transformer inductances and the switch output capacitance [35–37].

45


However, the active clamp circuit have the following downfalls.

1. It requires additional active and passive components to achieve ZVS.

2. It suffers from a line- and load-dependent range of operating points for which ZVS

is achieved. At increased line voltage, or reduced load, ZVS is lost.

3. The switch voltage stress is greater than the input voltage, necessitating the need

for high voltage switches with an increased ON-resistance.

The asymmetric half-bridge [43] and the phase-shift modulated full-bridge (PSM-FB)

[49] are PWM topologies that inherently achieve ZVS and clamp the voltage stress of

their switches to the input voltage. However, they also have following limitations.

1. Like the active clamp topologies, their ZVS capabilities are lost as the load is

reduced.

2. The leakage inductance responsible for attaining ZVS is also responsible for duty-

cycle loss which affects the voltage transfer characteristics of the converter [53].

The three-level isolated DC-DC converter [50–52] is also a good choice for the second

stage of the AC-DC converter topology. Besides achieving soft-switching in a certain

range, it also enables the use of a split capacitor in DC link of the system, thereby

reducing the voltage stress on the DC link capacitors. But it requires proper switching

strategy and flying capacitor to ensure balancing of split capacitor voltages.

Recent developments in the area of isolated DC-DC converters have been primarily

focused on implementation of resonant topologies to achieve natural ZVS. These con-

verters clamp the switch voltage to the input voltage by the use of simple capacitive

output filters and have the added benefit of incorporating the parasitic circuit elements

with the resonant tank components. The resonant converters can be implemented by

variable frequency control [34,54–57] and asymmetric pulse-width modulation (APWM)

control [53, 58, 59]. In general, different resonant topologies suffer from different limita-

tions in terms of their soft-switching range, output voltage regulation capability etc [34]

and therefore, the resonant converter is still an active area of research [54–56,59–63].

1.3.2 Single Stage Three-Phase AC-DC Power Conversion

As discussed before, in a three-phase AC-DC converter there are two stages of conversion:

front-end being the PFC and AC-DC conversion stage, while the back-end accomplishes

the DC-DC conversion with isolation. In order to reduce the cost, size and complexity

46

1. Introduction

(a) Half-bridge series resonant converter [34].

(b) ZVS three-level DC-DC converter [52].

Figure 1.11: Some of the industrially popular isolated DC-DC converters.

associated with two-stage AC-DC power conversion and PFC, researchers have tried to

propose single-stage converters that integrate the functions of these two stages in a single

power converter. Several single-phase and three-phase converters have been proposed in

the literature, with three-phase converters being preferred over single-phase converters

for higher power applications [52,64–73]. Generally, they either integrate a three-phase

boost rectifier with an isolated DC-DC stage [52, 72]; or combine three single-phase,

single-stage isolated converters into a three-phase isolated converter [71].

Almost all of the single-stage AC-DC converters operate in Discontinuous Conduction

Mode (DCM) of the input current. Operation in DCM mode offers many advantages

such as reduction of turn-on switching losses and the losses associated with the reverse

recovery of the diodes, natural power factor correction, and lastly, the fast dynamic

response.

However, there are many disadvantages associated with DCM operation that restricts

the use of single-stage AC-DC converters. Some of these disadvantages are summarized

below.

1. The main disadvantage of operation in DCM is the discontinuous current wave-

forms with high peaks which gives rise to increased turn-off current of the devices

and increased Difference Mode (DM) noise [64–66]. Additionally, DCM operation

47


C1 S1

S2

S3

S4

C2

D1

D2

DR1

DR2

Lo

Vo

Naux1vabc Labc1

Labc2

Naux2

-vaux1+

-vaux2+

DB1

DB2

(a) Interleaved single-stage three-phase three-level converter [68].

S1 S2

S3S4

D1

vCR

DR1

DR2

Lo

Vo

vabc Labc +

-

D2 D3

D4 D5 D6

+

-

Taipei RectifierFull-bridge Converter

(b) Single-stage TAIPEI rectifier [64].

Figure 1.12: Some of the single-stage three-phase AC-DC converters.

is known to cause low efficiency due to increased peak to average ratio of the

current waveforms.

2. Most of the three-phase single-stage converters operating in DCM have a boost

converter input section which is integrated in to the DC-DC conversion stage

[64,67,70]. Apart from high current peaks, these converters suffer from a large low-

frequency (six times the line frequency) component at the output due to the lack

of a bulk capacitor at the primary-side DC bus. More importantly, the absence of

bulk energy storing capacitor makes these converters not-at-all suitable for Hold

Up Time (HUT) operation, which is a critical requirement for any data center

power supply. Converters that are based on buck converters do not have these

drawbacks as they have inductive-capacitive filtering in their input and output

sections and can be implemented with a bulk capacitor at their primary-side DC

bus [65, 66]. It is shown in [66] that buck-based converters can indeed operate

with lower input and output ripple than boost-based converters but at the cost of

more distorted input current at lighter loads when operating with fixed switching

frequency.

3. The design of input inductor is a a major concern for the converters operating

48

1. Introduction

in DCM because of the high peak currents. In [64], an air-gap as high as 15.2

mm between the cores is reported for design of the input inductors of a 2.7 kW

converter. Such large gap not only increases the fringing-effect-induced winding

loss, but also causes EMI issues with the neighbouring circuitry. Proper winding

strategy has to be taken to solve these problems.

4. Almost all the three-phase single-stage converters [64–70] have LC type filter at

their output. The common issue with such filters is the ringing of the rectifier diode

voltage that enforces the use of over-voltage-rated less efficient diodes and lossy

snubbers. Moreover, since the output port is a low-voltage high-current terminal

in data-center loads, the output inductor has to be designed for very high currents

which comes with its related higher conduction loss.

5. The switching frequency of these converters has to be varied in a wide range to

be within the boundary conduction mode of the input inductor currents. In [64] a

switching frequency range of 18 kHz to 300 kHz is reported. Such wide variation

not only complicates the control, but also affects the design of the filters and

magnetic components.

All of the above issues are true for high-power single-stage three-phase AC-DC converters

operating in DCM without interleaving at the front-end; but a major improvement is

possible when interleaving is employed [68, 70, 73]. Interleaving at the front-end allows

reducing the current peaks since the power is going to be equally shared among cells,

and at the same time it reduces the discontinuity in the current waveform before and

after the interleaving points, because the phase-shifted cells draw currents at different

intervals of the switching period. In [68] an interleaved single-stage three-phase AC-DC

converter is presented that reduces the current peaks to a large extent thereby making

the input and output filter design much simpler than the non-interleaved topologies.

In [70] a similar single-stage AC-DC converter based on the interleaved flyback topology

operated in DCM is proposed that achieves overall converter efficiency of 87%, which is

comparable with the two stage schemes.

However, there are two major issues related to such interleaved single-stage three-

phase AC-DC converters.

1. Such converters require active current control for balancing the power output from

the three phases [73], which may compromise the reliability of the system.

2. The device-count is increased for such interleaving and paralleling. This often

compromises the power density and efficiency.

49

1.4. Literature Review on DC-DC Power Supplies for the ICT equipment

1.3.3 Output Voltage Ripple of Three-Phase AC-DC Converters

Irrespective of single-stage or two-stage conversion from three-phase AC to DC, for high

current outputs as in data center loads, the output voltage ripple can be a major issue

since the output peak-to-peak voltage ripple needs to be maintained at less than 1% of

nominal output DC voltage [74] in data center power supplies.

For PWM converters like those proposed in [64–69, 72, 75], the output filter is es-

sentially LC type which, as discussed before, gives rise to additional voltage stress on

the output rectifier devices which enforces the use of higher voltage rated less efficient

rectifying devices and lossy snubber. If a resonant DC-DC converter is used, then pure

capacitive filter can be used which eliminates the additional voltage stress of output

rectifier [34, 53–59]. The size and ripple current stress of the output filter whether LC

or purely capacitive can be an issue if the output load current is very high (>80 A)

with a stringent voltage-ripple limit as imposed by common data center loads. In such

cases interleaved DC-DC converter can reduce the output filtering requirements. Some

literature [76–80] has shown the interleaved DC-DC converters that can be implemented

in the DC-DC stage of a two-stage AC-DC conversion scheme. But such natural inter-

leaving cannot be realized in any of the three-phase PFC single-stage AC-DC converters

reported in the literature [64–69,72].

1.4 Literature Review on DC-DC Power Supplies for

the ICT equipment

To complete the discussion on the whole power system architecture inside a DC based

data center, it is required to look into the DC-DC power conversions occurring inside the

ICT equipment as shown in Fig. 1.4. Usually the ICT equipment is fed by a 48 V DC

(telecom center) or a 380 V DC (data center) in a DC based power system architecture.

Inside the ICT equipment rack, there are variety of DC-DC converters based on the final

voltage requirement of the loads like routers, network switches, microprocessors in the

network servers etc. The common voltage levels are 48 V, 12 V, 5 V, 3.3 V and 1 V. Such

voltage levels can be achieved with a single-stage or a double-stage conversion scheme

based on the level of output voltage, output power and the required efficiency. One such

typical architecture is shown in Fig. 1.13. Irrespective of the number of conversion stages

these converters are isolated DC-DC converters and can be implemented by the standard

PWM converters like flyback [35], forward [36,37], half-bridge [38–43], full-bridge [44–49]

50

1. Introduction

IT Load380V/48V

VRM380 V

DC busIT Load

380V/12V

VRM

Network

Server

380V/12V

VRM

12V/1V

VRM

ICT equipment

Figure 1.13: Typical DC-DC conversions inside an ICT equipment (rack).

or three-level converters [50–52]; or by the DC-DC resonant converters [34, 53–59]. All

the issues with such converters are already discussed in the previous section and are

not repeated here. These converters are popularly called as point-of-use power supply

(PUPS) [53] or Point-of-Load (PoL) converters. In PUPS, as with all power converters,

the main goal is to increase power density by increasing efficiency and decreasing size

by operating at higher frequencies. Attaining ZVS for wide load range satisfies both

power-density and efficiency requirements by eliminating frequency-dependent switching

loss, which permits higher frequency operation. Usually they are operated at close to

megahertz range of switching frequency [53,58,59] to achieve very high power density.

1.5 Summary of Literature Review

In summary, following are the key findings from the above literature review, which also

set out the motivation of this thesis.

1. A three-phase PFC rectifier followed by a DC-DC isolated converter is commonly

used in a two-stage configuration for generation of room-level DC distribution

voltage (380 V DC or 48 V DC) in DC based data centers.

(a) Six-switch active front-end (AFE) boost rectifier is usually preferred in the

first stage because of its compatibility with universal three-phase input volt-

age (210Vrms < Vl−l < 480Vrms), direct input current control, and least

number of active switch count. The only limitation of this topology is the

requirement of high-voltage rated (>650 V) switches.

(b) For the second stage high-frequency-transformer-isolated DC-DC converter,

resonant topologies are gaining popularity due to their simple capacitive out-

put filter, soft-switching feature, incorporation of the parasitic elements with

the resonant tank, and limited voltage-stress on the switches. However, en-

suring soft-switching for the complete range of line and load variation is a

51

1.6. Research Objectives

210~480 V DC UPS

Battery

Load

ICT equipment

PDU

(Load distribution

cabinet)

Nine-Switch Interleaved

Three-Phase AC-DC Single

Stage Isolated Converter

APWM Half-Bridge

DC-DC Resonant

Converter

48 V

or

380 V

48 V

or

380 V

Figure 1.14: Proposed DC based power system architecture for data centers. Notethat the highlights of the system are the nine-switch interleaved three-phase AC-DCsingle-stage isolated converter and the APWM half-bridge DC-DC resonant converter.

major challenge for these converters.

2. Integration of the functions of the aforementioned two stages in a single-stage

power converter has become an active area of research recently, with the moti-

vation of reducing the cost and size associated with the two-stage AC-DC power

conversion. The progress of such research has so far been limited by the inefficient

Discontinuous Conduction Mode (DCM) of the input currents, which poses many

design challenges.

3. Irrespective of the type of output filter used (LC or only C), the size of the filter is a

major issue for high load current (>80 A) of data center loads. Interleaving of the

DC-DC converter can be a very good solution to this issue. But, such interleaving

cannot be realized in any of the single stage AC-DC converters reported so far in

the literature.

1.6 Research Objectives

Having discussed the challenges to meet the critical requirements of data center power

supplies, this research proposes a DC based power system architecture as shown in Fig.

1.14. The two main focus areas of the proposed system are as follows.

1. Achieving a single-stage AC-DC isolated conversion with interleaved

output: The front-end of the proposed system is a new three-phase AC-DC single

stage isolated converter based on the recently developed nine-switch converter

[81–84] featuring interleaving at the output DC port. This will be discussed in

Chapters 2 and 4.

2. Improving the efficiency of the PoL conversion: An APWM half-bridge

DC-DC series resonant converter topology [53, 58, 59] will be extensively used as

the PoL converters inside the ICT equipment racks. A novel design procedure for

such converters is presented in Chapter 3. It will be shown that the lower parts

52

1. Introduction

of the single-stage nine-switch AC-DC converter are three APWM Half-Bridge

(APWM HB) resonant converters and their design process is also similar.

The proposed data center power system architecture is expected to have the following

essential features.

1. Continuous input current: Despite being a single-stage AC-DC converter, the

proposed nine-switch converter will have Continuous Conduction Mode (CCM) of

the input inductor currents. This will simplify the input filter design to a great

extent and also there will be no issue of DM noise. Moreover, the converter can

operate with constant switching frequency, resulting in simpler control strategy.

2. No issues with DC bus voltage balancing: The proposed system will retain

a bulky energy storing capacitor at the intermediate DC bus. Unlike the VIENNA

rectifier, it will not use a split-capacitor configuration. So, there will be no issue

of neutral point balancing in the proposed system.

3. Complete phase interleaved three-phase DC-DC conversion: The pro-

posed nine-switch converter will implement three interleaved resonant DC-DC

converters integrated with the input PFC stage without increasing the device

count. In fact, it will have 25% less device-count as compared to its two-stage

counterpart. Being a resonant topology, it will have simple capacitive output filter

and because of the interleaving, the filter requirement will be reduced.

4. Higher efficiency and power density: Typically data center power conversion

systems has overall system efficiency of around 75% which rapidly reduces with

reduction in load [17]. It has been reported in [20] that migration to DC system

can offer an increase in efficiency of roughly about 8%-10%. This research aims to

improve on this further by reducing the number of conversion stages and number

of active switches in the converter; and also ensuring soft-switching by the incor-

poration of resonant topology. Also, till the introduction of of Wide Band Gap

(WBG) substrate based high voltage MOSFETs like SiC and GaN FETs, conven-

tionally three-phase AC-DC boost or buck converters were mostly implemented

with IGBT devices. Such devices suffer from current tailing at turn-off which

severely restricts the switching frequency to be around 20 kHz only. This limita-

tion in switching frequency restricted the maximum achievable power density of

the three-phase AC-DC converters. The recently invented WBG devices have no

such drawback and can be easily operated at higher frequency. By incorporation

53

1.7. Proposed Single-Stage Three-Phase AC-DC Converter

of resonant topology inside the three-phase AC-DC conversion stage along with

the use of WBG devices, it is expected to achieve a higher operating frequency of

the converter , which will reduce the size of the magnetics and improve the power

density.

5. Higher ambient temperature: One of the main factors influencing the cooling

requirements of the data center power system components especially the power

converters are the strict limitation of their maximum operating ambient temper-

ature which is typically 550C. It is very much evident that if this maximum

operating temperature is increased typically up to 750C, then there can be sig-

nificant reduction in cooling requirement or the cooling load imposed by the data

center equipment. Presently most of the power converters used to power data

center loads are designed and manufactured with Si based power devices with

maximum allowable junction temperature being around 1250C. Of late, SiC and

GaN based power devices (the WBG devices) able to operate at junction temper-

atures close to 2000C are becoming more and more prominent. This will allow

the data center to be operated at higher ambient temperature thereby reducing

cooling requirements.

6. Extended ZVS range of PUPS converters: Most resonant converters, be

it frequency controlled or duty ratio controlled, have a limited ranges of input

voltage and load variation where it features natural ZVS (although these natural

ZVS ranges are wider than equivalent PWM converter). To extend these ranges

some auxiliary active or passive circuitry are needed. This research aims to provide

a novel design of the APWM half-Bridge DC-DC resonant converter that will have

natural ZVS over the complete range of input voltage and load variation without

the use of any auxiliary circuitry. These converters are expected to increase the

overall efficiency and power density of the PUPS converters.

1.7 Proposed Single-Stage Three-Phase AC-DC Con-

verter

In order to properly explain the organization of the thesis, the proposed topology should

be introduced at this point. Fig. 1.15 shows the proposed nine-switch interleaved three-

phase AC-DC single stage isolated converter, which is the heart of this thesis.. For

convenience, it is assumed that the converter is composed of a “three-phase AFE boost

54

1. Introduction

SA SB SC

SAX SBY SCZ

SZSYSX

Cdc

Ls

Lr

vS

+

Vdc

-

AB

C

ZY

X

N

P

CoRL

+

Vo

-

Cr

Figure 1.15: Proposed nine-switch converter based single-stage three-phase AC-DC con-verter.

SA SB SC

SA’ SB’ SC’

Cdc

LsvS

+

Vdc

-

AB

C

N

P

Lr

Co RL

+

Vo

-

Cr

SX’ SY’ SZ’

SX SY SZ

XY

Z

Figure 1.16: Two-stage twelve-switch back-to-back (BTB) equivalent of the proposednine-switch converter based single-stage three-phase AC-DC converter.

PFC rectifier” and three “half-bridge DC-DC resonant converters” as shown in Figs.

1.17(b) and 1.17(c) respectively. They are also referred as the “upper converter” and

the “lower converters” respectively. The three middle switches are shared between these

two converters. The boost PFC section, controlling the input power factor and the

DC-link voltage Vdc, consists of the upper three switches SA,B,C along with the OR-

ed combination of the middle three switches SAX,BY,CZ and the bottom three switches

SX,Y,Z . Similarly the three half bridge DC-DC converters are comprised of SX,Y,Z along

with the OR-ed combination of SAX,BY,CZ and SA,B,C . This is illustrated clearly in Fig.

1.17.

Since the three DC-DC converters are connected in parallel to the load, the use of

three phase shifted carrier signals, as proposed in this thesis, imposes three high fre-

quency phase shifted PWM waveforms of magnitude Vdc across the three resonant tanks

consisting of series inductor Lr, series capacitor Cr and the magnetizing inductance Lm

of the transformer. Thus, a parallel operation of three interleaved half-bridge DC-DC

resonant converters is realized, each of which can be controlled either by the frequency

or by the duty cycle of the uni-polar PWM waveforms vXN,Y N,ZN . It will be shown in

Chapters 3 and 4, that this work adopts the duty cycle control which is also known as

the asymmetric pulse-width modulation (APWM) control [53,58,59].

As evident from the above discussion, the proposed converter integrates a three-

55

1.7. Proposed Single-Stage Three-Phase AC-DC Converter

SA

SB

SC

SA

XS

BY

SC

Z

SZ

SY

SX

Cd

c

LsL

r

vS

+Vd

c

-

AB

CZY

X

N P

Co

RL

+Vo

-

Cr ia

ix

iSA

iSA

X

iSX

SA

SB

SC

SA

XS

BY

SC

Z

SZ

SY

SX

Cd

c

Ls

vS

+Vd

c

-

AB

C

N P

iaSA’

SB’

SC’

SA

SA

X

SX

Cd

cL

r

+Vd

c

-X

N P

3RL

+Vo

-

Cr

ix

SX’

=+

3

(a)

(b)

(c)

13C

o

Figure1.17:

Proposedsingle-stage

AC-D

Cconverter

andits

decomposition

intoathree-phase

boostPFC

rectifierand

threehalf-bridge

DC-D

Cresonant

converters.

56

1. Introduction

phase active front-end (AFE) boost PFC rectifier and three phase-interleaved APWM

half-bridge DC-DC resonant converters in a single stage. In a conventional two-stage

configuration as shown in Fig. 1.16, this integration requires twelve switches, which

implies that the proposed converter yields a 25% saving in device count. A novel three-

carrier modulation technique is also introduced for controlling both the PFC stage and

the interleaved DC-DC stage. Thus the output voltage ripple is reduced by 67% without

any additional hardware for modulation and control. It has been shown in this thesis

that the choice of sawtooth carrier wave over triangular carrier wave leads to reduced

switching loss for this converter. Moreover, despite being a single-stage topology, the

PFC stage of the converter operates in Continuous Conduction Mode (CCM), and thus

eliminates all the issues related to DCM.

1.8 Organization of the Thesis

This report is organized into four more chapters and two appendices. Chapter 2 starts

with the an overall review of the nine-switch converter and its basic operation. The pri-

mary issue with the switching of three switches in a leg is identified and the modulation

scheme is explained in the different modes of operation of the converter. It then moves

on to review the low loss areas (LLAs) of the nine-switch converter for different modes

of operation, which indicate the application areas where the nine-switch converter has

relatively lower losses as compared to the twelve-switch back-to-back (BTB) converter.

It is found that only the load-source combination for the AC-AC Common Frequency

(AC-AC CF) mode and the source-source combination for the AC-DC Different Fre-

quency (AC-DC DF) mode have been reported, so far, to yield relatively lower loss for

the nine-switch converter. Chapter 2 shows that the nine-switch converter can have

relatively lower loss even with a load-source combination, instead of only source-source

combination in its AC-DC DF mode – when the upper terminal is connected to a DC

load and the lower terminal is connected to an AC source. This configuration also meets

all the requirements of a non-isolated AC-DC power supply for data center loads. Math-

ematical proof is presented with derivation of the particular operating parameters for

which the nine-switch converter will have comparatively lower losses. The analysis is

validated with simulation and experimental results from a 1 kW non-isolated power con-

verter prototype for data center loads. Results are presented for different cases of load

sharing to indicate the most efficient load sharing conditions. Finally, the benchmark

of the application criteria of the nine-switch converter for having lower conduction loss

57

1.8. Organization of the Thesis

than the BTB converter is updated in Chapter 2.

Even though the lower converters of the proposed nine-switch single-stage AC-DC

converter are using the standard APWM half-bridge series resonant topology, this the-

sis proposes a novel design methodology of the APWM HB series resonant converter

with magnetizing current assisted ZVS. This design had to be presented in Chapter 3

so that the design equations developed in Chapter 3 can be straight-away referred to

when designing the lower converters of the proposed nine-switch converter in Chapter 4.

After discussing the steady-state operation of the APWM HB resonant converter with

detailed modes of operation, Chapter 3 indicates the behaviour of the circuit at certain

instants of the switching period which will lead to the proposed novel design procedure

of the converter. Empirical formulae are derived to design the resonant network and

the magnetizing inductance of the high-frequency transformer systematically in a flow-

chart based manner. The proposed design is then validated using simulations as well

as experiments and is compared with a reference APWM HB series resonant converter

design that uses an auxiliary LC circuit for ZVS.

To validate that the proposed novel design methodology of the APWM HB series

resonant converter presented in Chapter 3 is applicable irrespective of input voltage,

output voltage, rated power and operating frequency of the converter, a step-up con-

verter was built using the APWM HB series resonant topology to interface the Photo

Voltaic (PV) modules to the 380 V DC bus of the data centers. This work is presented

in Appendix A. The design procedure of this converter is exactly the same as that of

the PoL converter presented in Chapter 3. Therefore, without repeating the design sec-

tion, only the performance of the converter is studied in Appendix A by presentation of

simulation and experimental results.

Chapter 4 introduces the proposed nine-switch single-stage three-phase AC-DC con-

verter. First, the basic operation of the proposed converter is explained with the pro-

posed novel three-carrier modulation scheme. It is shown that such modulation scheme

leads to interleaved operation of the three DC-DC resonant converters integrated within

the proposed topology resulting in low output DC voltage ripple. Then the design pro-

cedure of the converter is presented including the design of the controllers. Justification

is provided for the choice of SiC MOSFET as the enabling technology for the converter

along with the identification of soft-switching areas of the switches in a line-cycle, and a

theoretical loss analysis of the converter. Chapter 4 also validates the choice of sawtooth

carrier over triangular carrier for the nine-switch converter. Proposed system with the

modulation scheme is validated with 1.5 kW laboratory prototypes and results are pre-

58

1. Introduction

sented for both 48 V DC output and 380 V DC output. A cost comparison between the

proposed nine-switch single-stage converter and its equivalent two-stage twelve-switch

BTB converter is also presented in Chapter 4.

Chapter 5 delves a little deeper into the proposed three-carrier modulation, mostly

to find out its impact on the harmonics of the three-phase input currents. It starts

off with the development of the mathematical expressions for the complete harmonic

solutions of the pole voltages with three-carrier modulation for different scenarios of

natural sampling and regular sampling. The THD performance is then compared with

the standard single-carrier modulation scheme for each case. Finally, the use of the

proposed three-carrier modulation in the proposed nine-switch single-stage converter is

validated in Chapter 5.

Chapter 6 concludes the thesis. It briefly states the focus areas and then discusses

the proposed solutions. It also lists the possible future works in this line of research.

1.9 Contributions of the Thesis

The contributions of this thesis can be summarized in the following three points.

1. A novel SiC-based nine-switch interleaved three-phase AC-DC single-

stage isolated converter: This converter integrates a three-phase active front-

end (AFE) boost PFC rectifier and three phase-interleaved half-bridge DC-DC

resonant converters in a single stage. In a conventional two-stage configuration

this integration requires twelve switches, which implies that the proposed converter

yields a 25% saving in active switch count. Moreover, despite being a single-stage

topology, the PFC stage of the converter operates in Continuous Conduction Mode

(CCM), and thus eliminates all the issues related to the Discontinuous Conduction

Mode (DCM). A novel modulation scheme using three separate 120 phase shifted

high frequency carriers for the three legs of the proposed converter is developed to

drive the switches. It is shown that such modulation scheme leads to interleaved

operation of the three DC-DC resonant converters integrated within the proposed

topology resulting in 67% lower output DC voltage ripple than the conventional

two-stage configuration. It is shown that the choice of sawtooth carrier wave over

triangular carrier wave leads to reduced switching loss for this converter. Justifica-

tion is also provided for the choice of SiC MOSFET as the enabling technology for

the converter along with the identification of soft-switching areas of the switches

in a line-cycle. Proposed converter with the modulation scheme is validated with

59

1.9. Contributions of the Thesis

1.5 kW laboratory prototypes and results are presented for both 48 V DC output

and 380 V DC output, which meet the Energy Star 80PLUS platinum efficiency

standard, making them potential candidates for data-center loads. A comparison

of cost of manufacturing between the proposed nine-switch single-stage converter

and its equivalent two-stage twelve-switch BTB converter shows 21.4% savings in

case of the proposed nine-switch single-stage AC-DC converter.

2. A novel APWM half-bridge DC-DC series resonant converter with nat-

urally extended ZVS range: The proposed converter uses the magnetizing

current of the transformer and eliminates the need of extra components (like LC

network) that are otherwise used in APWM half-bridge series resonant converter

for ensuring zero-voltage switching (ZVS) over wide range of line and load varia-

tion. The converter with the proposed design methodology operates at the reso-

nant frequency of the tank and features load-independent ZVS for a wide range

of input voltage variation with minimal magnetizing current. Empirical formulae

are derived to design the resonant network systematically in a flow-chart based

manner. A new optimal method of design of the magnetizing inductance of the

high-frequency transformer is also presented, which can be extended to a stan-

dard LLC converter as well. The proposed design is validated using simulations as

well as experiments and is compared with a reference APWM HB series resonant

converter design that uses an auxiliary LC circuit for ZVS. Two separate experi-

mental prototypes of the two converters rated for 30W, 48V/5V with a switching

frequency of 500 kHz were built and tested in the laboratory. It is shown that

the converter with the proposed design methodology, apart from having lower

component-count, is about 3% more efficient than the reference topology at the

rated power. This design procedure has been used for the PoL converters inside

the ICT equipment, as well as for the lower converters of the proposed nine-switch

single-stage AC-DC converter.

3. Benchmark of application criteria of the nine-switch converter for re-

duced conduction loss: The nine-switch converter is a multi-port converter hav-

ing two three-phase terminals and a DC link, just like a twelve-switch back-to-back

(BTB) converter, but with 25% reduction of active switch count. However, the

reduction from twelve-switch to nine-switch may not always be an efficient choice

considering losses in the switches. Only the load-source combination for the AC-

AC Common Frequency (AC-AC CF) mode and the source-source combination for

60

1. Introduction

the AC-DC Different Frequency (AC-DC DF) mode have been reported, so far, to

yield relatively lower loss for the nine-switch converter. This work has shown that

the nine-switch converter can have relatively lower loss even with a load-source

combination, instead of only source-source combination in its AC-DC DF mode

– when the upper terminal is connected to a DC load and the lower terminal

is connected to an AC source. Mathematical proof is presented with derivation

of the particular operating parameters for which the nine-switch converter will

have comparatively lower losses. The analysis is validated with simulation and

experimental results of a 1 kW system. Results are presented for different cases

of load sharing to indicate the most efficient load sharing conditions. Finally, the

benchmark of the application criteria of the nine-switch converter for having lower

conduction loss than the BTB converter is updated in this thesis.

1.10 Summary

This chapter introduces the importance of reduction of heat generation, especially from

the power systems inside the data center, by improving the efficiency of the power

converters used. Stringent requirements of the power supplies for data center loads are

identified and it is shown that migration towards a DC based power architecture can be

promising because of reduction of number of conversion stages and the absence of phase

balancing or harmonic issues of the AC systems. A literature review is then carried out

for the three-phase PFC rectifiers and the isolated DC-DC converters – the two stages

commonly used for converting the utility three-phase AC to regulated and isolated DC

in a two stage conversion scheme. Thereafter, the existing single-stage converters, that

integrate the functions of these two stages in a single power converter, are introduced;

and the problems related to their operation, especially with the inefficient Discontinuous

Conduction Mode (DCM) are discussed. This sets the background and the motivation

of this work, which then leads to the research objectives and the introduction to the

proposed solutions in this thesis. Finally, the main contributions of this thesis are listed.

61

Chapter 2

The Nine-Switch Converter –

Review and Benchmark of

Application

Before going into the detailed design and implementation of the proposed single-stage

nine-switch AC-DC converter, it is necessary to review of the basic operation of the

nine-switch converter. This chapter discusses the issues of modulation and switching

of the nine-switch converter in general. It then moves on to review the low loss areas

(LLAs) of the nine-switch converter for different modes of operation, which indicate the

application areas where the nine-switch converter has relatively lower losses as compared

to the twelve-switch back-to-back (BTB) converter. In this regard, this chapter adds

a special application criterion to the benchmark of the set of application criteria and

shows that it can be used to develop a non-isolated power supply for data center loads.

2.1 Introduction

The nine-switch converter is a multi-port converter having two three-phase terminals

and a DC link, similar to a twelve-switch back-to-back (BTB) converter, but with 25%

reduction of active switch count (refer to Figs. 2.1 and 2.2). Despite being a relatively

new topology (first introduced in 2007 [81]) it has found variety of applications like

independent control of two three-phase induction motors from the same DC source [81,

85], three-phase AC-AC UPS [86], three-phase AC-AC power conditioner [83], AC-DC

renewable system [84,87], compact electric vehicle (EV) drives [88,89], dual transformer-

62

2. The Nine-Switch Converter – Review and Benchmark of Application

less hybrid power filters [90], wind energy conversion system [91], as well as topology

variations, such as dual-output matrix converters [92], a family of multi-port dc-ac

converters [93] and dual-output Z-source inverters [94] etc. However, the reduction in

number of switches from twelve to nine is not always more efficient as it is expected

to be. In fact, in most of the cases the BTB converter is still preferred because of its

relatively lower loss, not to mention about its ease of modulation and control. One of

the themes of this chapter is to find out those application criteria where the nine-switch

converter is more efficient than the BTB converter, and set a benchmark. Then only

the 25% savings in active switch count can be considered as beneficial without making

any trade-off.

The primary issue in a nine-switch converter is the sharing of the middle switches by

the upper and the lower halves of the converter, which gives rise to a switching constraint

that requires the upper terminal modulation reference to be always placed above the

lower terminal modulation reference [81, 82, 84, 86, 95–97]. This forces the modulation

indices to be less than 1, causing the increase of switching frequency harmonics in the line

current (in case of sinusoidal pulse width modulation), as well as increase of the DC link

voltage. The effect is most severe in AC-AC Different Frequency (AC-AC DF) mode,

where either of the two modulation indices has to be less than 0.5, which means the DC

link voltage may be more than double of what it is in case of the BTB converter [88,95].

These disadvantages are avoided to a large extent in case of AC-AC Common Frequency

(AC-AC CF) mode and AC-DC Different Frequency (AC-DC DF) mode of operations,

where at least one of the modulation indices can be very close to 1. However, the AC-

AC CF and AC-DC DF modes of the nine-switch converter do not always give better

efficiency as compared to the BTB converter. But, the cause for that is not very well

documented in literature and there is a substantial research gap in the loss modeling

of the nine-switch converter. Few papers [87,95,98] have addressed this issue indirectly

by comparing the current stresses on the switches of the nine-switch converter with

that of the BTB converter. In [95], a mathematical comparison of the losses in the two

converters is developed by investigating the switch currents for different applications, as

well as for operating parameter variations in any particular application. It has clearly

shown the Low Loss Areas (LLAs) of the nine-switch converter for different application

criteria. Based on the conclusions of [95], the application criteria of the nine-switch

converter for having an LLA can be listed as shown in Table 2.1.

However, the conclusions drawn in [95] are not completely exclusive. In particular,

it has been clearly concluded in [95] that in AC-DC DF mode, the upper and lower

63

2.1. Introduction

Table 2.1: Application Criteria of Nine-Switch Converter for Existence of LLA as perQIN et al.

Mode of Operation Upper terminal connected to Lower terminal connected to

AC-AC Common Frequency (CF) Source LoadLoad Source

AC-DC Different Frequency (DF) AC Source DC Source

terminals of the nine-switch converter have to be connected to an AC source and a DC

source respectively, in order for the converter to have an LLA, and hence, relatively

lower conduction loss as compared to the BTB converter. It is imperative to mention at

this point that, in all the AC-DC DF applications of the nine-switch converter reported

so far [84, 87, 95, 98, 99], the upper terminal is always connected to an AC source/load,

and the lower terminal to a DC source/load. The other possibility of AC-DC DF mode

with the upper terminal connected to a DC source/load, and the lower terminal to

an AC source/load, remains completely unexplored. This chapter investigates the loss

comparison in these possible combinations of source and load, and shows that the nine-

switch converter can have relatively lower losses as compared to its BTB precedence, if

the upper terminal is feeding a DC load and the lower terminal is drawing power from

an AC source.

It is interesting to note that the above-mentioned load-source configuration meets

all the requirements of a non-isolated AC-DC power supply for data center loads. A

380 V DC data-center load connected to the upper terminal can be fed in parallel from

a three-phase AC grid (120 V rms-phase-voltage) connected to the lower terminal and

a DC source (400 V DC) connected to the DC-link [15] (refer to Fig. 2.13). Results

from a 1 kW laboratory prototype shows that this configuration achieves 25% saving in

switch count along with 0.4% more efficiency than the BTB converter.

Thus, the main contribution of this chapter is to show that the nine-switch converter

can have relatively lower losses than the BTB converter even with a load-source com-

bination, instead of only source-source combination, for the upper and lower terminals

in its AC-DC DF mode. First, a brief description is presented on the basic operation,

modulation and control of the nine-switch converter. Each mode of operation is then

identified and is discussed in light of the losses as compared to the BTB counterpart.

Following the mathematical analysis and the experimental validation, a benchmark is

finally established for the application criteria of the nine-switch converter with lower

conduction loss than the BTB converter.

64


SA1

iSA1

Upper Source

or Load

SA2

SA3

iSA2

iSA3

Lower Source

or Load

DC-link

Source or

Load

iU

iD

P

N

AB

C

ZYX

Vdc

+

_

Figure 2.1: Schematic of a nine-switch converter.

SA1'

SA2’

iSA1'

iSA2'

Upper Source

or Load

SA2'’

SA3’

iSA2'’

iSA3'

Lower Source

or Load

DC-link

Source or

LoadiU

iD

P

N

AB

C

XY

Z

Vdc

+

_

Figure 2.2: Schematic of a twelve-switch back-to-back (BTB) converter.

2.2 Topology, Modulation and Control of the Nine-

switch Converter

The nine-switch converter was first proposed as a reduced-switch-replacement of the

twelve-switch back-to-back (BTB) converter to drive two separate three-phase induction

motors from the same DC-link [81, 85]. Figs. 2.1 and 2.2 show the generic topologies

of the nine-switch converter and the BTB converter respectively. It is clear that the

nine-switch converter has only three legs with three switches installed on each of them;

whereas, the BTB converter has six legs with two switches on each of them. For conve-

nience, we shall assume that both the converters are composed of an “upper converter”

and a “lower converter”, as has been done in most literature, and as shown in Figs.

2.1 and 2.2. The novelty of the nine-switch converter is that the middle switch in each

individual leg is shared by both the upper converter and the lower converter, thereby

reducing the switch count by 25% in comparison to the BTB converter.

65

2.2. Topology, Modulation and Control of the Nine-switch Converter

Table 2.2: Switching States of BTB Converter

Switching state S1′ S2′ S2′′ S3′ vAN vXN

1 On Off On Off Vdc Vdc2 Off On Off On 0 03 On Off Off On Vdc 04 Off On On Off 0 Vdc

Table 2.3: Switching States of Nine-Switch Converter

Switching state S1 S2 S3 vAN vXN

1 On On Off Vdc Vdc2 Off On On 0 03 On Off On Vdc 0

2.2.1 Switching constraint

The reduction of the number of switches in the nine-switch converter topology imposes

certain switching constraints for the switching pattern design. In the BTB converter

shown in Fig. 2.2, the upper converter pole-voltage vAN , which is the voltage at node

A with respect to the negative DC bus N , can be controlled by switches SA1′ and SA2′

of the upper converter, whereas the lower converter pole-voltage vXN can be controlled

by SA2′′ and SA3′ of the lower converter. This means that the two pole-voltages of the

same leg in BTB converter can be controlled independently. The BTB converter has

four switching states per phase, as defined in Table 2.2.

For the nine-switch topology, the control of the two pole-voltages has to be accom-

plished through the three switches on each leg. Because the middle switches are shared

by the upper and the lower halves, the nine-switch converter has only three switching

states per phase, as listed in Table 2.3. It can be observed that switching state 4 for the

BTB converter does not exist in the nine-switch converter, which implies that the lower

converter pole-voltage vXN cannot be higher than the upper converter pole-voltage vAN

at any instant. The simple reason is the presence of the DC-link across the legs with its

positive terminal P nearer to nodes A − B − C, and its negative terminal N nearer to

nodes X−Y −Z. This is, in fact, the main constraint for the switching scheme design of

the nine-switch converter, irrespective of its application and the modulation technique

used [82–84,86–88,95,96,100].

To comply with the aforementioned switching constraint in case of carrier-based

continuous PWM schemes, such as sinusoidal PWM (SPWM), space vector PWM

(SVPWM), and third-harmonic injection PWM (THIPWM), the upper terminal mod-

ulation reference has to to be always placed above the lower terminal modulation ref-

66


erence. Additionally, to prevent short-circuit of the DC bus, the middle switches of the

legs have to be fed with the XOR-ed combination of the gate pulses of the top and the

bottom switches.

Fig. 2.3 illustrates the generalized carrier-based modulation scheme for the nine-

switch converter. The upper converter modulating wave RefU and the lower converter

modulating wave RefD are arranged such that RefU is not lower than RefD at any

instant of time. These two modulating waveforms are compared with a common trian-

gular carrier. It can be seen that two modulation references RefU and RefD has been

used to generate the gate pulses for the top switch and the bottom switch respectively,

while the gate pulse for the middle switch is generated by the XOR combination of the

top and bottom switch gate pulses. Mathematically

vg,A2 = vg,A1 ⊕ vg,A3. (2.1)

The generated pole-voltages vAN and vXN are also shown in the figure. This ar-

rangement guarantees that switching state 4 of the BTB converter is eliminated here for

the nine-switch converter. Also, the insertion of dead times to protect the nine-switch

converter against any accidental short-circuit of DC-link is automatically taken care of

by the XOR-ing process, as long as proper dead times are inserted to vg,A1, vg,A1′and

vg,A3, vg,A3′, as per controlling a normal Voltage Source Inverter (VSI).

2.2.2 Modes of operation

While the DC-link of the nine-switch converter is always connected to a DC source/load,

the source/load connected to the upper and the lower terminals of the converter can be

either AC or DC. Based on such connections, the nine-switch converter can have the

following three modes of operation. These modes are also demonstrated in Fig. 2.4.

1. AC-AC Common Frequency (AC-AC CF) mode, where both the source/load con-

nected to the upper and the lower terminals are AC, and the fundamental frequen-

cies of their voltage/current are same.

2. AC-AC Different Frequency (AC-AC DF) mode, where both the source/load con-

nected to the upper and the lower terminals are AC, and the fundamental frequen-

cies of their voltage/current are different.

3. AC-DC Different Frequency (AC-DC DF) mode, where either one of the upper

and the lower terminals is connected to an AC source/load and the other terminal

67


RefU

RefD

Carrier

+

-

+

-

Top switch

RED = Rising Edge Delay

RED

RED

RED

RED

U = A, B, C D = X, Y, Z

RefU

1

-1

0

vg,A1

vg,A2

vg,A3

vAN

vXN

RefD

Carrier

Vdc

Vdc

Middle switch

Bottom switch

t1 t2 t3 t4 t5 t6

Figure 2.3: Generation of gate pulses for one leg of the nine-switch converter. Insertionof dead times to protect the nine-switch converter against any accidental short-circuitof DC-link is also automatically taken care of by the XOR-ing process, as long as properdead times are inserted to vg,A1, vg,A1′and vg,A3, vg,A3′, as per controlling a normalVoltage Source Inverter (VSI).

68


Nine-switch

converter + _

Nine-switch

converter

Nine-switch

converter

Nine-switch

converter

Nine-switch

converter

+ _

(a) AC-AC Common Frequency mode

(b) AC-AC Different Frequency mode

(c) AC-DC Different Frequency mode

Figure 2.4: Different modes of operation of the nine-switch converter based on theload/source connected to the terminals.

is connected to a DC source/load.

While the focus of this thesis is the AC-DC DF mode for designing AC-DC converter,

the modulation schemes for all of the aforementioned modes are discussed here, in order

to emphasize the significance of the AC-DC DF mode for applications in data centre

loads.

2.2.2.1 AC-AC Common Frequency (AC-AC CF) mode

Fig. 2.5 illustrates the SPWM modulation scheme for AC-AC CF mode of operation,

where mr and mi are the modulation indices for the upper and the lower converters

respectively. Note that, unlike the BTB converter, both the modulating waves here

are compared to a common triangular carrier wave. The gate signals are generated at

the waveforms’ intersections with the carrier. To prevent the modulating waves from

intersecting each other, the upper converter’s modulating waves are lifted to the top,

whereas the lower converter’s modulating waves are pushed to the bottom by adding

proper DC offsets. In this way, the switching constraints of the nine-switch converter

are satisfied. If the upper converter’s modulating wave is set in phase with the that

of the lower converter, as in the case shown in Fig. 2.5, both the modulation indices

69


RefURefD

Figure 2.5: SPWM scheme for CF-mode operation of the nine-switch converter [82].

can simultaneously reach a maximum of unity. The CF-mode operation is particularly

suitable for applications in UPS [86].

2.2.2.2 AC-AC Different Frequency (AC-AC DF) mode

Fig. 2.6 shows the SPWM modulation scheme for the AC-AC DF mode mode of opera-

tion. In this case, the upper converter’s modulation index and phase angle can both be

adjusted independently from those of the lower converter. In order to satisfy the switch-

ing constraint discussed earlier, the sum of the two modulation indices mr and mi must

not exceed 1. The AC-AC DF mode can be applied to variable-speed drives [81, 85].

For matching the input and output ratings, we limit both the maximums of mr and mi

to 0.5. It can be observed from Fig. 2.6 that both the modulating waves can only be

adjusted within half of the carrier’s magnitude (which represents the DC-link voltage);

therefore, the DC-link voltage Vdc of the converter is twice as high as the rated DC volt-

age of a BTB converter with the same AC ratings. This is different from the situation

of the CF mode with identical upper converter and lower converter phases, in which the

DC-link voltage of the converter can be tightly controlled and maintained at around its

rated value.

It should be noted that although the added DC offsets guarantee that the instant

value of RefU is always higher than that of RefD , they are of zero sequence in the

three phases and have no effect on the input/output ac magnitudes.

2.2.2.3 AC-DC Different Frequency (AC-DC DF) mode

This mode can be thought of as a particular case of the AC-AC DF mode where one

of modulating waves is a DC signal as shown in Fig. 2.7. This mode has been used in

AC-DC renewable systems [84, 87]. Since the voltages of the DC renewable sources are

70


RefU

RefD

Figure 2.6: SPWM scheme for DF-mode operation of the nine-switch converter [82].

RefU

RefD

Figure 2.7: SPWM scheme for AC-DC-DF mode operation of the nine-switch converter[87].

low, the lower modulation index can be as low as 0.2 which means the upper modulation

index can be as high as 0.8. Therefore this mode also has the advantage of controlled

DC-link voltage (albeit higher than a BTB converter).

2.2.3 Space Vector PWM

To better utilize the DC-link voltage and improve the THD of the three-phase line

currents in a three-phase rectifier-inverter system, many alternative carrier-based con-

tinuous PWM schemes, such as space vector PWM (SVPWM), and third-harmonic

injection PWM (THIPWM), are well established in the literature [101]. The principles

of these methods can all be applied to the nine-switch converter but a little modification

would be necessary, because when designing the switching pattern for the nine-switch

converter, the switching constraints discussed earlier must be satisfied.

Although there is enough literature available for SVM in case of nine-switch con-

verter [96, 100], which shows long and complex switching tables, essentially it can be

implemented with two synchronized standard SVM for the upper and the lower con-

verter and the gate pulse for the middle switch generated by the XOR of top and

71


RefU

RefD

D

SA

SB

SC

SA’

SB’

SC’

SX

SY

SZ

SX’

SY’

SZ’

SA

SB

SC

SX

SY

SZ

SAX

SBY

SCZ

Figure 2.8: Modular Space Vector Modulation (SVM) for the nine-switch converter [100].

bottom switch pulses. The same has been depicted in Fig. 2.8. This is possible because,

no matter what, the modulation technique has to comply with the switching constraints

discussed before, which kind of decouples the upper converter and the lower converter.

2.2.4 Control

As shown in Fig. 2.3, the XOR implements the time-multiplexing of the states of the

middle switches. For example, for the time segment [t1, t4] when switch S1 is ON, all

that is needed is node A in Fig. 2.1 should not connect to node N (i.e. the negative

DC bus), and for that it is enough to have either switch S2 or switch S3 in OFF state,

which is ensured as seen in Fig. 2.3 (S2 is OFF for the time segments [t1, t2] and [t3,

t4]; and S3 is OFF for the time segment [t2, t3]). So the fundamental component of vAN

is exactly of the shape of RefA and not at all affected by the XOR operation. Similar is

true for the lower converter. For the time segment [t3, t6] when switch S3 is ON, node

X should not connect to node P (i.e. the positive DC bus), and for that it is enough to

have either of S1 and S2 in OFF state, which is ensured. So the normalized average of

vXN is exactly equal to RefX as desired. This is to emphasize that the XOR does not

impose any coupling between the upper converter and the lower converter and they can

be controlled independently [82,83,87,88].

The control implementation for the proposed nine-switch single-stage three-phase

72


RefU

1

-1

0

vg,A1

vg,A2

vg,A3

RefD

Carrier

Figure 2.9: Modulation of the nine-switch converter.

AC-DC converter has been elaborated more in Chapter 4.

2.3 LLA of Nine-Switch Converter for Different Modes

of Operation

As discussed in the introduction, one of the key findings of this chapter is a special

application criterion for which the nine-switch converter has relatively lower losses as

compared to the BTB converter. An application criteria is determined to be suitable

for the nine-switch converter based on the existence of the Low Loss Areas (LLAs) [95].

This section briefly reviews such LLAs in different modes of the nine-switch converter,

before introducing the new application criterion in the next section.

The LLAs of the nine-switch converter can be identified by studying the current

stresses on its switches as compared to those in the BTB converter, as has been done

in [95]. For ease of comparative discussion, some of the diagrams are redrawn here

from [95]. The well-established modulation technique [83, 84, 86, 87, 95] of the nine-

switch converter for generation of gate pulses for the switches of leg-a using a sawtooth

carrier wave is shown in Fig. 2.9. The instantaneous switch currents for one-to-one

mapped switches of the two converters are tabulated in Fig. 2.10. Note that switch

SA2 of the nine-switch converter, instead of a single equivalence, is mapped to SA2′ and

SA2′′ of the BTB converter. Also, unlike switches of the BTB converter which carry

one terminal current (iU or iD) each, switches SA1 and SA3 of the nine-switch converter

carry both terminal currents simultaneously (±(iU + iD)). Their combined currents can

hence be either higher or lower than the individual currents depending on their relative

frequency, phase, and amplitude.

73

2.3. LLA of Nine-Switch Converter for Different Modes of Operation

RefU

1

-1

0

iSA1

RefD

Carrier

T1 T2 T3

T

iSA2

iSA3

iSA1'

iSA2'

iSA2'’

iSA3’

State

SA1 , SA2 , SA3

SA1' , SA2' , SA2'’ , SA3'

0, 1, 1

0, 1, 0, 1

0

iU

(iU + iD)

0

iU

0

iD

1, 0, 1

1, 0, 0, 1

-iU

0

iD

-iU

0

0

iD

1, 1, 0

1, 0, 1, 0

-(iU + iD)

-iD

0

-iU

0

-iD

0

Nine-Switch

Currents

Twelve-Switch

Currents

Figure 2.10: Instantaneous switch currents of the nine-switch converter and the twelve-switch converter for different switching states.

74


The following observations are noted from Fig. 2.10.

1. At the end of T1, SA1 and SA1′ switch ON the same current −iU . The same applies

to SA2 and SA2′ , which switch OFF the same current iU . The other switches do

not commutate at this instant.

2. At the beginning of T3, SA3 and SA3′ switch OFF the same iD, while SA2 and

SA2′′ switch ON the same −iD. The other switches do not commutate at this

instant.

Therefore the switching losses of the nine-switch and BTB converters are equal with the

same DC-link voltage. Conduction losses of the two converters are however different,

caused by the different switch currents during T1 and T3. The middle switches of the

nine-switch converter carries same overall currents as their counterparts in the BTB

converter. It is only the conduction losses of the top and the bottom switches that

makes the difference.

Based on the above fact, the existence of LLAs of different modes of the nine-switch

converter can be summarized from [95] as follows.

1. AC-AC Common Frequency (AC-AC CF) Mode: In this mode, the nine-

switch converter will have comparatively less conduction loss than the BTB con-

verter when the instantaneous terminal currents are of opposite polarities and have

a phase difference smaller than 90. That means an AC source connected to any

one of the upper and the lower terminals, and an AC load connected to the other

terminal from the same phase-leg, like in an online UPS [86] and AC-AC power

conditioner [83]. Fig. 2.11 shows the LLA plots of the nine-switch converter in this

mode of operation. Here, M = (1−MoD)/(1−MoU ), with MoU and MoD as the

DC offsets applied to RefU and RefD respectively. ID and IU are the amplitudes

of the lower terminal and upper terminal AC currents iD and iU respectively. The

phase difference shown in the y-axis is the phase difference between iD and iU .

The shaded sides of the curves are indicating the regions, where the nine-switch

converter has lower losses than the BTB converter.

2. AC-AC Different Frequency (AC-AC DF) Mode: It has been shown in [95]

that the AC-AC DF mode of operation of the nine-switch can not have an LLA.

The reason is that in this mode, the cancellation of switch current in one half-cycle

is offset by the addition of the switch current in the other half-cycle.

3. AC-DC Different Frequency (AC-DC DF) Mode: According to [95], this

mode of the nine-switch converter will give comparatively lower conduction loss

75

2.3. LLA of Nine-Switch Converter for Different Modes of Operation

Figure 2.11: LLAs of nine-switch converter for AC-AC CF mode with a load-sourcecombination as per [95]. (a) based on AVERAGE switch current, (b) based on RMSswitch current.

76


Figure 2.12: LLAs of nine-switch converter for AC-DC DF mode with a source-sourcecombination as per [95].(a) based on AVERAGE switch current, (b) based on RMSswitch current.

than the BTB converter for a source-source combination, like in the case of tying

multiple green sources to a DC micro-grid [84, 87]. The upper AC terminals can

be tied to a wind or diesel generator, while the lower DC terminals can be tied

to a combination of low-voltage fuel cells and photo-voltaic sources. The sources

generate power in harmony for eventual feeding to the DC micro-grid connected

to the DC-link of the converter. Fig. 2.12 shows the LLA plots of the nine-switch

converter in this mode of operation.

As discussed in the introduction of this chapter, there is an incomplete conclusion

drawn in [95] for the AC-DC DF mode of operation. It concluded that in AC-DC DF

mode, the upper and lower terminals of the nine-switch converter have to be connected

to an AC source and a DC source respectively, in order for the converter to have an LLA.

77

2.4. LLA of Nine-Switch Converter for Load-Source Combination in AC-DC DF Mode

It has not considered the other possibility of AC-DC DF mode with the upper terminal

connected to a DC source/load, and the lower terminal to an AC source/load. The

next section investigates the loss comparison in these possible combinations of source

and load, and shows that the nine-switch converter can have relatively lower losses as

compared to its BTB precedence, if the upper terminal is feeding a DC load and the

lower terminal is drawing power from an AC source.

2.4 LLA of Nine-Switch Converter for Load-Source

Combination in AC-DC DF Mode

Extending the same concept as in [95], the LLAs for the load-source combination as

shown in Fig. 2.13 are derived in this section. As can be seen in Fig. 2.13(b), the

converter is using a three-phase AC source (lower terminal) and a DC source (DC link)

to power a DC load (upper terminal). For the ease of keeping track throughout this

section, the configuration can be summarized as follows.

Upper terminal : DC load

Lower terminal : AC source

DC link : DC source

2.4.1 Qualitative Reasoning for Existence of LLAs

Following the same way as in [95], the reason of existence of the LLAs for this config-

uration of AC-DC DF mode (upper terminal connected to a DC load, and the lower

terminal to an AC source) of nine-switch converter can be analyzed from the currents

through the switches SA1 of the nine-switch converter and SA1′ of the BTB converter.

As shown in Fig. 2.14(a), when RefD is near its negative peak, the current (iD + iU )

through SA1 is higher than the current iU through SA1′ for the duration T3. This is

because both iD and iU are negative during T3 and they add up through SA1. On the

other hand, in Fig. 2.14(b) when RefD is near its positive peak, the current (iD + iU )

through SA1 is lower than the current iU through SA1′ for the duration T3 . Here, iU

is negative and iD is positive. Hence, a cancellation of instantaneous current is seen in

SA1. It is evident that T3 in Fig. 2.14(b) is longer than T3 in Fig. 2.14(a), which essen-

tially means that the net effect of cancellation is more than the net effect of addition of

78


iU = -IU

BTB

Or

Nine-switch

converter iD = IDcos(ω0t+φ)

Vdc

vs

Io

Pdc,in

Pdc,out = Pload

Pac,in

DC loads

(a) Generic representation.

SA1

iSA1

SA2

SA3

iSA2

iSA3

iU = -IU = -Io/3

iD

vs = 120V,60Hz

(3-ph AC Grid)

RL

Io

Vd

c =

40

0V

Vo =

38

0V

(DC

Data

-ce

nte

r)

-

+

-

+ DC

DC

Bi-dir.

(b) Detailed connection for a nine-switch converter.

iU = -IU = -Io/3

vs = 120V,60Hz

(3-ph AC Grid)

RL

Io

Vo =

38

0V

(DC

Data

-ce

nte

r)

-

+

SA1'

SA2’

iSA1'

iSA2'

SA2'’

SA3’

iSA2'’

iSA3'

iD

Vd

c =

40

0V

-

+ DC

DC

Bi-dir.

(c) Detailed connection for a BTB converter.

Figure 2.13: The special load-source combination of the nine-switch converter and theBTB converter under study.

79


the instantaneous currents through SA1. Mathematically, this can be represented as

AA1,+ve + AA1,−ve < 2×AA1′ , (2.2)

where, AA1,+ve, AA1,−ve and AA1′ are the shaded areas as marked in Fig. 2.14.

Note that area AA1′ of the BTB converter remains same during positive and negative

half-cycle of phase-a voltage va. This is because the back-end DC-DC part of the BTB

converter is completely decoupled from the front-end rectifier part by the intermediate

DC-link.

However, this net reduction of current is not seen in SA3, because the interval T1 as

fixed by RefU does not vary over a line-cycle.

Again, the same reasoning is valid for the case when the upper terminal is connected

to a DC source, and the lower terminal to an AC source. Since iU is positive in this

case, iD and iU cancels each other during the negative half-cycle of RefD, and they add

up during the positive half-cycle. Therefore, the net effect of addition becomes more

than that of the cancellation, and as a result, the nine-switch converter experiences more

overall conduction loss as compared to the BTB converter.

It should be noted that the shaded areas in Fig. 2.14 are marked only to show the

addition and the cancellation of currents in different instants of the switching period.

They can be used as an indication of loss comparison only when the average switch

current is concerned (as in the case of IGBT). For the case of MOSFET, as in this work,

the actual indication of loss comparison is the product of RMS current and time, which

is not so easy to comprehend from Fig. 2.14. However, it is apparent that the addition

and the cancellation of currents will affect the loss comparison accordingly.

2.4.2 Mathematical Derivation of LLAs

The reader is referred to [95, 98] for a detailed background of the mathematical proofs

presented here. In this case, the operating parameters of the converters can be assumed

as follows.

RefU = MoU

RefD = MD cosω0t−MoD

iU = −IU

iD = ID cos(ω0t+ ϕ)

(2.3)

Here, MoU and MoD are the DC offsets applied to the upper and lower terminal

80


vSA1

iSA1

iSA1'

RefU RefD

iD + iU

iU

T3T

AA1,-ve

AA1'

(a) During negative half-cycle of RefD.

vSA1

iSA1

iSA1'

RefU RefD

iD + iU

iU

T3 T

AA1,+ve

AA1'

(b) During positive half-cycle of RefD.

Figure 2.14: Currents through SA1 of the nine-switch converter and SA1′ of the BTBconverter.

81


modulation references RefU and RefD respectively, and MD is the lower terminal mod-

ulation index. ID, ω0 and ϕ represent the amplitude, angular frequency and phase of

the lower terminal AC source current iD, whereas IU is the amount of DC load current

drawn from the upper terminals. Also, applying simple geometry in Fig. 2.10, the

following can be obtained.

T1 = T (1−RefU )/2

T2 = T (RefU −RefD)/2

T3 = T (1 +RefD)/2

Consequently, from Fig. 2.10, the difference of the square of the RMS switch current

of the two converters [95] is obtained as

∆i2RMS = ω0

2π

∫ [(iU + iD)2 − i2U ]T3

T

+[(iU + iD)2 − i2D]T1

T

dt

which simplifies to

∆i2RMS = 14(1−MoD)I2

D + 12(1−MoU )I2

U −12MDIDIU cosϕ. (2.4)

Similarly, the average switch current difference of the two converters is obtained as

∆|i|Av = ω0

2π

∫ (|iU + iD| − |iU |)

T3

T

+(|iU + iD| − |iD|)T1

T

dt

which simplifies to

∆|i|Av = − 1π

(1−MoU )ID + 12(1−MoU )IU

− 14MDID cosϕ , for ID ≤ IU

= 12πMDID cosϕ

IUID

√1−

(IUID

)2− sin−1

(IUID

)+ 1π

(2−MoU −MoD)ID

√1−(IUID

)2− IUID

sin−1(IUID

)− 1π

(1−MoU )ID −12(1−MoD)IU , for ID > IU

. (2.5)

For most efficient utilization of the DC link in a nine-switch converter, the sum of

82


the two modulation references should be no less than 1.0. Therefore, the following is to

be chosen.

MoD = 12(1−MoU )

MD = 1−MoD

(2.6)

Based on the definition of

M = 1−MoD

1−MoU(2.7)

as in [95], the parameters can also be defined as

MoU = 2M − 12M + 1

MoD = 12M + 1

MD = 2M2M + 1

(2.8)

Hence, for the difference of the square of the RMS switch current of the two converters

to be negative, i.e., for ∆i2RMS < 0, the following inequality must hold good.

cosϕ > M(ID/IU )2 + 22M(ID/IU ) (2.9)

The LLA plots obtained from (2.9) is shown in Fig. 2.15. A similar inequality (2.10)

can be obtained from (2.5) for ∆|i|Av < 0, which will lead to another LLA plot as shown

in Fig. 2.16.

cosϕ > 2(IU/ID)(1−MoU )MD

− 4(1−MoU )πMD

, for ID ≤ IU

> p1 + p2− p3 , for ID > IU

(2.10)

where

p1 = 2(1−MoU )MD

[(IU/ID)

√1− (IU/ID)2 − sin−1(IU/ID)

]p2 = π(1−MoD)(IU/ID)

MD

[(IU/ID)


]

p3 =2(2−MoU −MoD)

[√1− (IU/ID)2 + (IU/ID) sin−1(IU/ID)

]MD

[(IU/ID)


]Similar to [95], these LLAs indicate the maximum phase difference between the

upper terminal current and voltage, below which, the nine-switch converter will have

lower conduction losses than the BTB converter. It has been found that a maximum

83


Figure 2.15: LLAs of nine-switch converter for AC-DC DF mode based on RMS switchcurrent, when the upper terminal is connected to a DC load and the lower terminal isconnected to an AC source.

Figure 2.16: LLAs of nine-switch converter for AC-DC DF mode based on AVERAGEswitch current, when the upper terminal is connected to a DC load and the lower terminalis connected to an AC source.

ϕmax exists only when M > 2 if the conduction losses are related to the RMS switch

current (as is the case for MOSFETs), and M > 0.8 if the conduction losses are related

to the average switch current (as is the case for IGBTs).

It should be noted that although the above analysis takes the phase ϕ of the AC

current in the lower terminal in to account, it has little influence on the conduction

losses of the switches in the AC-DC DF mode [95]. In fact, considering iD = ID cosω0t

and neglecting its phase, the inequality (2.9) becomes

2M(ID/IU ) > M(ID/IU )2 + 2,

84


Figure 2.17: LLA conditions M > 2 and (ID/IU ) < 2 of nine-switch converter for AC-DC DF mode based on RMS switch current, when the upper terminal is connected to aDC load and the lower terminal is connected to an AC source.

which holds good for M > 2 and (ID/IU ) < 2 as depicted in Fig. 2.17.

The same analysis above can be repeated with the upper DC terminal current as-

sumed as flowing in to the converter, i.e., a DC source connected to the upper terminal.

In this case the configuration can be summarized as follows

Upper terminal : DC source

Lower terminal : AC source

DC link : DC load

Substituting iU = IU in (2.3) and performing similar subsequent analysis, the fol-

lowing inequality is obtained for ∆i2RMS < 0.

cosϕ < −M(ID/IU )2 − 22M(ID/IU ) (2.11)

It is clear that (2.11) does not give any LLA. Same is true for ∆|i|Av < 0 in this

operating condition. Therefore, it can be concluded that this criterion of application

(upper terminal connected to DC source and lower terminal connected to AC source) of

the nine-switch converter is not as efficient as the BTB converter.

85

2.5. Simulation Results and Discussions

2.4.3 Efficient Load Sharing

It can be proven from (2.9) that the LLA plots based on RMS switch current as shown

in Fig. 2.15 will be always on the left side of ID/IU = 2 for any M > 2. Therefore,

the third condition for existence of LLA (the other two conditions being M > 2 and

choice of ϕ as per (2.9) based on RMS switch current is: ID/IU < 2, which leads to the

following.

( 32Va)ID

( 32Va)IU

< 2

⇒( 3

2VaID)( 3

2 ×MDVdc

2 )IU< 2

(2.12)

where, Va is the peak of the phase-a voltage va, and Vdc is the DC-link voltage.

Substituting Pac,in = 32VaID and Pload = 3MDVdcIU in the above leads to

Pac,inPload

<12 . (2.13)

This signifies that, not more than half of the load power should be drawn from the

lower terminal AC side in order to get lower conduction loss in the nine-switch converter

as compared to the BTB converter. The other half of the load power must be supplied

by the DC source (Pdc,in) connected to the DC-link. Note that this is for the case when

MOSFETs are used to realize the converters, i.e. the losses are related to RMS switch

current.

Similarly, it can be proven that the LLA plots based on average switch current as

shown in Fig. 2.16 will be always on the left side of ID/IU = 1.4 for any M > 0.8. This

leads to the following load-sharing condition

Pac,inPload

< 0.35.

Therefore, if the converters are realized with IGBTs (where the losses are related to

average switch current), maximum 35% of the load power can be drawn from the lower

terminal AC side in order to get lower conduction loss in the nine-switch converter as

compared to the BTB converter.

2.5 Simulation Results and Discussions

To validate the analysis, the two systems both rated for 1 kW were simulated in PLECS.

The key parameters chosen for the simulations are listed in Table 2.4. The switching

86


Table 2.4: Design Parameters for Comparison of Nine-switch Converter and BTB Con-verter

Parameter name (symbol) Parameter valueLower terminal 3-ph AC source (vs) 120 V, 60 Hz (RMS ph. voltage)Upper terminal DC load (RL) 144.4 Ω (per phase)DC-link source (Vdc) 400 VLower modulation ratio (MD) 0.95Lower modulation offset (MoD) 0.05Upper modulation offset (MoU ) 0.9Lower terminal power factor 1.0 (ϕ = 0)Switching frequency (fs) 100 kHzDevice resistance (RDS,on) 0.28 Ω (C3M0280090D)

losses of both the systems are set to zero, since they are equal for both the systems [95]

and therefore do not make any difference in the analysis. The ON-resistance (RDS,on)

is considered as per the data-sheet of the SiC MOSFET C3M0280090D, which is used

for development of the laboratory prototypes.

The simulation was carried out with the extensive use of the “periodic average” block

in PLECS [102], suited to determine the average conduction losses of power semicon-

ductors. The averaging time was specified as the switching period T = 1/fs. The value

of M was chosen as 10. Therefore, MD , MoD and MoU were calculated as per (2.8) for

efficient utilization of DC bus. It may also be noted that there is no particular reason

as such for simulating with ϕ = 0, other than having a unity power factor for the AC

source. In fact, as shown in Fig. 2.15, for M = 10, ϕ can be anywhere between 0 to

65 in order for the nine-switch converter to have an LLA. The application considered in

this work is a 380V data-center load fed from a three-phase AC grid (120 V rms-phase-

voltage) and a DC source (400 V DC) [15]. Since this system does not require any

reactive power support, the AC grid power factor should ideally be unity, and therefore

ϕ should be 0.

Fig. 2.18 shows the comparative periodic average of total conduction losses for

different ID/IU values. It can be seen that for ID/IU = 2.5/0.88, the conduction

loss in the nine-switch converter is greater than that in the BTB converter; whereas,

for ID/IU = 1.5/0.88 and 0.5/0.88, the nine-switch converter has comparatively lesser

conduction loss. This is clearly in compliance with the LLA plot corresponding to

M = 10 as shown in Fig. 2.15.

Fig. 2.19 shows the comparative periodic average of conduction losses in the first

leg of the two converters. It can be seen that the losses in the middle and the bottom

switches of the two converters are almost same; whereas, the losses in the top switches

SA1 and SA1′ differ significantly. Loss in SA1 is higher than that in SA1′ during the

87

2.5. Simulation Results and Discussions

Periodic

avera

ge o

f co

nve

rter

conduct

ion lo

ss (W

)

Time (s)

BTBNine-switch

ID=2.5A, IU=0.88A

ID=1.5A, IU=0.88A

ID=0.5A, IU=0.88A

Figure 2.18: Comparative periodic average of total conduction losses in the nine-switchconverter and the twelve-switch converter.

negative half cycle of phase-a voltage vA, because of addition of iD and iU . On the

other hand, loss in SA1 is lower than that in SA1′ during the positive half cycle of vA,

because of cancellation between iD and iU . It is clear from Fig. 2.19 that the effect

of cancellation is more than that of addition, which results in overall lower loss in the

nine-switch converter. This is in complete agreement with the analysis made in the

previous section.

It should be noted that the 60 Hz ripple present in the average conduction loss of

one leg in Fig. 2.19 is due to the choice of the averaging time (in the “periodic average”

block in PLECS) as the switching period T = 1/fs, as mentioned earlier. The 60 Hz

ripple per leg, in turn, causes a ripple of 180 Hz in the loss plot of Fig. 2.18 because of

the 120 phase shift between the three phases of the AC source. These loss ripples will

not be present if the averaging time is increased to, say, one line-cycle of the AC voltage

(16.67 ms).

The thermal simulation set-up is shown in Fig. 2.20. The thermal capacitance and

thermal resistance of the heat-sinks are chosen as 45 J/K and 0.002 K/W. The initial

temperatures of all the components are set to 25C. Fig. 2.21 shows the comparison of

steady-state heat flow in the heat-sinks of the two converters. It is further corroborated

from this figure that the nine-switch converter has comparatively lower loss than the

BTB converter for this particular combination of load and source connection.

88


SA3 SA3'

SA2 SA2' + SA2''

SA1 SA1'

va

additioncancellationWW

WV

Time (s)

Figure 2.19: Comparative periodic average of conduction losses in the first leg of thenine-switch converter and the twelve-switch converter for ID = 0.5A and IU = 0.88A.

Figure 2.20: Thermal simulation set-up of the nine-switch converter and the twelve-switch converter.

89

2.6. Theoretical Conduction Loss Comparison

Heat

flow

in the

sin

k (W

)

Time (s)

BTB

Nine-switch

Figure 2.21: Comparison of steady-state heat flow for the nine-switch converter and thetwelve-switch converter for IU = IU = 0.88A.

2.6 Theoretical Conduction Loss Comparison

The RMS current expressions of the switches of the two converters used for the calcu-

lation of conduction losses are listed here.

For nine-switch converter

i2SA1RMS = 12(1 +MoU )I2

U + 14(1−MoD)I2

D −12MDIDIU cosϕ

i2SA2RMS = 12(1−MoU )I2

U + 14(1−MoD)I2

D

i2SA3RMS = 12(1−MoU )I2

U + 14(1 +MoD)I2

D

For BTB converter

i2SA1′RMS

= 12(1 +MoU )I2

U

i2SA2′RMS

= 12(1−MoU )I2

U

i2SA2′′RMS

= 14(1−MoD)I2

D

i2SA3′RMS

= 14(1 +MoD)I2

D

90


Table 2.5: Calculated Conduction Losses for the Two Converters

Switch RMS current (A) Conduction loss (W)SA1 0.7437 0.15486511SA2 0.4704 0.06195732SA3 0.4896 0.06711828Total conduction loss per leg for 9-switch converter 0.283940723SA1’ 0.8588 0.20651048SA2’ 0.192 0.01032192SA2” 0.4294 0.05162762SA3’ 0.4504 0.05680084Total loss per leg for BTB converter 0.325260869Difference of per-leg conduction loss 0.041320146

Here, MoU and MoD are the DC offsets applied to the upper and lower terminal

modulation references respectively, and MD is the lower terminal modulation index.

ID and ϕ represent the amplitude and phase of the lower terminal AC source current,

whereas IU is the amount of DC load current drawn from the corresponding upper

terminal. For calculation of conduction losses at 1 kW rated power, the following values

has been used.

MoU = 0.9, MoD = 0.05, MD = 0.95, ID = IU = 0.88A, ϕ = 0 and RDS,on = 0.028Ω

(C3M0280090D).

The theoretical conduction losses of the two converters for 1 kW power are shown in

Table 2.5.

2.7 Experimental Results and Discussions

Experimental set-ups for both the systems were also built and tested in the laboratory

with the same parameters as mentioned in Table 2.4. The laboratory prototype of the

nine-switch converter as a part of the experimental set-up is shown in Fig. 2.22. Two

such prototypes were used to realize the BTB topology with the middle-switches of all

legs removed and their footprints shorted. This section validates the claims presented

in the analysis and the simulations. The two cases ID/IU < 2 and ID/IU > 2 are

considered separately to study the loss comparison of the two converters.

2.7.1 For ID/IU < 2

In this case, the upper and lower terminal currents are maintained as ID = 1A and

IU = 0.88A respectively. Therefore, the three-phase AC source connected to the lower

terminal supplies 254 W and the DC source connected to the DC-link supplies the rest

746 W to the 1000 W load. Figs. 2.23 and 2.24 show the key experimental waveforms

91

2.7. Experimental Results and Discussions

Gate drivers(CRD-001)

One leg comprising of three switches

Heat sinksDC-link

capacitors

Gate pulses

Figure 2.22: Experimental prototype of the nine-switch converter. Two such prototypeswere used to realize the BTB topology with the middle-switches of all legs removed andtheir footprints shorted.

of the test set-up. It is observed that the three-phase AC source (lower terminal) is

operating at close-to-unity power factor (0.99) and the output DC voltage and currents

(upper terminal) are stable at 380 V and 2.64 A respectively.

The experimental waveforms of currents through the top switch SA1 of the nine-

switch converter for the positive and the negative half-cycle of phase-a voltage va are

shown in Figs. 2.25 and 2.26 respectively. The corresponding switch current through

the top switch SA1′ of the BTB converter is shown in Fig. 2.27. It is apparent that the

sum of the shaded areas in Figs. 2.25 and 2.26 is less than twice the shaded area in Fig.

2.27. The implication here is that the nine-switch converter has lower conduction loss

than the BTB converter.

2.7.2 For ID/IU > 2

In this case, the upper and lower terminal currents are maintained as ID = 2.5A and

IU = 0.88A respectively. Therefore, the three-phase AC source connected to the lower

terminal supplies 636 W and the DC source connected to the DC-link supplies the rest

364 W to the 1000 W load. Figs. 2.28 and 2.29 show the key experimental waveforms

of the test set-up in this case. It is observed that the three-phase AC source (lower

terminal) is again operating at close-to-unity power factor (0.99) and the output DC

voltage and currents (upper terminal) are stable at 380 V and 2.64 A respectively.

Similar to the previous case, the experimental waveforms of currents through the top

switch SA1 of the nine-switch converter for the positive and the negative half-cycle of

92


Io (1A/div)

Vo (100V/div)

va (100V/div)

ia (2A/div)10ms/div

Figure 2.23: Key input and output waveforms of the nine-switch converter at the ratedpower of Pload = 1kW with ID = 1A and IU = 0.88A. Note that Pac = 254W <0.5× Pload.

Io (0.5A/div)

ia,b,c (0.5A/div)

5ms/div

Figure 2.24: Three-phase balanced ac currents at lower terminal with ID = 1A, and theload current at upper terminal with IU = 0.88A.

iSA1 (0.5A/div)cancellation

va (100V/div)

vg,A1 (20V/div)

vg,A3 (20V/div)

T

T3

2μs/div

Figure 2.25: Current through the top switch SA1 of the nine-switch converter duringPOSITIVE half-cycle of phase-a voltage va with ID = 1A and IU = 0.88A.

93


iSA1 (0.5A/div)

addition

va (100V/div)

vg,A1 (20V/div)

vg,A3 (20V/div)

T

T3

2μs/div

Figure 2.26: Current through the top switch SA1 of the nine-switch converter duringNEGATIVE half-cycle of phase-a voltage va with ID = 1A and IU = 0.88A.

iSA1' (0.5A/div)

va (100V/div)

vg,A1' (20V/div)

vg,A3' (20V/div)

2μs/div

TT2+T3

Figure 2.27: Current through the top switch SA1′ of the BTB converter during POS-ITIVE half-cycle of phase-a voltage va with ID = 1A and IU = 0.88A. It remainssame during NEGATIVE half-cycle of va. Also, it does not change for the other case ofID = 2.5A, as long as IU is maintained at 0.88A. Note that vg,A3′ does not have anyparticular significance in this figure; it is shown to maintain similarity with Figs.2.25and 2.26.

Io (1A/div)

Vo (100V/div)

va (100V/div)

ia (2A/div) 10ms/div

Figure 2.28: Key input and output waveforms of the nine-switch converter at the ratedpower of Pload = 1kW with ID = 2.5A and IU = 0.88A. Note that Pac = 636W >0.5× Pload.

94


Io (0.5A/div)

ia,b,c (1A/div)

5ms/div

Figure 2.29: Three-phase balanced ac currents at lower terminal with ID = 2.5A, andthe load current at upper terminal with ID = 2.5A and IU = 0.88A.

iSA1 (1A/div)

cancellation

va (100V/div)

vg,A1 (20V/div)

vg,A3 (20V/div)

T

T3

2μs/div

Figure 2.30: Current through the top switch SA1 of the nine-switch converter duringPOSITIVE half-cycle of phase-a voltage va with ID = 2.5A and IU = 0.88A.

phase-a voltageva are shown in Figs. 2.30 and 2.31 respectively. For comparison with

the corresponding switch current through the top switch SA1′ of the BTB converter,

Fig. 2.27 is referred to again, since iSA1′ does not change in case of BTB converter as

long as IU is unchanged. It is clear from Fig. 2.30 that even though iD and iU are of

opposite polarity during T3, the resultant current (iD + iU ) through SA1 is considerably

large due to the large difference of magnitude between ID and IU . Therefore the sum

of the shaded areas in Figs. 2.30 and 2.31 can not be less than twice the shaded area

in Fig. 2.27. The implication here is that the nine-switch converter does not have lower

conduction loss than the BTB converter.

Once again, the shaded areas in Figs. 2.25, 2.26, 2.27, 2.30 and 2.31 do not indicate

the loss comparison; the actual indicator should be the product of RMS current and

time since MOSFETs are used to realize the converters. However, the shaded areas do

indicate the addition and the cancellation of currents that have direct implications in

loss comparison.

95

2.8. Benchmark of Application Criteria of Nine-Switch Converter with LowerConduction Loss

iSA1 (1A/div)

addition

va (100V/div)

vg,A1 (20V/div)

vg,A3 (20V/div)

T

T3

2μs/div

Figure 2.31: Current through the top switch SA1 of the nine-switch converter duringNEGATIVE half-cycle of phase-a voltage va with ID = 2.5A and IU = 0.88A.

Finally, to emphasize the low loss feature the full-load experimental efficiency plots

of the two systems are presented in Fig. 2.32 for variation of Pac,in/Pload. Note that

the horizontal axis of Fig. 2.32 does not indicate load power variation; it indicates the

fraction of load power being supplied by the lower terminal AC source. It is evident

that the nine-switch converter has higher efficiency than the BTB converter in the

region where Pac,in/Pload < 0.5. This is in clear agreement with (2.13) and the analysis

presented in Section 2.4.3. The other striking feature to note is that efficiency gain for

nine-switch converter is highest (about 0.4%) when Pac,in = 224W , because, at this

point, ID = IU and the cancellation between iD and iU is most effective. Also, the two

efficiency plots converged at Pac,in = 450W , which is as expected since for M = 10

and ϕ = 0, the value of ID/IU can be read from Fig. 2.15 as approximately 1.8, which

translates to Pac,in/Pload = 0.45 as the convergence point.

It should be remembered here that even though the efficiency gain is not very high,

the nine-switch converter has an inherent advantage of 25% saving in the active device-

count. The point of interest here is that one need not compromise in terms of efficiency

for gaining in terms of device-count.

2.8 Benchmark of Application Criteria of Nine-Switch

Converter with Lower Conduction Loss

As explained in [95], for AC-AC CF mode of the nine-switch converter, the upper and

lower terminal currents have to be of opposite polarities (with a phase difference smaller

than 900) to get an LLA. This means that, of the two AC equipment connected to the

two terminals, one must be source, while the other must be load. However, for the

AC-DC DF mode, it does not really matter whether the AC equipment connected (to

96


93.8

94

94.2

94.4

94.6

94.8

95

95.2

95.4

95.6

95.8

0 0.2 0.4 0.6 0.8 1 1.2

Fu

ll-lo

ad

effic

ien

cy (

%)

Pac,in / Pload

9-sw

BTB

Figure 2.32: Full-load experimental efficiency plots of the nine-switch converter and thetwelve-switch converter for variation of Pac,in/Pload with Pload = 1000W . Note that thehorizontal axis does not indicate load power variation; it indicates the fraction of loadpower being supplied by the lower terminal AC source.

Table 2.6: Updated List of Application Criteria of Nine-Switch Converter for Existenceof LLA

Mode of Operation Upper terminal connected to Lower terminal connected to

AC-AC Common Frequency (CF) Source LoadLoad Source

AC-DC Different Frequency (DF) AC Source/Load DC SourceDC Load AC Source/Load

either of the upper or the lower terminal) is a source or a load. This is because for both

AC load and AC source, the current changes its polarity in every half cycle, which does

not affect the analysis presented here in any way.

Therefore, keeping the above in mind, Table 2.1 should be updated as Table 2.6,

which shows the complete list of application criteria of the nine-switch converter where

it has lower conduction loss as compared to the twelve-switch BTB converter.

2.9 Summary

This chapter has added a special application criterion to the benchmark of the set of

application criteria for which the nine-switch converter has comparatively lower losses

than its BTB counterpart. LLAs of the nine-switch converter are derived and plotted,

which show that a load-source combination is possible with better thermal performance

than the BTB converter in the AC-DC DF mode. The analytical claims are verified with

the simulation and experimental results from a non-isolated power converter prototype

97

2.9. Summary

for data center loads.

It should be noted here that the nine-switch-based topology proposed in this chapter

is applicable for the AC-DC conversion stage of a DC data center only if isolation is

not crucial at this stage. Isolation is anyway provided in the isolated DC-DC converter

to step-down the 380 V DC to 48 V DC or 12 V DC for rack-level power distribution.

However, modern day data center power architecture requires isolation at the AC-DC

stage as well. Therefore, the isolated variant of the nine-switch AC-DC converter is

discussed in the forthcoming chapters.

98

Chapter 3

An APWM HB Series

Resonant Converter with

Magnetizing Current Assisted

ZVS

In Chapter 1 it has been shown that the lower converter of the proposed nine-switch

single-stage isolated three-phase AC-DC conversion system is a parallel combination

of three asymmetrical pulse-width-modulated half-bridge (APWM HB) series resonant

converters. This chapter presents a novel and detailed design procedure for the standard

APWM HB series resonant converter which is applicable for both the lower converters

of the nine-switch converter and the DC-DC converters serving the loads inside the ICT

equipment of a data center. This chapter is presented before Chapter 4 so that the

design equations developed here can be straight-away referred to when designing the

lower converters of the proposed nine-switch converter in Chapter 4.

3.1 Introduction

The low-voltage low-power point-of-use power supplies (PUPS) in data center racks re-

quire converters that not only have high power density and high efficiency, but also op-

erate in constant switching frequency to avoid the synchronization issues present in such

systems [53]. Such converters are also commonly called Point-of-Load (PoL) convert-

ers. The asymmetrical pulse-width-modulated half-bridge (APWM HB) series resonant

99

3.1. Introduction

converter is thus an ideal candidate for these systems because it has the advantage of

constant-frequency operation over the conventional variable-frequency half-bridge res-

onant converters [103, 104]. The APWM HB series resonant converter also features

limited voltage stress on the switches, soft-switching over wide load-range and the use

of a simple capacitive output filter [53, 58, 59, 105–107]. Its main drawback is the loss

of zero-voltage switching (ZVS) at higher input voltage. To eliminate this problem, an

auxiliary circuit was suggested in [59] and [105] so that the ZVS range is extended for a

large input voltage range. However, the auxiliary circuit not only decreased the power

density, but also caused certain efficiency penalty due to the extra auxiliary current [53].

An alternative solution was presented in [53] by the use of a CLL resonant circuit to

maintain ZVS over all line and load conditions without excessive circulating current.

However, the use of an additional inductor, in parallel to the transformer primary wind-

ing, again makes the converter bulkier than the standard APWM HB series resonant

converter. In [108], a new topology has been proposed that ensures load-independent

soft-switching and reduced circulating current; but it has an additional switch in series

with one of the output diodes.

Some researchers [109–111] have reported the discontinuous conduction mode (DCM)

operation of the series resonant converter at fixed frequency, which may be incorporated

for the APWM HB series resonant converter to achieve low switching losses for wide

range of load and line variations. The DCM operation from [109, 111] and the oper-

ation at resonant frequency as described in [109, 110], can easily achieve zero current

switching (ZCS) as the switches do not have to commute any current. However, these

converters still have significant output capacitance (of the MOSFETs) loss which limits

the operating frequency [53]. Moreover, the ZCS with resonant frequency operation as

in [109,110] is achievable only for symmetrically driven resonant tanks [53], and not for

asymmetrically driven tanks as in APWM HB series resonant converters.

Another possible solution can be to use the magnetizing current, like in conventional

LLC resonant converters, to achieve ZVS. The choice of magnetizing inductance is a

crucial issue for any resonant converter that uses the magnetizing current for achieving

soft switching. This is because the magnetizing current directly adds up with the reso-

nant tank current and increases the power losses in the tank elements and the switches

without participating in the power transfer to the load. This affects the overall efficiency

of the converter. Due importance is given in literature [34,49,54–57,62,112,113] for the

optimal design of magnetizing inductance for LLC resonant converters. However, this

issue is somewhat less addressed in APWM HB series resonant converter, primarily be-

100

3. An APWM HB Series Resonant Converter with Magnetizing Current Assisted ZVS

cause, so far, it has been studied as a series resonant converter with the magnetizing

inductance of the transformer assumed to be infinitely large [53,58,59,105–107].

The design of magnetizing inductance for APWM HB series resonant converter how-

ever, is different from the one in conventional LLC resonant converter [34,57]. In an LLC

converter, the tank current always leads the pole voltage (refer to Fig. 3.1) by a small

angle. By addition of an optimum amount of lagging magnetizing current, the resultant

tank current is made lagging w.r.t. the pole voltage to achieve ZVS. However, because of

the asymmetric duty, the tank current in an APWM HB series resonant converter leads

the pole voltage in one switching transition and lags it on the other, making it difficult

to choose an optimal value of required magnetizing current. It is imperative to mention

here that all resonant converters need a lagging current during switching transitions for

ensuring ZVS.

As a solution, in the APWM HB converter, the switching frequency can be chosen

much higher than the resonant frequency to obtain an always-lagging current and thus

minimize the requirement of magnetizing current for ZVS. However, this phase lag re-

sults in additional circulating current, and especially if the maximum allowable duty

ratio is less than 0.5 for maximum rated load, the required phase lag becomes more to

ensure ZVS with minimum magnetizing current. On the other hand, if the converter

is operated at the resonant frequency, the magnetizing current requirement increases

for ZVS because of the asymmetric duty ratio. So, there is a clear trade-off between

minimization of magnetizing current and minimization of required phase lag for this

design.

This chapter presents a novel design procedure of the standard APWM HB resonant

topology, without any auxiliary circuit, which operates at the resonant frequency and

still requires reduced magnetizing current for achieving ZVS for wide range of line and

load variations. Thus, the total circulating current is reduced resulting in better overall

converter efficiency. A reference topology with an auxiliary LC network as presented

in [59] is chosen to compare the performance of the proposed design. It is found that the

proposed topology has better efficiency than the reference topology for the load range

of 30%-100%.

101

3.2. Steady State Operation

Figure 3.1: Schematic of the standard Asymmetrical Pulse Width Modulated (APWM)half-bridge resonant converter. Note that vs is the pole voltage incident on the seriesresonant tank.

Figure 3.2: Schematic of the reference converter: modified series-resonant APWM con-verter [59].

3.2 Steady State Operation

3.2.1 Topology and Equivalent Circuit Model

Fig. 3.1 shows the standard topology of an APWM half-bridge resonant converter. The

reference converter, which is a modified series-resonant APWM converter presented

in [59] is shown in Fig. 3.2. The reference converter has an extra auxiliary network

consisting of capacitors Ca1, Ca2 and inductor La. This auxiliary network is totally

absent in the proposed converter as shown in Fig. 3.3, which uses the magnetizing

current of the transformer for achieving ZVS of the switches.

As shown in Fig. 3.3, the half-bridge chopper circuit consisting of switches S1 and

S2 produces a uni-polar ac voltage vs when switched with an asymmetric duty ratio

D. This voltage is incident on a series resonant tank (Cr, Lr) which transfers input

Cr Lr

Vi

iLr

Co RL

+

Vo

-

D1

D2

S1

S2

[N:1:1]

+

vs

-Coss2

Coss1

. ..Lm

iLm

Figure 3.3: Schematic of the proposed APWM HB series resonant converter with mag-netizing current assisted ZVS. Note that the magneizing inductor (Lm) shown here isan integral part of the transformer, and not a separate physical inductor.

102


Figure 3.4: Equivalent circuit of the resonant network of the APWM HB series resonantconverter.

power to the load RL through a high-frequency centre-tapped transformer with turns

ratio N : 1 : 1, a diode rectifier (D1, D2) and an output filter Co. The body diodes and

the drain-to-source capacitances (Coss1, Coss2) of the two switches have been explicitly

shown here as they take part in the soft-switching of the switches.

The APWM pole voltage vs is represented by the Fourier series [58]

vs = DVi +∑ √

2Vi√

1− cos 2nπDnπ

sin(nωst+ θn) (3.1)

where, θn = tan−1(

sin 2nπD1− cos 2nπD

)and ωs is the switching frequency (angular) of

the converter. The capacitor Cr blocks the DC component DVi of vs and also forms the

resonant tank with Lr. The equivalent circuit of the resonant network with vs as the

voltage source is shown in Fig. 3.4. The aim is to tune the resonant tank only for the

fundamental ac component of vs. The voltage vs and its fundamental AC component

vs1 are shown in Fig. 3.5. It is clear that vs1 lags the rising edge of vs and leads the

falling edge, both by an angle of θ1. The resonant current is similar to that in [58] and

is given as,

iLr = vs,ac|Zin|

=∑ √

2Vi√

1− cos 2nπDnπ |Zin|

sin(nωst+ θn − φn) (3.2)

where, |Zin| = Rac

√1 +Q0

2(ω − 1

ω

)2and φn = tan−1

[Q0

(ω − 1

ω

)]with,

Rac = 8π2N

2RL (3.3)

Q0 = ωrLrRac

(3.4)

ω = ωsωr

= ωs√LrCr (3.5)

As per first harmonic approximation (FHA), the series resonant tank should be tuned

to deliver the power at the fundamental AC component of vs. Further, for the minimum

103


DT (1-D)T

vg1td

0 Tt1 t4

θ1vg2

t

t

t

t

t

t2 t3 t5

vs

vs1

i’Lr

vCr

vLr

vpri

iLr

iLm

iD1 iD2

i’Lr

t

vCr ≤ NVo

(a)

(b)

(c)

(d)

(e)

(f)

Figure 3.5: Key waveforms of the proposed APWM HB series resonant converter: (a)Switching pulses for top switch (vg1) and bottom switch (vg2); (b) Pole voltage (vs), itsfundamental ac component (vs1) and intended resonant tank current (i′

Lr); (c) Voltage

across resonant capacitor (vCr ) and voltage across transformer primary winding (vpri);(d) Voltage across resonant inductor (vLr ); (e) Resonant tank current (iLr ), intendedresonant tank current (i′

Lr) and magnetizing current (iLm); (f) Currents through output

diodes D1 and D2.

104


circulating current within the resonant tank, the current, iLr is expected in phase with

the fundamental AC component of vs, which means φn = 0. Therefore, the resonant

current is expressed as (3.6).

iLr =√

2Vi√

1− cos(2πD) sin(ωst+ θ1)πRac

(3.6)

Fig. 3.5 shows the key waveforms of the converter operation. Although the converter

is topologically similar to an LLC resonant converter, the magnetizing inductance Lm

does not take part in resonance and just provide some auxiliary current to ensure ZVS

of the switches, as will be seen in the following sections. Moreover, unlike LLC resonant

converter, the output voltage regulation in this case is done by variation of duty ratio and

not switching frequency. The proposed converter is operated at the resonant frequency

ωr of the series tank. i.e., ωs = ωr and ω = 1. Therefore it is found that iLr is in phase

with vs1.

It should be noted that the proposed converter is based on running the series resonant

converter in DCM. However, unlike conventional series resonant converter as in [109,

111], the discontinuity is in the output diode currents and not in the series resonant

inductor current as shown in Fig. 3.5, because the finite amount of magnetizing current

is always flowing through the resonant tank as in an LLC resonant converter. Also, unlike

conventional LLC resonant converter, the discontinuity in the output diode current is

present in only one of the two switching transitions (S2 turn-off and S1 turn-on), and

not in both because of the asymmetric duty ratios of the switches.

3.2.2 Modes of Operation

It is important to mention here that due to parameter variations in practical resonant

circuits, it is almost impossible to operate exactly at the resonant frequency. At best, one

can only achieve a very close to resonant frequency operation. However, for theoretical

analysis, an exact resonant frequency operation can be safely assumed without much

loss of generality.

For simplicity of analysis, following other assumptions are made under the steady-

state operation of the converter.

1. All the devices and components used are ideal.

2. Output filter capacitor Co is large enough to maintain output voltage Vo constant.

Modes of operation of the converter can be subdivided into 6 intervals based on the

time instants shown in Fig. 3.5. Prior to t = 0, the converter is under the deadtime td,

105


where both S1 and S2 are off. The small negative tank current iLr has discharged Coss1

completely and charged Coss2 to Vi, and then started flowing through the body diode

of S1. Output diode D1 is conducting, and therefore the transformer primary voltage

vpri has been clamped to NVo.

Interval 1 (0 < t 6 t1 in Fig. 3.5):

Since the body diode of S1 is conducting, S1 is turned on with ZVS at t = 0, marking

the beginning of this interval as well as the switching cycle. The resonant tank current

iLr starts increasing and eventually crosses zero sometimes during this interval. Output

diode D1 continues to conduct, and therefore vpri is clamped to NVo. The magnetizing

current iLm also crosses zero and becomes positive sometimes during this interval. The

interval lasts until the switching pulse vg1 of S1 is removed. The KVL equation during

this interval is given as,

Vi = vCr (t− t0) + vLr (t− t0) +NVo , 0 < t 6 t1 (3.7)

Interval 2 (t1 < t 6 t2 in Fig. 3.5):

S1 is turned off at the beginning of this interval and the deadtime td starts. The large

positive tank current iLr quickly discharges Coss2 and charges Coss1 to Vi, and then

starts flowing through the body diode of S2. The input source gets isolated following

this instance and the power transfer to the load is continued by the resonant circuit.

Output diode D1 is still conducting, and therefore vpri is clamped to NVo. The KVL

equation during this interval is given as,

vCoss2(t− t1) = vCr (t− t1) + vLr (t− t1) +NVo , t1 < t 6 t2 (3.8)


Since the body diode of S2 is conducting, S2 is turned on with ZVS at the beginning of

this interval. iLr now flows through the channel of S2, instead of its body diode. The

resonance in the tank continues as in Interval 2 with D1 still conducting, and therefore

vpri clamped to NVo. This interval ends when vpri changes its polarity from positive to

negative. The magnetizing current iLm reaches its positive peak value at the end of this

interval. The KVL equation during this interval is same as that of the previous interval,

and is given as,

vCoss2(t− t2) = vCr (t− t2) + vLr (t− t2) +NVo , t2 < t 6 t3 (3.9)

106



This interval is basically the negative half of iLr . The current iD1 through the output

diode D1 becomes zero at the beginning of this interval. Diode D2 starts conducting and

therefore vpri gets clamped to −NVo. The magnetizing current iLm starts decreasing

from its positive peak value, crosses zero and, at the end of this interval, reaches its

negative peak value. The complete second half of the resonant cycle occurs in this

interval as depicted in Fig. 3.5. At the end of this interval, the current iD2 through the

output diode D2 becomes zero and the resonant tank gets isolated from the load. The

KVL equation during this interval is given as,

0 = vCr (t− t3) + vLr (t− t3)−NVo , t3 < t 6 t4 (3.10)


Since iD2 has become zero at the beginning of this interval and none of the output diodes

is conducting, vpri is no longer clamped to −NVo and it changes to a certain positive

value. The power supply to the load is continued by the output capacitor Co. Since

there is no reflected load current iRac , only the negative magnetizing current iLm flows

through the resonant tank circuit. Applying KVL, vpri can be calculated as,

vpri(t− t4) = −vCr (t− t4)− vLr (t− t4) , t4 < t 6 t5 (3.11)

There is no switching taking place in this interval. The magnetizing current iLm

starts increasing from its negative peak value because vpri changes polarity from negative

to positive. However it is important to note that, at the end of this interval, iLm still

remains negative. The interval lasts until the switching pulse vg2 of S2 is removed.

Interval 6 (t5 < t 6 T in Fig. 3.5):

The bottom switch S2 is turned off at the beginning of this interval and the deadtime td

starts. The small negative magnetizing current iLm discharges Coss1 and charges Coss2

to Vi. Applying KVL, vpri can be calculated as,

vpri(t− t5) = vCoss2(t− t5)− vCr (t− t5)− vLr (t− t5) , t5 < t 6 T. (3.12)

Thus, vpri will eventually exceed NVo thereby turning on D1 during this period.

The moment D1 turns on, vpri gets clamped to NVo. The reflected load current iRac

starts building up from zero to positive. The magnetizing current iLm , which started

107

3.3. Design Guidelines

increasing from its negative peak at t4, still has sufficiently large negative value so that

the resultant iLr remains negative till the end of this interval (t = T ). When the

charging of Coss2 and simultaneous discharging of Coss1 is complete, the small negative

iLr flows through the body diode of S1, thereby assisting in ZVS turn-on of S1 at t = T .

The circuit reverts back to Interval 1 after this when S1 is turned on.

3.2.3 Calculation of Input Power

For calculation of the input power, the average of the input current is required. It is

clear from Fig. 3.1 that the input current of the converter is same as the top-switch

current iS1. Considering only the fundamental component, iS1 can be approximated as,

iS1

= (Vi −NVo)

√Cr/Lr sinω0t

+NVo(t+ θ1T/2π − T/4)/Lm , 0 < t 6 DT

= 0 , DT < t 6 T.

(3.13)

Therefore, the input power can be approximated as,

Pi,fund = 1T

∫ DT

0ViiS1dt

= Vi(Vi −NVo)√Cr/Lr(1− cos 2πD)/(2π)

+ ViNVoDT (2πD + 2θ1 − π)/(4πLm).

(3.14)

3.3 Design Guidelines

The behaviour of the circuit at certain instants of the switching period which will lead

to the design procedure of the converter are explained in this section. The time instants

mentioned in this section also are from Fig. 3.5.

At the Instance t = t1:

As can be seen in Fig. 3.5, at t = t1 when S1 turns off, iLr has a significantly large

positive value. This is valid in general for any load or input voltage condition of the

APWM HB resonant converter as long as ωs = ωr and D < 0.5. This means that ZVS

of S2 is always guaranteed. However, the same is not true for S1 as seen in Fig. 3.5 at

t = T . A negative iLr (T ) is needed for ZVS of S1, which is not easy to obtain as long

as iLr is in phase with vs1.


108


As shown in Fig. 3.5, at t = t4, iD2 and vs1 become zero, and the transformer primary

voltage is obtained (assuming negligible voltage drop across Lr) as,

vpri(t4) ≈ −vCr (t4) (3.15)

Now, if |vCr (t4)| > NVo, D1 will turn-on and there will be a reflected positive load

current iRac on the primary side as shown by the dotted curve in Fig. 3.5. Then a

higher negative iLm will be required to get a resultant negative iLr in order to ensure

ZVS of S1. Thus, to ensure D1 does not turn-on at t = t4, the condition maintained in

this work is,

|vCr (t4)| 6 NVo (3.16)

It is important to note here that any combination of Lr and Cr (that maintains

ωs = ωr) works fine with |vCr (t4)| 6 NVo. In fact, it is found that, the lesser vCr (t4)

is as compared to NVo, the easier it is to achieve ZVS for S1. This is because for

|vCr (t4)| < NVo, vpri becomes asymmetric in such a way that results in iLm having

a negative DC shift. This extra negative DC shift of iLm , although acts in favour of

achieving ZVS for S1, may saturate the transformer core. Therefore, the optimal design

condition is,

|vCr (t4)| = NVo (3.17)


As discussed in the previous section, after the deadtime td has started at t = t5, vpri

eventually exceeds NVo, thereby turning on D1, and iRac starts building up from zero

to positive. Therefore, iLm which started increasing from its negative peak at t = t4,

still has to be sufficiently negative so that the resultant iLr remains negative till t = T

to ensure ZVS of S1.

From the above discussion, the two main design conditions to be followed in this

work can be summarized as follows.

1. The magnitude of the negative peak of the voltage across the series resonant

capacitor should be equal to N times the specified output voltage of the converter,

where N is the transformer turns ratio (|vCr (t4)| = NVo).

2. The switching frequency of the converter should be slightly greater than or equal

to the resonant frequency of the resonant tank (ωs ≥ ωr).

109

3.4. Design Procedure

3.4 Design Procedure

The goal is to design the APWM resonant converter for minimum input voltage and

maximum load at maximum allowable duty Dmax. By doing so, for an increasing input

voltage or a decreasing load, the output voltage can be regulated just by decreasing the

duty ratio D.

3.4.1 Calculation of Transformer Turns Ratio

The transformer turns ratio can be calculated from the voltage conversion ratio derived

in [59] and [105] as shown in (3.18).

VoVin

=√

1− cos 2πD2√

2N1√

1 +Q2(ω − 1ω )2

(3.18)

The proposed converter has ω = 1. So, the transformer turns ratio N , which cor-

responds to minimum input voltage and maximum load at maximum allowable duty

Dmax, is calculated as (3.19).

N = Vi,min√

1− cos 2πDmax

2√

2Vo(3.19)

3.4.2 Design of Magnetizing Inductance

The optimum design of the magnetizing inductance of the transformer, is critical for

high performance. Since the output capacitance (Coss) of the low voltage MOSFETs

used in PoL converters is very high (in the range of 100 pF to 1 nF), the energy needed to

discharge the capacitor from input voltage to zero voltage is also substantially high (1~10

µJ). This implies that the magnetizing inductance of the transformer has to be very low,

resulting in increased losses. Although significant amount of literature addresses the

design of magnetizing inductance in LLC and APWM resonant converters [49,55,57,112],

there is a lack of unanimity in regard to the equivalent circuit to be considered during

the deadtime. For instance, references [57, 63] include only the magnetizing inductance

(Lm), while others [54, 55] consider both magnetizing and series inductances (Lm and

Lr). However, none of these designs are universally applicable for any combination

of input voltage, output voltage, rated power and operating frequency. For example,

the study in [54] indicates a limitation of switching frequency for its optimal design of

magnetizing inductance and deadtime. Another approach is to consider the discharge

of Coss to be linear instead of being resonant. However, a linear discharge requires a

110


vds1

0

td

π/2

vg1

Vi

Ce

q =

2C

oss

vCeq

ieq

+

- +

-

Le

q =

Lr

π

(a) (b)

t5 T

vCeq

Figure 3.6: (a) Equivalent circuit of the primary side during the deadtime. (b) Keywaveforms for calculation of magnetizing inductance and deadtime.

large magnetizing current and there is a lack of proper attention to optimize the value

of this current. A new method of design of magnetizing inductance is presented here

to overcome the aforementioned issues. The method can also be extended to normal

variable-frequency LLC converters.

The magnetizing inductance of the transformer should be designed in such a way

that it provides just enough current for the switches to achieve ZVS at the worst case,

which in this work, is considered as 10% load at maximum input voltage. However, at

lower loads, vpri does not remain a symmetrical square wave (and iLm gets a negative

DC shift), which make the calculations difficult. Therefore the calculation of Lm in

this section is actually done for the full load condition at Vi,max with the intention of

providing sufficient margin to take care of the low load condition. Interestingly though,

the negative DC shift of iLm in low load conditions actually assists in ZVS of the switches

(S1 in particular), rendering the necessity of the said margin to be minimal.

This work proposes a different equivalent circuit for the primary side network of the

converter during the deadtime td (from t5 to T ) with the sole consideration of the series

resonant inductor Lr. The designed LC network is shown in Fig. 3.6(a) with the initial

conditions [54] of: vCeq (0) = 0 and iLeq (0) = iLr (t5) = iLm(t5). Since the voltage across

Lm is clamped to NVo, it does not participate in the resonance during the deadtime.

Similarly, Cr also does not participate in this resonance because its voltage does not

change significantly during the deadtime. Only Lr with the initial current of iLm(t5)

resonates with 2Coss and shows zero initial voltage during the deadtime.

Assuming the voltage at the primary side vpri is a symmetrical square wave, the

slope of iLm is obtained as NVoLm

. So, iLm(t5), and therefore iLeq (0) is given by,

iLeq (0) = iLm(t5) = NVoT

2Lm

(12 −

θ′

1π

)(3.20)

111


where θ′

1 corresponds to the maximum input voltage Vi,max and is given by θ′

1 =

tan−1(

sin 2πDmin

1− cos 2πDmin

)with Dmin = 1

2π cos−1

(1− 8N2V 2

0V 2i,max

). With such initial con-

ditions, the voltage vCeq for this LC network can be solved as,

vCeq (t) = iLeq (0)

√LeqCeq

sin(ω′t) = NVoT

2Lm

(12 −

θ′

1π

)√Lr

2Cosssin(ω′t) (3.21)

where ω′ = 1√2LrCoss

. At the end of the deadtime, vCeq should become equal to

Vi,max. Therefore, the marginal ZVS conditions for this case [57] are,

td = 14 ×

2πω′

(3.22)

vCeq (td) = Vi,max (3.23)

Further simplification of (3.22) and (3.23) gives the direct expressions of deadtime

and magnetizing inductance as follows.

td = (π/2)√Lr2Coss (3.24)

Lm =NVoT

(12 −

θ′1π

)√Lr

2Coss(2Vi)

(3.25)

This also complies with the condition that the available energy (Eavailable) in Leq is

exactly equal to the energy needed (Eneeded) to charge Ceq to Vi, [49].

Eavailable = (1/2)Lri2Leq (0) (3.26)

Eneeded = (1/2)× 2Cossv2Ceq (td) = Cossv

2Ceq (td) (3.27)

It shows that the sizing approach in (3.24) and (3.25) provides an ideal valley-

switching and works for the system specification regarding to the input voltage, output

voltage, rated power and operating frequency. However, the effect of parasitic elements,

such as the transformer secondary winding leakage inductance and the output diode

capacitance, are not considered for the circuit design. The parasitic components always

show nonlinear and unpredictable nature and cause ringing at the switching point, af-

fecting the ZVS of the switches. These effects must be taken into account in practical

design cases, as will be shown later in this chapter.

112


3.4.3 Design of the Resonant Tank

It has been already explained that the optimal design condition is: |vCr (t4)| = NVo.

The voltage across the capacitor Cr is obtained as [58],

vCr = DVi + vCr,ac = DVi −∑ √

2Vi√

1− cos 2nπDπn2ωs |Zin|Cr

cos(nωst+ θn − φn) (3.28)

Equation (3.28) can not give the exact value of vCr at t = t4 directly. However, a

valid approximation can be made by considering only the fundamental ac component

vCr,ac1 , which is at its negative peak at t = t4.

NVo = −vCr (t4) ≈ −DVi + vCr,ac1,peak (3.29)

Replacing Vi = Vi,min, n = 1, ωs = ωr = 1√LrCr

, |Zin| = Rac, t = t4 and D = Dmax

in (3.28) and then substituting into (3.29), the following equation is obtained.

√LrCr

= πRac(NVo +DmaxVi,min)4NVo

(3.30)

The other obvious equation relating Lr and Cr is:√LrCr = 1

ωr. Thus Lr and Cr

can be solved as,

Lr = πRac(NVo +DmaxVi,min)4NVoωr

(3.31)

Cr = 4NVoπωrRac(NVo +DmaxVi,min) . (3.32)

3.4.4 Correction Factor and Quality Factor

The quality factor Q0 of the tank can be calculated as,

Q0 = ωrLrRac

= π

4

[1 + 2

√2Dmax√

1− cos 2πDmax

]. (3.33)

It is interesting to note that this Q0 is the maximum achievable Q0 for the design

condition as mentioned in (3.17) and it does not depend on anything else other than the

maximum allowable duty Dmax. Fig. 3.7 shows the variation of maximum achievable

Q0 with respect to Dmax. For Dmax = 0.5, Q0 = π/2 = 1.57, which is the absolute

maximum achievable Q0 for the proposed converter design. Also, the approximation in

(3.29) is accurate only for Dmax = 0.5. For values of Dmax lesser than 0.5, with the

calculated values of Lr and Cr as per (3.31) and (3.32) respectively, |vCr (t4)| is not equal

to NVo; rather it is a little lesser than NVo as depicted in Fig. 3.5. This difference is

113


Figure 3.7: Variation of maximum achievable quality factorQ0 with respect to maximumallowable duty Dmax.

attributed to all the harmonics present in vCr . As a result, with Dmax less than 0.5, the

maximum achievable Q0 also becomes less than π/2 as shown in (3.33) and Fig. 3.7.

In section 3.3, it has been discussed that, for |vCr (t4)| < NVo (which is equivalent

of Q0 < π/2), there will be undesired DC shift in the magnetizing current iLm . A

correction factor ε, as defined below, can be introduced to correct the values of Lr and

Cr as per (3.35), so as to maintain Q0 = π/2 for all values of Dmax.

ε = 2

1 + 2√

2Dmax√1− cos 2πDmax

(3.34)

L′

r = εLr and C′

r = Crε

(3.35)

3.4.5 Parameter Variations

Finally, a major factor in designing any resonant converter is to take care of the tol-

erance and derating-over-time of the inductors and the capacitors. These parameter

variations can be as high as ±20%, which will shift the resonant frequency accordingly.

A digitally implemented Pulse-width Locked Loop (PWLL) for automatic resonant fre-

quency tracking has been presented in [114] for LLC converter, which takes care of these

variations very efficiently. The same control scheme can be adopted and implemented

for the proposed topology. The reader is referred to [114] for further details on control

implementation, as it is out of the scope of this work.

The design procedure presented here can be summarized in the form of a flowchart

as shown in Fig. 3.8.

114


Is Isw,rms < 0.75ID ?

Start

Approximate Ii,rms from ηPi/Vi

Select S1 and S2 having V(BR)DSS > Vi,max and

ID > Ii,rms

Calculate Coss for the desired operating

point

Choose Dmax = 0.45

Specify Vi , Vo , Po , fs and

expected η

Calculate N from (3.19)

Calculate Lr and Cr from (3.31), (3.32) and

(3.35)

Calculate td from (3.24) and Lm from (3.25)

Calculate Isw,rms from tank current

End

Sel

ect

S1 a

nd

S2 w

ith l

esse

r I D

rat

ing

Yes

No

Figure 3.8: Flowchart of design procedure of the proposed APWM HB resonant con-verter.

115

3.5. Design Implementation in Data Center PoL Converters

Table 3.1: Specifications for Design of the Proposed APWM HB Resonant Converter

Parameter Name Symbol ValueInput voltage Vi 43-53 VOutput voltage Vo 5 VOutput power Po 30 WSwitching frequency fs 500 kHz

3.5 Design Implementation in Data Center PoL Con-

verters

To validate the design procedure discussed above, this section presents the example of

design of an APWM converter that meets the specifications of a typical PoL converter in

data center loads. The converter parameters are listed in Table 3.1. A reference design

of the modified APWM converter based on existing literature [59,105] as shown in Fig.

3.2, is also presented in parallel for comparative evaluation.

Before proceeding further in to the design, Coss and td must be specified. The device

IRL520NPBF, which complies with the requirements as specified in [115] is selected for

this study. The average Coss is calculated based on the method specified in [59] and

found to be 147.9 pF at 43 V input, and 133.2 pF at 53 V input. A rounded-off value

of 150 pF is used for all other calculations in this work. A deadtime of 60 ns according

to (3.24) is chosen for both the converters.

Furthermore, there will be voltage drops occurring in various elements of the practical

circuit, especially in the output diodes, which need to be compensated. Assuming a 0.5

V drop in each of the output diodes, Vo in all calculations is substituted as 5.5 V. Also,

Dmax is chosen as 0.45 (and not 0.5) to give some more margin for compensation and

to ensure the DCM operation.

3.5.1 Reference Design

The design process of the reference topology of the modified APWM converter as shown

in Fig. 3.2, is governed by (3.4), (3.5), (3.3) and (3.18). The first step is to fix the

values of Q0 and ω for the particular design. However, the choice of Q0 and ω presented

in [58, 59, 105] is somewhat heuristic and the ranges of Q0 and ω recommended therein

for achieving ZVS over wide range of load and input voltage variations are as follows.

1.5 6 Q0 6 2.5 and 1.05 6 ω 6 1.3 (3.36)

For proper comparison with the proposed converter, Q0 and ω for the reference

116


Table 3.2: Design Comparison of the Proposed APWM HB Converter and the ReferenceConverter

Parameter Name Symbol Reference Design Value Proposed Design ValueRelative operating freq. ω 1.1 1Full load quality factor Qo 1.57 1.57Maximum duty ratio D 0.45 0.45Deadtime td 60 ns 60 nsSwitch output capacitance Coss 150 pF 150 pFTransformer turns-ratio N 3.5 4Resonant inductance Lr 5 µH 5 µHResonant capacitance Cr 24.7 nF 20 nFMagnetizing inductance Lm 170 µH 20 µHAuxiliary inductance La 20 µH NAAuxiliary capacitance Ca 2.2 µF NAOutput filter capacitance Co 0.2 mF 0.2 mF

Table 3.3: Important Components Used for the Two Converter Prototypes

Component Name Symbol Part No.MOSFET S1, S2 IRL520NPbFDiode D1, D2 VS-STPS40L15CTPbFPrimary-side driver IXDN609SIResonant capacitor Cr B32641B0103J, B32529C6472K289Output capacitor Co UPS1H221MPD1TDAuxiliary capacitor Ca PHE426KF7220JR06L2

converter are selected as 1.57 and 1.1 respectively. Other parameters calculated/chosen

are listed in Table 3.2. The auxiliary inductor value La is chosen as high as possible

such that the auxiliary current is just enough to ensure ZVS of the top switch at the

worst case (i.e., at maximum input voltage of 53V with minimum load of 3W).

3.5.2 Proposed Design

As mentioned before, the values of Q0 and ω for the proposed converter are 1.57 and

1 respectively. Following the design procedure of the previous section other parameters

of the converter are obtained and listed in Table 3.2. It may be noted that the value of

Lm used in in Table 3.2 for the proposed design is 30% lesser than the calculated value

of 29 µH from (3.23). This is determined heuristically from the experiment to account

for the ringing effects of the parasitic elements, as discussed before.

It is evident from Table 3.2 that both the designs are almost similar to each other.

The magnetizing inductance in the proposed topology serves the same purpose as that

of the auxiliary inductance in the reference topology. The important components used

in the two experimental prototypes are given in Table 3.3.

117

3.5. Design Implementation in Data Center PoL Converters

3.5.3 Physical Design of Magnetic Components

The physical design of the magnetic components in this work has been done following

the guidelines laid down in [116]. However, for the sake of completeness, the key design

equations and procedures are presented here.

For inductor:

First, the required area product is calculated by (3.37) and a core having area product

more than the required value is chosen.

ACAW = LIpIrmskwBmJ

(3.37)

Here, AC and AW are the cross-section area and the window area of the core respec-

tively. L is the desired inductance value, Ip and Irms are the peak and the RMS values

of inductor current respectively. The constant kw is the window utilization factor, Bm is

the maximum flux density inside the core, and J is the current density of the conductor.

Their values are chosen as 0.5, 0.1 T and 2.5 ×106 A/m2 respectively.

Then, the number of turns nind is calculated as per (3.37) and the nearest integer

value is chosen.

nind = LIpBmAC

(3.38)

In the next step, the required air-gap lg is calculated as per (3.37), where µ0 =

4π × 10−7 H/m is the permeability of free space.

lg = µ0nindIpBm

(3.39)

Finally, to avoid the effects of fringing flux the following inequality is checked and

confirmed.

lg <<√AC (3.40)

For the design of all the magnetic components in this work, it is ensured that lg is

at least 10 times smaller than√AC .

For transformer:

For the design of the transformer, the primary and secondary voltages are assumed

to be square waves. First, the required area product is calculated by (3.41) and a core

having area product more than the required value is chosen.

118


Table 3.4: Details of Magnetic Components Used for the Two Converter Prototypes

Component Reference design Proposed DesignTransformer core PQ20/16-3F3 PQ20/16-3F3Primary winding 7 turns of 108/40 litz wire 8 turns of 108/40 litz wireSecondary winding (2+2) turns of 176/40 litz wire (2+2) turns of 176/40 litz wireAir-gap 0 0.27 mmResonant inductor core PQ20/16-3F3 PQ20/16-3F3Resonant inductor winding 5 turns of 108/40 litz wire 5 turns of 108/40 litz wireResonant inductor air-gap 0.5 mm 0.5 mmAuxiliary inductor core PQ20/16-3F3 NAAuxiliary inductor winding 10 turns of 108/40 litz wire NAAuxiliary inductor air-gap 0.5 mm NA

ACAW = P

2fskwJBm(3.41)

Here, P is the rated power of the transformer and fs is the switching frequency. The

numbers of turns in the primary winding (nP ) and the secondary winding (nS) are then

calculated as per (3.42), where VP and VS correspond to the peak values of the primary

and the secondary voltages respectively.

nP = VP4fsBmAC

; nS = VS4fsBmAC

(3.42)

As for the air-gap, the same procedure is followed as in the design of the inductor

assuming the transformer is the magnetizing inductor.

The optimum design of the converters call for the most optimized design of the mag-

netic elements. However, the aim of this study is just to compare the two designs using

similar design parameters. Therefore, the choices of the magnetic components as listed

in Table 3.4, though not the optimum choices, are good enough for this comparative

study. Appropriate air-gaps were provided in the inductors and the transformers to ad-

just the values of inductances, and also to avoid core saturation. The value of resonant

inductance provided in Table 3.2 is the sum of the transformer leakage inductance and

the external series inductance added.

3.6 Experimental Results and Discussions

Both the designs presented in the previous section were simulated in PSIM. Two separate

laboratory prototypes, as shown in Fig. 3.9, were also built and tested. The results

obtained from the simulations as well as from the experiments are discussed in this

section.

119


Aux. capacitors

Aux. inductorResonant inductor

Resonant capacitor

Transformer

Output diodes

Output capacitor

MOSFETs

Figure 3.9: Laboratory prototypes of the proposed APWM HB converter and the refer-ence converter from [59]. The reference converter needs more pcb area to accommodatethe auxiliary LC network.

Figure 3.10: Comparison of different currents (RMS) of the two converters.

0

0.5

1

1.5

2

Pow

er

loss (

W)

Full load at Vi = 48 V

Proposed syst Reference syst

Figure 3.11: Comparison of different losses in the two converters.

120


vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

For Vi = 43V

iLa (0.2A/div)

vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

For Vi = 48V

iLa (0.2A/div)

vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

For Vi = 53V

iLa (0.2A/div)

Figure 3.12: Experimental demonstration of ZVS of top switch S1 of the referenceconverter at full load for different input voltages.

Fig. 3.10 shows the comparative values of the different RMS currents of the two

topologies as obtained from the simulations. It can be seen that, the reference topology

has higher tank current at higher loads because it maintains ω > 1. Whereas, the

proposed topology has higher tank current at lower loads owing to the presence of

the extra magnetizing current in the resonant tank. However, the reference topology

always has some auxiliary inductor current which is completely absent in the proposed

topology. Now, in both the topologies, it is the resonant tank current that affects the

losses in almost all the elements (MOSFET, resonant capacitor, resonant inductor and

transformer). Whereas, the effect of the auxiliary current on losses in the reference

topology is localized to only the MOSFETs and the auxiliary LC network. Therefore,

the effect of the tank current should be more pronounced than the auxiliary current

in the overall efficiency and it is expected that the reference converter will have lower

efficiency for higher loads, and higher efficiency for lower loads.

It can be also inferred from Fig. 3.10 that, the switch current of the reference

topology, which consists of the tank current and the auxiliary current, is higher than

the switch current of the proposed topology, which is only the tank current, for all

loading conditions.

121


vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

200ns/div

For Vi = 43V

iLa (0.1A/div)

vds1 (20V/div)

vg1 (5V/div)

200ns/div

For Vi = 48V

iLr (0.5A/div)

iLa (0.1A/div)

vds1 (20V/div)

vg1 (5V/div)

200ns/div

For Vi = 53V

iLr (0.5A/div)

iLa (0.1A/div)

Figure 3.13: Experimental demonstration of ZVS of top switch S1 of the referenceconverter at 10% load for different input voltages.

Fig. 3.11 shows the various power losses in the two converters at full load for an

input voltage of 48 V. The loss computation in this study is done in the similar way as

described in [61,63] and therefore, is not elaborated in details here. It can be seen that,

even though the losses in the auxiliary elements (La and Ca) of the reference system

are quite small, the extra circulating current in the resonant tank due to ω = 1.1 has

caused the overall loss in the reference system to be higher than that in the proposed

system.

For the sake of completion, the expressions of various currents of the two systems

are provided in the Appendix. The MOSFETs have only conduction loss and turn-off

loss as they achieve zero voltage turn-on for all line and load conditions. Similarly the

diodes have only conduction loss and no reverse-recovery loss as they are always turned-

off with zero current. The magnetic components have both copper loss and core loss,

and the capacitors have some conduction loss due to their equivalent series resistance.

The losses in the gate driver circuits are not taken into account in this study as the gate

drivers are powered separately.

Figs. 3.12, 3.13, 3.14 and 3.15 show the experimental demonstration of zero-voltage

turn-on (ZVS) of the top switch S1 for both the converters at two extreme loading

122


vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div

For Vi = 43V

For Vi = 48V

For Vi = 53V

Figure 3.14: Experimental demonstration of ZVS of top switch S1 of the proposedconverter at full load for different input voltages.

vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

200ns/div

For Vi = 43V

vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

200ns/div

For Vi = 48V

vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

200ns/div

For Vi = 53V

Figure 3.15: Experimental demonstration of ZVS of top switch S1 of the proposedconverter at 10% load for different input voltages.

123


Figure 3.16: Comparative experimental efficiency plots of the two converters.

conditions and at different input voltages. It is clear that S1 in both the converters

achieves marginal ZVS at the worst case (i.e., at maximum input voltage of 53V with

minimum load of 3W). The zero-voltage turn-on of the bottom switch S2 can also be

inferred from these figures. Since iLr has a high positive value before the turning-on

of S2, Coss2 is discharged very fast and the ZVS of S2 is achieved very easily. Another

important aspect noted from these figures is that, S1 has to turn-off with almost the

peak of the resonant tank current iLr , which makes the turn-off loss of S1 higher than

that of S2, which turns-off with only the small magnetizing/auxiliary current. Also, the

drain-to-source voltage ringing is seen to be higher at S1 turn-off as compared to that

at S2 turn-off because of the same reason.

For instance, at the rated power of 30 W with the nominal input voltage of 48 V, the

top switch S1 has the turn-off loss of 0.724 W (by turning-off the peak resonant tank

current of 2.74 A), while the bottom switch S2 has the turn-off loss of only 0.127 W (by

turning-off the peak magnetizing current of 0.48 A). This shows the difference of the

proposed converter from the frequency controlled half-bridge series resonant converter

operating in DCM and also from the conventional half-bridge LLC resonant converter.

The frequency controlled half-bridge series resonant converter operating in DCM will

have absolutely zero turn-off loss for both the switches because of the presence of dis-

continuity in the resonant tank current during both the switching transitions; and the

half-bridge LLC resonant converter will have finite turn-off loss (overall lesser turn-off

loss than the proposed converter) for both the switches because of the presence of small

magnetizing current during both the switching transitions. However, as explained in

the introduction of this chapter, both frequency controlled half-bridge series resonant

converter operating in DCM, and LLC resonant converter are frequency-controlled and,

therefore, are not suitable for PoL applications.

Fig. 3.16 shows the comparative experimental efficiency of the two converters over

the entire load range for different input voltages. It is clear that the reference converter

124


Full load @ Vi = 53V,

Lr = 4μH, fs = 560kHz

10% load @ Vi = 53V,


Full load @ Vi = 53V,


10% load @ Vi = 53V,


vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

200ns/div 200ns/div

200ns/div 200ns/div

vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

vds1 (20V/div)

vg1 (5V/div)

iLr (1A/div)

vds1 (20V/div)

vg1 (5V/div)

iLr (0.5A/div)

Figure 3.17: Experimental demonstration of ZVS of top switch S1 of the proposedconverter for ±20% variation of resonant inductor.

vpri (50V/div)

iLr (5A/div)

vCr (50V/div)

400ns/div

Figure 3.18: Capacitor voltage vCr and transformer primary voltage vpri along with theresonant tank current iLr at full load condition of the experimental set-up.

has lower efficiency for medium to full load range, but higher efficiency in low load range,

which matches perfectly with the expectations of the analysis and simulation. It is to

be noted here that the efficiency measurements are carried out excluding the gate-driver

losses.

Finally, to show the robustness of the proposed design procedure, a variation of ±20%

was introduced for the value of the resonant inductor, and the switching frequency was

adjusted accordingly to match the actual resonant frequency. Fig. 3.17 shows that

the proposed converter can still achieve ZVS for the extreme input voltage and loading

conditions, which proves the efficacy of the proposed solution.

The capacitor voltage vCr and transformer primary voltage vpri along with the res-

onant tank current iLr at full load condition of the experimental set-up is shown in Fig.

3.18. It is clear from Fig. 3.18 that, unlike what is shown in Fig. 3.5, vpri is not perfectly

clamped to the reflected output voltage in any of its half cycles. It has a high frequency

125

3.7. Comparison of Different APWM HB Resonant Topologies

0.00745313 0.00746094 0.00746875

Time (s)

0

-50

-100

-150

50

100

150

Vcr Vpri I(L2)*10

vpri

iLr x 10

vCr

100

50

0

-50

-100

-150

150

0.00745313 0.00746094 0.00746875

Time (s)

Figure 3.19: Capacitor voltage vCr and transformer primary voltage vpri along with theresonant tank current iLr at full load condition of the simulated system.

ripple (of the order of megahertz) and a low frequency ripple (500kHz) riding over it.

The high frequency ripple is caused by the output diode capacitance ringing with trans-

former leakage inductance. The low frequency ripple is seen because the voltage is not

measured across only Lm, rather it is measured across the series combination of Lm and

the leakage inductance of the transformer Llk. Since Llk is non-zero for the practical

transformer, the small voltage drop across Llk is added to the vpri measurement. The

same result can be reproduced in simulation by splitting Lr into two series connected

inductors of values 4.5µH and 0.5µH (where 0.5 is the value of Llk) and then measuring

vpri across the series combination of Llk and Lm. This is shown in Fig. 3.19.

3.7 Comparison of Different APWM HB Resonant

Topologies

A qualitative comparison of the proposed topology and other APWM HB resonant

topologies is presented in Table 3.5. It is clear that, out of all the topologies being

compared, only the proposed topology can achieve ZVS over complete range of load and

input voltage without any extra component and with minimum circulating current.

3.8 Summary

This chapter has shown that the standard APWM HB resonant converter, without

any auxiliary circuit or extra component, can achieve soft-switching over the complete

range of input voltage and load variation with the help of proper design of the resonant

tank and the magnetizing inductance of the transformer. Apart from having minimum

component-count, it gives better efficiency than its counterparts for a wide range of load

126


Table 3.5: Comparison of Different APWM HB Resonant Topologies

Topology Extra componentused for ZVS ZVS range Full-load circulating current

Proposed Nil Complete range ofload and input voltage Minimal, since ω = 1

Modified series-resonantAPWM converter [59]

One auxiliary inductor andtwo auxiliary capacitors

Complete range ofload and input voltage

Higher than proposed,since ω > 1

CLL resonant APWMconverter [53]

One parallel inductor inthe resonant tank

Complete range of loadand input voltage


Topology in [108] One MOSFET in series withone of the output diodes

Very limited range ofinput voltage

Similar as proposed,since ω = 1

SR-APWM converter [58] Nil Very limited range ofinput voltage


variation. The circulating current is minimized not only by operating the converter at

the resonant frequency, but also by optimizing the magnetizing current. The design

equations derived in this chapter are going to be used in the next chapter for design of

the lower converter of the proposed nine-switch single-stage isolated three-phase AC-DC

converter.

127

Chapter 4

A Nine-Switch Interleaved

Three-Phase AC-DC Single

Stage Isolated Converter

It has been proven in Chapter 2 that the nine-switch converter can have relatively lower

losses as compared to the twelve-switch back-to-back (BTB) converter, if the upper

terminal is feeding a DC load and the lower terminal is drawing power from an AC source.

Using this configuration, a power supply was developed for a 380 V DC data-center load,

fed in parallel from a three-phase AC grid (120 V rms-phase-voltage) and a DC source

(400 V DC). However, the DC output voltage generated therein is non-isolated, which

is generally not accepted for modern day power architecture inside data centers. This

chapter proposes an isolated single-stage three-phase AC-DC converter based on the

nine-switch bridge, with many other added features like interleaved operation, soft-

switching etc., which make it a potential candidate for data center loads.

4.1 Introduction

As discussed in Chapter 1, three-phase AC-DC power supply units (PSU) having input

power factor correction (PFC) capability and giving an isolated DC output of typically

48 V are widely used for powering telecom devices etc [22,24]. Also, it has been discussed

that the future DC based data centers are envisioned to be operating at a room-level

distribution voltage of 380 V DC, which has to come from these PSUs. Conventionally,

in such a PSU, there are two stages of conversion: front-end being the PFC and AC-DC

128

4. A Nine-Switch Interleaved Three-Phase AC-DC Single Stage Isolated Converter

conversion stage, while the back-end accomplishes the DC-DC conversion with isolation.

The literature review in Chapter 1 also showed that six-switch active front-end (AFE)

boost rectifier is usually preferred in the first stage because of its compatibility with

universal three-phase input voltage (210Vrms < Vl−l < 480Vrms), direct input current

control, and least number of active switch count. On the other hand, resonant topologies

are gaining popularity for the high-frequency-transformer-isolated DC-DC conversion in

the second stage because of their simple capacitive output filter, soft-switching feature,

and limited voltage-stress on the switches.

In pursuit of reduction of cost, size and complexity of the two-stage AC-DC power

conversion for data center applications, several single-stage converters have been pro-

posed in the literature [52, 64–73]. Generally, they either integrate a three-phase boost

rectifier with an isolated DC-DC stage [52, 72], or combine three single-phase, single-

stage isolated converters into a three-phase isolated converter [71]. Almost all of the

single-stage AC-DC converters proposed in literature operate in Discontinuous Conduc-

tion Mode (DCM) of the input current. Operation in DCM offers many advantages

such as natural power factor correction, reduction of turn-on switching losses and diode

reverse recovery losses, and so on [64]. However, there are numerous design challenges,

as discussed in Chapter 1, arising from the high current peaks of DCM operation. This

has restricted the use of these single-stage AC-DC converters in data center applications.

A major improvement is possible in single-stage conversion when interleaving is em-

ployed. Interleaving at the front-end allows reduction of the current peaks and reduces

the discontinuity in the current waveform before and after the interleaving nodes [68,73].

However, there are two major issues related to such interleaved single-stage A-DC con-

verters not only have more active switches, but also require active current control for

balancing the power output from the three phases [73].

The other possibility of harnessing the benefits of interleaved operation is applying

it at the back-end DC-DC stage. This can reduce the output filtering requirements,

besides reducing the conduction losses in the output rectifier especially for high current

output as in data center loads [76, 117, 118]. But such natural interleaving cannot be

realized in any of the three phase PFC single-stage AC-DC converters reported in the

literature.

To overcome these issues, this chapter presents a novel single-stage three-phase AC-

DC isolated converter, based on a nine-switch bridge topology. The proposed converter

integrates a three-phase active front-end (AFE) boost PFC rectifier and three phase-

interleaved half-bridge DC-DC resonant converters in a single stage. In a conventional

129


two-stage configuration this integration requires twelve switches, which implies that the

proposed converter yields a 25% saving in device count. A novel three-carrier modulation

technique is also introduced for controlling both the PFC stage and the interleaved DC-

DC stage. Thus the output voltage ripple is reduced by 67% without any additional

hardware for modulation and control. It has been shown in this chapter that the choice

of sawtooth carrier wave over triangular carrier wave leads to reduced switching loss

for this converter. Moreover, despite being a single-stage topology, the PFC stage of

the converter operates in Continuous Conduction Mode (CCM), and thus eliminates all

the issues related to DCM. The proposed topology is therefore an ideal candidate for

single-stage AC-DC power conversion in DC based data centers.

The constraints in the modulation of the nine-switch converter, as discussed in Chap-

ter 2, result into higher than usual DC-link voltage (more than 750 V for universal input

voltage). Moreover, the interleaved modulation strategy adopted in this work requires

high switching frequency operation to limit the input current Total Harmonic Distortion

(THD). A suitable MOSFET for such high voltage and high frequency operation was not

commercially available until recently. But with the recent advent of the Silicon Carbide

(SiC) MOSFETs rated for 900 V and above [119], this converter has become practically

realizable with high frequency operation.

4.2 Steady State Operation

4.2.1 Topology and Equivalent Circuit Model

Fig. 4.1 shows the proposed nine-switch converter based single-stage three-phase AC-

DC isolated power conversion system. For convenience, it is assumed that the converter

is composed of a “three-phase AFE boost PFC rectifier” and three “half-bridge DC-

DC resonant converters” as shown in Figs. 4.2(b) and 4.2(c) respectively. They are

also referred as the “upper converter” and the “lower converters” respectively. The

three middle switches are shared between these two converters. The boost PFC section,

controlling the input power factor and the DC link voltage Vdc, consists of the upper

three switches SA,B,C along with the OR-ed combination of the middle three switches

SAX,BY,CZ and the bottom three switches SX,Y,Z . Similarly the three half bridge DC-

DC converters are comprised of SX,Y,Z along with the OR-ed combination of SAX,BY,CZ

and SA,B,C . This is illustrated clearly in Fig. 4.2.

Since the three DC-DC converters are connected in parallel to the load, the use of

three phase shifted carrier signals, as explained in the next sections, imposes three high

130


SA SB SC

SAX SBY SCZ

SZSYSX

Cdc

Ls

Lr

vS

+

Vdc

-

AB

C

ZY

X

N

P

CoRL

+

Vo

-

Cr

Figure 4.1: Proposed nine-switch converter based single-stage three-phase AC-DC con-verter.

frequency phase shifted PWM waveforms of magnitude Vdc across the three resonant

tanks consisting of series inductor Lr, series capacitor Cr and the magnetizing induc-

tance Lm of the transformer. Thus, a parallel operation of three interleaved half-bridge

DC-DC resonant converters is realized, each of which can be controlled either by the

frequency or by the duty cycle of the uni-polar PWM waveforms vXN,Y N,ZN .

The primary issue in a nine-switch converter is the sharing of the middle switches

by the upper and the lower halves of the converter, giving rise to a switching constraint

that requires the upper terminal modulation reference to be always placed above the

lower terminal modulation reference [82]. This forces the modulation indices to be less

than 1, causing increase of line current THD [120] and DC-link voltage. However, in

the applications related to integration of DC sources like solar energy, battery etc. to

the grid using the nine-switch converter [87, 95], these disadvantages are avoided to a

large extent. In these cases, a DC signal is used as the lower modulation reference.

Since the voltages of these DC sources are low, the lower modulation index can be as

low as 0.2 which means the upper modulation index can be as high as 0.8. Hence, the

DC-link voltage Vdc can be kept lower (albeit higher than a BTB converter) and the

input current THD is also lowered. This work has utilized this advantage, along with

the incorporation of a modified modulation technique and interleaved resonant converter

operation to develop a high performance isolated PSU for data center loads.

4.2.2 Modulation

For generation of switching signals three sine waves RefA,B,C for the upper converter

and three DC signals RefX,Y,Z for the lower converter are used as modulation signals

131


SA

SB

SC

SA

XS

BY

SC

Z

SZ

SY

SX

Cd

c

LsL

r

vS

+Vd

c

-

AB

CZY

X

N P

Co

RL

+Vo

-

Cr ia

ix

iSA

iSA

X

iSX

SA

SB

SC

SA

XS

BY

SC

Z

SZ

SY

SX

Cd

c

Ls

vS

+Vd

c

-

AB

C

N P

iaSA’

SB’

SC’

SA

SA

X

SX

Cd

cL

r

+Vd

c

-X

N P

3RL

+Vo

-

Cr

ix

SX’

=+

3

(a)

(b)

(c)

13C

o

Figure4.2:Proposed

single-stageAC-D

Cconverterand

itsdecomposition

intoathree-phase

boostPFCrectifierand

threehalf-bridge

DC-D

Cresonantconverters.

132


RefA

RefCRefBvcarr,A

RefX,Y,Z

2m

lo2

mu

p

vcarr,B vcarr,C

1

-1

0

Figure 4.3: Proposed three-carrier modulation scheme for the nine-switch converter.Note that in practice, carrier frequency is much higher than the modulation referencefrequency.

RefA1

-1

0

vg,A

vg,AX

vg,X

vAN

vXN

RefX

vcarr,A

Vdc

Vdc

t1 t2 t3 t4(a) t5

ia, ixia

-ix

RefA

RefX

vcarr,A

Vdc

Vdc

ia-ix

(b)

2fsfs

Figure 4.4: Generation of gate pulses for the switches of the first leg and the key terminalvoltages and currents of the same leg for – (a) sawtooth carrier, and (b) triangularcarrier. It is apparent that with triangular carrier, the middle switch operates at twicethe switching frequency (2fs).

133


as usual. But for carrier signal, instead of using a single sawtooth wave, three separate

sawtooth waves vcarr,[A,B,C] are used, one for each leg. These three sawtooth waves

are 120 phase shifted from each other as shown in Fig. 4.3. As such, the following

modulation signals are defined for the first leg.

RefA = MA sinω0t+MOA = mup sinω0t+MOA

RefX = −MOX = 2mlo − 1(4.1)

Here, ω0 is the angular line frequency; mup (or MA), mlo are the modulation indices

of the upper and the lower converters respectively; andMOA, MOX are the offsets given

to the modulation signals. Fig. 4.4 shows the generation of gate pulses for the switches

of the first leg where,

vg,AX = vg,A ⊕ vg,X .

It should be noted here that, although the choice of carrier between triangular wave-

form and sawtooth waveform does not make much difference in normal three-phase

Sine-PWM (SPWM) converters, it makes a significant difference in terms of switching

loss for the case of the nine-switch converter. As can be found in almost all the existing

literature [82,83,87,88,95], owing to the XOR operation, the middle switches operate at

twice the switching frequency (2fs), because a triangular carrier has been used every-

where. Whereas, a sawtooth carrier, as used in this work, retains the switching frequency

of the middle switches at fs while maintaining the XOR condition unchanged, as can

be seen from Fig. 4.4(a). This results in overall lower switching loss for the converter.

As shown in Fig. 4.4(a), the XOR implements the time-multiplexing of the states of

the middle switches. For example, for the time segment [t1, t3] when switch SA is ON,

all that is needed is node A in Fig. 4.2 should not connect to node N (i.e. the negative

DC bus), and for that it is enough to have either switch SAX or switch SX in OFF

state, which is ensured as seen in the diagram (SAX is OFF for the time segments [t1,

t2] and SX is OFF for the time segment [t2, t3]). So the fundamental component of vAN

is exactly of the shape of RefA and not at all affected by the XOR operation. Similar is

true for the lower converter. For the time segment [t3, t5] when switch SX is ON, node

X should not connect to node P (i.e. the positive DC bus), and for that it is enough to

have either of SA and SAX in OFF state, which is ensured. So the normalized average

of vXN is exactly equal to mlo as desired. This is to emphasize that the XOR does not

impose any coupling between the upper converter and the lower converter and they can

be controlled independently [82,83,87,88].

134


PIVdc_ref

Vdc iq_ref = 0

id_ref

id

iq

Boost PFC contro ller

PLLvasvbsvcs

ω0t

PI

+

_

abc/dqiaibic

dq/abc

RefA

vm_d

vm_q

PIVo_ref

Vo

RefX,Y,Z

Output DC voltage controller

+_+_

RefB

RefC

Figure 4.5: Overall control scheme for the proposed nine-switch converter.

The use of three separate carriers for each leg does not affect the operation of the

upper converter other than slightly distorting the input current waveforms. However, for

high frequency carriers, this distortion is negligible; whereas some significant advantage

is achieved in the lower converters by doing so. The resonant tank input voltages vXN ,

vY N and vZN are now phase shifted to each other by 120. Thus, the high frequency

ripple in the final isolated DC output voltage Vo is decreased three times and so is

the required value of the output filter capacitor Co for a given allowable ripple content

in Vo. It may be noted here that typically in data center operations, the output DC

voltage should have less than 1.5% peak to peak ripple at rated power [74]. Each of

the three DC-DC half bridge resonant converters are controlled by constant frequency

Asymmetrical Pulse Width Modulation (APWM) [59, 121] and the duty ratio of each

of the lower most switches are realized by comparing three DC signals RefX,Y,Z with

the three sawtooth carrier waveforms vcarr,[A,B,C] such that RefX,Y,Z is less than the

minimum value of RefA,B,C .

4.2.3 Control

It is well established in the literature, that the XOR operation does not impose any

coupling between the “upper converter” and the “lower converter” and they can be

controlled independently [82,83].

A standard two loop control in d − q frame for stabilization of DC link voltage Vdc

as well as correction of power factor by input current control is applied for the upper

converter. For the lower converters, a simple PI controller is provided to regulate the

output voltage Vo by controlling RefX,Y,Z . The overall control scheme is shown in

Fig. 4.5. Also, Fig. 4.6 shows the PLECS implementation of the proposed control and

135

4.3. Design Aspects and Simulation of the Proposed Converter

Figure 4.6: PLECS simulation of the proposed control and modulation scheme.

modulation scheme. For simultaneous implementation of the controllers the modulation

indices mup and mlo are chosen first according to the input voltage and desired DC link

voltage [122] as per (4.2) and (4.3).

Vdc = 2vllpk/(√

3mup) (4.2)

mup +mlo = 1 (4.3)

Here, vllpk is the peak amplitude of line to line AC input voltage. The amplitude

band of the carriers is now divided into two windows of width 2mup and 2mlo as shown

in Fig. 4.3. The modulating waves RefA,B,C and RefX,Y,Z are varied within these

windows as per the variation of input voltage and load current respectively. Since the

theoretical duty ratios of the lower converters vary from 0 to mlo, APWM resonant

converter operation [59, 121] is implemented to ensure ZVS of its switches as shown in

Fig. 4.2.

4.3 Design Aspects and Simulation of the Proposed

Converter

This section deals with the design of the proposed converter with the help of mathe-

matical analysis as well as simulation. MATLAB and PLECS have been used for the

simulations.

4.3.1 Choice of DC-link Voltage

The DC link voltage Vdc is inversely proportional to the upper converter modulation

indexmup as given by (4.2). Hence, it is desired to havemup close to 1 to have minimum

Vdc. However, for APWM control of the DC-DC resonant converters, the lower converter

136


0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 03

4

5

6

7

8

9

Input

curre

nt TH

D (%)

S w i t c h i n g f r e q u e n c y ( k H z )

t h r e e - c a r r i e r m o d u l a t i o n s i n g l e - c a r r i e r m o d u l a t i o n

Figure 4.7: Simulated THD variations of input currents w.r.t. switching frequency forsingle-carrier vs. proposed three-carrier modulation.

modulation index mlo should also be sufficiently high (close to 0.5 ) [59, 121], forcing

mup to be less than 1 as per (4.3). Thus, a trade-off has to be made according to (4.2)

and (4.3) while choosing the values of Vdc, mup and mlo. For the proposed system, these

values are chosen as 570 V, 0.6 and 0.35 respectively for a three-phase input voltage of

120 V (line-to-neutral, rms).

4.3.2 Choice of Switching Frequency

Due to the use of three-carrier modulation, there will be some added distortions in

the three-phase input currents. Fig. 4.7 shows the simulated THD variations of the

three-phase input currents w.r.t. switching frequency for the standard single-carrier

modulation and for the proposed three-carrier modulation at rated power. This clearly

shows that the switching frequency should be much higher than the line frequency to

obtain lower THD of the input currents. Moreover, the integration of the resonant

converters with the PFC stage ensures soft-switching of the switches, which facilitates

high switching frequency operation, also enabling the reduction of the size of the resonant

tanks. For the proposed system, a switching frequency of 60 kHz was chosen, which gives

about 6% THD of input current at full-load as per Fig. 4.7. As will be seen later in the

results section, all the harmonic profile of the proposed converter complies with the IEC

61000-3-2 standard for Class A type loads like the ICT equipment racks in data centers.

137


4.3.3 Design of Boost Inductor and DC-link Capacitor

This part of the design is similar to any three-phase boost PFC rectifier [22]. The boost

inductor is designed based on the current ripple at the switching frequency according to

(4.4).

Ls = (vllpk − 3vllpk2/2Vdc)/(IafsδiL,pp) (4.4)

Here, Ia is the peak of the a-phase current, fs is the switching frequency and δiL,pp is

the percentage of peak-to-peak ripple of the inductor current w.r.t. its peak value. For

the proposed system, a 1.5 mH boost inductance results into about 12% peak-to-peak

ripple in the current.

DC-link capacitance value is calculated based on the requirement of energy during

transients as per (4.5).

Cdc = 2Poth/(V12 − V2

2) (4.5)

Here, Po is the output power, th is the transient duration considered, and V1 and

V2 are the initial and final voltages of the DC-link capacitor respectively during the

transient. For the proposed system, a DC-link capacitance of 605 µF is selected, which

provides about 80 V margin for a transient duration of one line-cycle (2π/ω).

4.3.4 Design of Resonant Tank and the High-Frequency Trans-

formers

Design of this part is done following the procedure in [121]. For the sake of completion,

the key design equations are reproduced here. The aim is to operate the converter at

the resonant frequency of the resonant tank to achieve load-independent ZVS assisted

by minimal magnetizing current.

The average output capacitance Coss as described in [59] is used for ZVS considera-

tion of the switches. The transformer turns ratio N can be calculated as

N = Vdc√

1− cos(2πmlo)/(2√

2Vo). (4.6)

The two resonant tank elements Lr and Cr are defined by (4.7) and (4.8) respectively,

Lr = επRac(NVo +mloVdc)/(4NVoωr), (4.7)

Cr = 4NVo/(επωrRac(NVo +mloVdc)), (4.8)

138


with

ε = 2/(1 + 2√

2mlo/√

1− cos(2πmlo)). (4.9)

Here, ωr is the resonant frequency (angular) of the resonant tank, which is essentially

the switching frequency (angular) of the converter. Rac is the reflected equivalent load

resistance, defined as

Rac = 8N2(3RL)/π2.

The required deadtime td and the magnetizing inductance Lm are obtained form

(4.10) and (4.11) respectively.

td = (π/2)√Lr2Coss (4.10)

Lm =NVoT

( 12 −

θ1π

)√ Lr2Coss

(2Vi)(4.11)

where

θ1 = tan−1(sin(2πmlo)/(1− cos(2πmlo))).

It is to be noted here, that the actual Lm used for ZVS in simulation and experiment

is smaller than the value calculated from (4.11). This is to account for the cancellation

of terminal currents at certain portions of the input current line-cycle as explained in

the next section.

4.3.5 Controller Design

As explained earlier, there is no coupling between the “upper converter” and the “lower

converter” in terms of control. Therefore their controllers are designed independently.

4.3.5.1 Controller Design for Boost PFC Part

Neglecting the cross-coupling between d and q components of the currents for a balanced

three-phase system, the plant transfer functions of the boost PFC rectifier for a standard

two-loop control in d− q frame [28] can be obtained as (4.12), (4.13) and (4.14).

Gid(s) = id(s)dd(s)

= −2sCdcVdc − 4Po/Vdc6s2LsCdc + 6sLsPo/V 2

dc + 3v2llpk

/V 2dc

(4.12)

Giq(s) = iq(s)/dq(s) = −Vdc/(3sLs) (4.13)

139


Gvdc(s) = vdc(s)id(s)

=3vllpkVdc

2sCdcV 2dc + 2Po

+Po/vllpk

(sCdc + Po/V 2dc)

×

[6s2LsCdc + 6sLsPo/V 2

dc + 3v2llpk

/V 2dc

−2sCdcVdc − 4Po/Vdc

] (4.14)

Here, id, iq are the d and q components of the input current; dd, dq are the d and q

components of the duty ratio of the top switch. Substituting the values of parameters

from Table 4.1, the above transfer functions can be written in their pole-zero forms as

follows.

Gid(s) = id(s)dd(s)

= −126720(s+ 15.261)(s+ 3.82− 382.82i)(s+ 3.82 + 382.82i)

Giq(s) = iq(s)/dq(s) = −570/(0.0045s)

Gvdc(s) = vdc(s)id(s)

= −0.0666(s+ 8)(s+ 8)(s− 19203)(s+ 7.8894)(s+ 7.3969)(s+ 15.2279)

A cascaded two loop-control with the PI controllers as mentioned in Table 4.1 is

applied for this part of the converter. The bode plots of the d and q loop current

controllers for 100% and 10% loads are shown in Figs. 4.8 and 4.9 respectively. Similarly,

the bode plots of the DC-link voltage controller for 100% and 10% loads are shown in Fig.

4.10. It is evident that the plant transfer function of the DC-link voltage controller vdc(s)id(s)

has a Right Half Plane (RHP) zero at 19203 rad/s or 3 kHz, which is also visible in Fig.

4.10. This effectively reduces the phase margin of the system and affects the stability,

unless the controller bandwidth is designed far below (at least 1/10-th) the RHP zero

frequency. For the proposed converter, the DC-link voltage controller bandwidth is

chosen as 30 Hz. Note that in absence of the RHP zero, this bandwidth could have been

chosen as 6 kHz (1/10-th of the switching frequency).

4.3.5.2 Controller Design for DC-DC Resonant Part

While designing the controller for this part, it is important to know the low frequency

variations in the envelope of the output voltage with the duty ratio mlo as shown in Fig.

4.11(a). Change in the low frequency envelope vo(t) of the output voltage is given by

(1/3)Codvo(t)/dt = N 〈iLr 〉 − vo(t)/(3RL), (4.15)

where 〈iLr 〉 is the average of the resonant inductor current. This leads to the plant

140


-50

0

50

100M

agni

tude

(dB

) id_by_ddid_closeloopid_by_dd_lowid_closeloop_low

100 101 102 103 104 105 106-180-135

-90-45

04590

135180

Pha

se (

deg)

Frequency (Hz)

Figure 4.8: Bode plots of d-loop current controller for 100% and 10% loads.

-50

0

50

100

Mag

nitu

de (

dB) iq_by_dq

iq_closeloopiq_by_dq_lowiq_closeloop_low

100 101 102 103 104 105 106-90

-45

0

45

90

Pha

se (

deg)

Frequency (Hz)

Figure 4.9: Bode plots of q-loop current controller for 100% and 10% loads.

141


Mag

nitu

de (

dB)

-100

-50

0

50

100 101 102 103 104 105 106

Pha

se (

deg)

-180

-135

-90

-45

0

vdc_by_idvdc_closeloopvdc_by_id_lowvdc_closeloop_low

Frequency (Hz)

Figure 4.10: Bode plots of DC-link voltage controller for 100% and 10% loads.

Low frequency

varying envelope

of output voltage

iD1 iD2

vo

t

t

Average rectifier

current

iLr

vo

(a) (b)

D1

D2

Figure 4.11: (a) Transformer equivalent circuit along with output rectifier, and (b) Lowfrequency variations in rectifier currents and output voltage with varying duty ratio mlo

for a constant load.

142


Mag

nitu

de (

dB)

-100

-50

0

50

vo_by_mlovo_closeloopvo_by_mlo_lowvo_closeloop_low

100 101 102 103 104 105 106

Pha

se (

deg)

-135

-90

-45

0

Frequency (Hz)

Figure 4.12: Bode plots of output voltage controller for 100% and 10% loads.

transfer function of vo(s) w.r.t. mlo(s).

Gvo(s) = vo(s)mlo(s)

= Vdc sin(2πmlo)4N√

1− cos(2πmlo)1

1 + sRLCo(4.16)

A simple PI controller as mentioned in Table 4.1 is sufficient for this part as well.

The bode plots of the output voltage controller for 100% and 10% loads are shown in

Fig. 4.12.

As a summary of this section, the complete list of converter parameters calculated/-

chosen for simulation as well as experiment is presented in Table 4.1.

4.4 Prototype Implementation and Theoretical Loss

Analysis

This section deals with the selection of device and components for prototype implemen-

tation and the theoretical loss distribution in various components of the converter.

4.4.1 Switch RMS Currents

For the device selection, apart from the blocking voltage, the continuous current carrying

capability is to be considered. The instantaneous switch currents of the first leg of the

converter are tabulated in Fig. 4.13. Assuming unity power factor operation, the RMS

143

4.4. Prototype Implementation and Theoretical Loss Analysis

Table 4.1: Converter Parameters for Design of the Proposed Single-Stage Nine-SwitchConverter with 48 V Output

Parameter name Symbol ValueRated power Po 1.5 kWInput voltage (line-neutral, rms) vs 120 V, 60 HzOutput voltage Vo 48 VSwitching frequency fs 60 kHzLoad resistance RL 1.536 ΩInput boost inductance Ls 1.5 mHDC-link voltage Vdc 570 VDC-link capacitance Cdc 0.605 mFUpper converter duty ratio mup 0.6Lower converter duty ratio mlo 0.35Transformer turns ratio N 5.3Resonant inductance Lr 435 µHResonant capacitance Cr 16 nFSwitch output capacitance Coss 41 pFDeadtime td 415 nsTransformer magnetizing inductance Lm 2.6 mHOutput filter capacitance Co 0.22 mFd-current controller kp,id + ki,id/s 0.2+2000/sq-current controller kp,iq + ki,iq/s 0.2+2000/sDC-link voltage controller kp,vdc + ki,vdc/s 0.1+5/sOutput voltage controller kp,vo + ki,vo/s 0.1+500/sSampling frequency fsamp 120 kHz

of the top switch current iSA can be obtained as

ISA,rms =

√ω0

2π

∫ 2πω0

0

[ia

2T2

T+ (ia + ix)2T3

T

]dt, (4.17)

where, ia = Ia sinω0t

ix = Ix sinnω0t

(4.18)

T1 = 0.5T (1−RefA)

T2 = 0.5T (RefA −RefX)

T3 = 0.5T (1 +RefX).

(4.19)

Here, n is the ratio of the carrier frequency to the line frequency. Substitution of

(4.18), (4.19), (4.1) into (4.17) leads to

ISA,rms = (0.5)√

(1 +MOA)Ia2 + (1−MOX)Ix2. (4.20)

Similarly, the RMSs of the middle switch current iSAX and the bottom switch current

144


RefA

1

-1

0

iSA

RefX

vcarr,A

T1 T2 T3

T

iSAX

iSX

StateSA , SAX , SX 0, 1, 1

0

ia(ia + ix)

1, 0, 1

-ia0

ix

1, 1, 0

-(ia + ix)

-ix0

Switch

Current

Figure 4.13: Instantaneous currents through the switches of the first leg of the proposednine-switch converter at different switching states.

iSX can be obtained as follows.

ISAX,rms = (0.5)√

(1−MOA)Ia2 + (1−MOX)Ix2 (4.21)

ISX,rms = (0.5)√

(1−MOA)Ia2 + (1 +MOX)Ix2 (4.22)

Note that the lower terminal current ix is a First Harmonic Approximation (FHA)

of the actual resonant tank current [121].

4.4.2 Occurrence of Soft Switching

As in any three-phase boost PFC converter operating in CCM, the top switch achieves

ZVS only for positive half of the line-cycle of the input current. However, the middle and

bottom switches do not undergo ZVS for the whole line-cycle, even though the “lower

converter” is designed as per [121] for achieving full-range ZVS of its switches. This is

due to the cancellation of terminal currents ia and ix during the switching transitions.

As shown in Fig. 4.13, during the transition of switching states from [1, 1, 0] to [0, 1, 1],

the current through SX is (ia + ix), which has to be negative in order for SX to achieve

ZVS. However, from Fig. 4.14, it can be seen that |ix| < |ia| for π/4 < ω0t < 3π/4.

Therefore, despite ix being negative during this period, iSX is not negative, resulting in

loss of ZVS for SX . Same is true for the middle switch SAX .

Based on the above reasoning, the ZVS regions of each switch of a leg within a

line-cycle of the corresponding input phase current are marked in Fig. 4.14. The Zero-

Voltage Turn-Off regions of the switches are also indicated in the same figure. It can be

noted that the conduction of the body diode of the MOSFET before its turn-off causes

it to undergo a Zero-Voltage Turn-Off.

145


ia

ix

SA

SAX, SX

SA, SX

SAX

ω0t

π/4 3π/4 π 2π

ZVS Zero-Voltage Turn-Off

Figure 4.14: Identification of soft-switching areas of the switches of the first leg of theproposed nine-switch converter within a line-cycle of the phase current ia.

Table 4.2: Comparison of Switching Devices for Design of the Proposed Single-StageNine-Switch Converter

Parameter (at Tc = 25C) IPW90R500C3 C3M0280090DGate charge (Qg) 68 nC 9.5 nCGate energy (Qg × Vg) 0.95 µJ, Vg = 10V/− 4V 0.18 µJ, Vg = 15V/− 4VOn resistance (RDS,on) at Tj = 25C 0.39 Ω 0.28 ΩOn resistance (RDS,on) at Tj = 150C 1.1 Ω 0.385 ΩOutput capacitance (Coss) [59] 132 pF 41 pFFigure-of-merit-1 ((RDS,on × Coss)−0.5) [123] 1.39× 105 2.95× 105

Figure-of-merit-2 (RDS,on ×Qg) [119] 2.652× 10−8 0.266× 10−8

Diode reverse recovery time (trr) 480 ns 20 nsDiode peak reverse recovery current (Irrm) 31 A 3.4 ADiode forward voltage (VSD) 0.8 V 4.8 V

146


4.4.3 Selection of Switching Devices

Depending on the blocking voltage and the continuous current carrying capability, two

devices have been short-listed: IPW90R500C3 (a Si-MOSFET) and C3M0280090D (a

SiC-MOSFET) for realization of the converter. They are compared here in terms of loss.

References [119, 123, 124] have listed out some performance metrics that show the

superiority of SiC devices over Si devices. The two devices discussed here are compared

based on those metrics in Table 4.2 to show why the C3M0280090D is a better choice, if

not the only choice, among these two devices, to meet the Energy Star 80PLUS platinum

efficiency requirements [125] in data center applications. As per [59], Coss of the two

devices at the operating DC-link voltage of 570 V are determined as 132 pF and 41 pF

respectively. This indicates almost 70% reduction of switching loss for the C3M0280090D

device. Additionally, for a change of junction temperature (Tj) of 25C to 150C, a 182%

rise of RDS,on is noted from Table 4.2 for the IPW90R500C3 device; whereas the same

is only 37.5% for the C3M0280090D device. This gives lesser conduction loss for the

C3M0280090D based converter even at elevated ambient temperature.

Moreover, the faster body diode of the SiC device improves the conversion efficiency

by achieving an exceptionally low reverse recovery loss due to very small reverse recovery

current [124]. The low reverse recovery current also results in reduced switching noise

and improved filter design. These are more important in particular for CCM PFC, as

implemented in this work, because no significant improvement is expected for DCM PFC

as the recovery current from the diode does not influence the total conversion loss [124].

The conduction loss for all the three switches of a leg can be found from the RMS

current expressions presented in the previous subsection. Further, the simulation results

presented in Fig. 4.14 show that the top switches undergo hard-switching for half a line-

cycle, and the middle and bottom switches undergo hard-switching for one quarter of

a line-cycle. Taking note of these facts, the total losses in the switches of one leg of

the converter have been calculated and compared for the two short-listed devices in

Fig. 4.15, which shows that the losses for C3M0280090D is less than half of that for

IPW90R500C3. Thus, it is obvious from this discussion that the lone disadvantage of

higher diode forward voltage of the SiC-MOSFET is practically over-shadowed by the

numerous advantages of using it instead of a Si-MOSFET.

4.4.4 Loss Distributions

Table 4.3 lists out the important components used in the laboratory prototype of the

proposed converter. Similarly, Table 4.4 presents the details of the magnetic components.

147


Figure 4.15: Comparison of theoretical losses in the switches of a leg for the two devicesconsidered in this work.

Table 4.3: Important Components Used for the Proposed Single-Stage Nine-SwitchConverter Prototype

Component name Part numberMOSFET C3M0280090DOutput diode STPS80170CWMOSFET driver ACPL-W346-060EResonant capacitor B32672L8103J000, B32672L8562J000Output capacitor UPJ2A560MPDDC-link capacitor B32654A6684J, B32774D8505K, LLG2W391MELA50, LGL2W821MELC50

Data from these two tables have been used for loss analysis of the converter.

Fig. 4.16 shows the various losses in the converter at full-load condition. The loss

computation in this study is done in the similar way as described in [63,123] and there-

fore, is not elaborated in details here. However, some key loss equations are provided

here for reference.

Table 4.4: Details of Magnetic Components Used for the Proposed Single-Stage Nine-Switch Converter Prototype

Component DetailsBoost inductor core MP5812MPFC-HITACHI METGLAS alloy 2605SA1Boost inductor winding 100 turns of AWG14 copper wireTransformer core PQ32/30-3C95Primary winding 26 turns of 85/39 litz wireSecondary winding (5+5) turns of 280/39 litz wireResonant inductor core PQ32/30-3C95Resonant inductor winding 48 turns of 85/39 litz wire

148


0

5

10

15

20

25

30

35

Pow

er

loss (

W)

Total loss at full load = 109.7 W

Figure 4.16: Theoretical loss calculated for various components of the proposed nine-switch converter at the rated power of 1.5 kW.

4.4.4.1 Switch turn-on loss

From Fig. 4.14, the average turn-on losses of the switches can be obtained as follows.

Pon,SA = (1/(2π))∫ 2π

π

0.5CossVdc2dt

Pon,SAX = Pon,SX = (1/(2π))∫ 3π

4

π4

0.5CossVdc2dt

4.4.4.2 Switch turn-off loss

The turn-off current of each switch can be noted from Fig. 4.13. Since fs ω0/2π, it

can be assumed that the area under the curve of (ia + ix) is equal to the area under

the curve of ia. With this assumption, following are the turn-off losses of the top switch

(SA) and the middle switch (SAX), where tf is the fall-time of the switch.

Poff,SA = VdcIatffs2π/ω0

[∫ π4ω0

0sin(ω0t)dt+

∫ 2πω0

3π4ω0

sin(ω0t)dt]

Poff,SAX = VdcIatffs2π/ω0

∫ πω0

0sin(ω0t)dt

As per Fig. 4.4(a), the bottom switch always turns OFF with ix(t2) = iLm(t2) =

149


NVoT (0.5− θ1/π)/(2Lm) [121]. So, the bottom switch turn-off loss is given as

Poff,SX = Vdcix(t2)tffs2π/ω0

[∫ π4ω0

0sin(ω0t)dt+

∫ 2πω0

3π4ω0

sin(ω0t)dt].

4.4.4.3 Inductor core loss

Inductor core loss is given by

Pcore = kfe(∆B)βAC lm, (4.23)

where kfe, AC and lm are core loss co-efficient, core cross-sectional area and core

magnetic path length respectively. These parameters and the constant β can be deter-

mined from loss chart and datasheet. ∆B is the peak-to-peak variation of flux density

at switching frequency. The line-frequency (60 Hz) variation of flux inside the boost in-

ductor (Ls) core is neglected. Equation (4.23) is therefore valid for both boost inductor

(Ls) and resonant inductor (Lr).

4.4.5 Validation of Choice of Sawtooth Carrier over Triangular

Carrier

As discussed before, the choice of sawtooth carrier over a triangular carrier makes a

difference in terms of switching loss of the middle switches in case of a nine-switch

converter. The validation for the same is provided in this subsection.

The proposed converter is modulated with a novel three-carrier modulation scheme in

order to realize switching-frequency-phase-interleaving of the DC-DC stage, which causes

increased THD of input currents as compared to a standard single-carrier modulation as

shown in Fig. 4.7. Therefore, the reason for operating the proposed converter with high

switching frequency (more than 50 kHz) is to reduce the input current THD as seen in

Fig. 4.7 irrespective of the choice of carrier waveform. Now, even though the triangular

carrier, in general, gives lower THD than sawtooth carrier, it causes more switching loss

in the nine-switch converter by doubling the effective switching frequency of the middle

switches. The comparison of losses in the middle switch of one leg of the converter for

the two types of carrier is shown in Fig. 4.17, which clearly shows more switching loss

in case of triangular carrier.

It may also be noted that the sawtooth carrier will introduce measurement noise to

the sensors when the sampling point happens to be the switching point. Such noise can

be critical in analog controller where complex analog filters are difficult to implement.

150


0

0.5

1

1.5

2

2.5

3

3.5

triangular sawtooth

Po

we

r lo

ss (

w)

Pcond Psw

Figure 4.17: Comparison of switching losses in the middle switch of a leg for the twotypes of carrier.

TransformersMicrocontroller

(F28335)

Gate-driver

boards

Power board

3-phase input

DC output

(isolated)

DC-link

capacitors

Figure 4.18: Laboratory prototype of the proposed converter (boost inductors notshown). Dimensions without heat-sink: 17cm× 14cm× 5cm.

But in most cases, as in this work, the controllers for such three-phase converters are

implemented digitally. With a properly designed digital filter, these noises can be elim-

inated, which is demonstrated by the experimental waveforms presented in this work.

A digital low-pass 3rd order Butterworth filter with cut-off frequency of 20 kHz was

implemented in a F28335 DSP in this case.

4.5 Results and Discussions

A laboratory prototype of the proposed 1.5 kW converter, as shown in Fig. 4.18, was

built and tested. The results obtained from the experiment are discussed in this section.

Some essential results from PLECS simulation are also presented alongside the experi-

mental results to show their close agreement with each other, which demonstrates the

validity and high practicability of the proposed converter.

151

4.5. Results and Discussions

va 10×ia

Vo

Io

(a) From simulation.

ia (5A/div)

Vo (20V/div)Io (10A/div)

va (50V/div)

5ms/div

5ms/div

(b) From experiment.

Figure 4.19: Key input and output waveforms of the proposed nine-switch converter atthe rated power of 1.5 kW.

Fig. 4.19 shows the key input and output waveforms of the test set-up. It is observed

that the system is operating at close-to-unity power factor (0.99) and the output DC

voltage and currents are stable at 48 V and 31 A respectively. The full-load efficiency

of the converter is measured as 93.4%.

The three-phase input currents along with the phase-a voltage are shown in Fig.

4.20. It is clear that even with the proposed three-carrier modulation scheme the input

currents are well-balanced.

The harmonic profiles of the input current at full load and at 50% load are shown in

Figs. 4.21 and 4.22 respectively. It is apparent that, in both the cases, all the harmonic

components are well within the limits specified by IEC 61000-3-2 for Class A type loads.

The THD values of 6.12% and 7.52% can be noted from the figures for full load and

152


va

ia

ib

ic


ia (2A/div)

va (50V/div)

ib (2A/div)

ic (2A/div)

5ms/div

5ms/div

5ms/div

5ms/div


Figure 4.20: Three phase balanced input currents and phase-a voltage of the proposednine-switch converter at full-load condition.

153


THD = 6.12%

ia (2A/div)

5ms/div

0.5A/div, 248Hz/div

Figure 4.21: Harmonic spectrum of input current at full-load condition.

THD = 7.52%

ia (2A/div)

5ms/div

0.5A/div, 248Hz/div

Figure 4.22: Harmonic spectrum of input current at 50% load condition.

50% load respectively. These THD values are as expected from Fig. 4.7, which indicate

that they can be within 5% if the switching frequency is pushed to 90 kHz or more.

The dynamic performance of the converter is shown by Fig. 4.23 for step changes of

load from 50% to 100% and vice-versa.

Figs. 4.24 and 4.25 show the occurrence of ZVS for the three switches of a leg of

the converter at different points of the corresponding phase current. As can be seen,

the middle and the bottom switches are not able to achieve ZVS for π/4 < ω0t < 3π/4,

where |ia| > |ix| at the transition of switching states from [1,1,0] to [0,1,1]. The Zero-

Voltage Turn-Off regions of the switches also can be identified from Figs. 4.24 and 4.25.

These are in clear agreement with the analysis and simulation presented in the previous

sections. These figures also demonstrate clearly the XOR operation performed between

the top and bottom switch gate signals to obtain the gate signal for the middle switch.

To compare with the simulation, Fig. 4.26 shows the simulated waveforms for ZVS of

top and bottom switch at ω0t = π/2 of input current as an example case.

154


(a)

(b)

200ms/div)

Io (20A/div)

Vo (20V/div)

Vdc (100V/div)

va (400V/div)

ia,b,c (10A/div)

200ms/div)

Io (20A/div)

Vo (20V/div)

Vdc (100V/div)

va (400V/div)

ia,b,c (10A/div)

Figure 4.23: Key experimental waveforms under load transient from – (a) 100% to 50%of rated power, and (b) 50% to 100% of rated power.

155


ix

Vds,AX Vgs,AX

Vgs,A Vds,A

Vds,X Vgs,X

ω0t=0

ω0t=π/4

ω0t=π/2

ω0t=3π/4

ix

Vds,AXVgs,AX

Vgs,AVds,A

Vds,X Vgs,X

Vds,AXVgs,AX

Vgs,AVds,A

Vds,X Vgs,X

ia

Vds,AXVgs,AX

Vgs,AVds,A

Vds,X Vgs,X

ia

ia

ix

iaix

Figure 4.24: Occurrence of ZVS for the three switches of the first leg of the converterat different points of the phase-a current at full-load. Scale: for all vds = 400V/div, forall vgs = 20V/div, for all currents = 5A/div and time = 2µs/div. Note that this figureconforms to the ZVS regions indicated in Fig. 4.14.

156


ω0t=π

ω0t=5π/4

ω0t=3π/2

ω0t=7π/4

Vds,AXVgs,AX

Vgs,AVds,A

Vds,XVgs,X

Vds,AXVgs,AX

Vgs,AVds,A

Vds,XVgs,X

ia

ix

Vds,AXVgs,AX

Vgs,AVds,A

Vds,XVgs,X

ix

Vds,AXVgs,AX

Vgs,AVds,A

Vds,XVgs,X

ia

ix

iaix

ia

Figure 4.25: (Continuation of the previous figure) Occurrence of ZVS for the threeswitches of the first leg of the converter at different points of the phase-a current atfull-load. Scale: for all vds = 400V/div, for all vgs = 20V/div, for all currents = 5A/divand time = 2µs/div. Note that this figure conforms to the ZVS regions indicated inFig. 4.14.

157


Figure 4.26: ZVS of top and bottom switch at ω0t = π/2 of input current (Simulation).Note that the gate voltages (vgs) have been scaled up 50 times.

The operation of the converter at 20% load is shown in Fig. 4.27. It is clear that,

apart from operating in CCM at unity power factor, the converter achieves ZVS of the

middle and the bottom switches even for π/4 < ω0t < 3π/4, since |ia| < |ix| at the

transition from [1,1,0] to [0,1,1] here. Therefore, it can be claimed that the middle and

the bottom switches feature complete line-cycle ZVS at low loads, which is essential for

meeting Energy Star 80PLUS platinum efficiency requirements even at low loads.

Fig. 4.28 shows the three high-frequency resonant tank currents. They are phase

shifted to each other by 120, thereby demonstrating the clear interleaved operation of

the three half-bridge DC-DC resonant converters or the “lower converters”.

It may be noted that the resonant current waveforms presented in Figs. 4.24 and

4.25, 4.27 and 4.28 are similar to those presented in [121], where the small magnetizing

current helps in the ZVS of the middle switch during the tank current discontinuity.

To emphasize the importance of the novel modulation scheme, the ripple comparison

of output voltage for the single-carrier modulation vs. the three-carrier modulation is

shown in Fig. 4.29 for the same output capacitance Co of 220 µF. It is evident that

the use of three-carrier modulation decreases the output voltage ripple by increasing the

ripple frequency by three times. The peak-to-peak ripple is noted as only 1.25% for the

proposed three-carrier modulation, whereas the same is noted as 3.33% for the standard

single-carrier modulation.

Finally, the experimental efficiency plot of the converter is presented in Fig. 4.30

along with the Energy Star 80 PLUS Platinum efficiency standard required for data-

158


va (50V/div)

ia (2A/div)

Vo (20V/div)Io (2A/div)

5ms/div

5ms/div

ia (2A/div)

Vgs,A (20V/div)Vds,A (400V/div)ω0t=π/2

Vgs,AX (20V/div) Vds,AX (400V/div)

Vds,X

(400V/div)Vgs,X (20V/div)

ix (2A/div) 2μs/div

ω0t=3π/2

ia (2A/div)

Vgs,A (20V/div)

Vds,A (500V/div)

Vgs,AX (20V/div)Vds,AX

(500V/div)

Vds,X

(500V/div)

Vgs,X (20V/div)

ix (2A/div)

2μs/div

Figure 4.27: Operation of the converter at 20% load. The middle and bottom switchesof the leg achieve ZVS even at the worst cases.

center applications. It is apparent that the proposed converter meets the said require-

ments for the entire load range.

4.6 Cost Comparison

As for the cost of implementation, Table 4.5 shows the comparison of cost of the main

components required to implement the proposed system based on a nine-switch bridge vs.

based on a conventional twelve-switch back-to-back connected bridge. The comparison

is done for fabrication of 10,000 units of each of the converters and the cost is taken from

http://www.digikey.com/ on 14 March, 2017. DC-link capacitance value is calculated

based on the requirement of energy during transients as per the following equation

Cdc = 2PothV 2

1 − V 22

Here, Po is the output power, th is the transient duration considered, and V1 and

V2 are the initial and final voltages of the DC-link capacitor respectively during the

transient. Po and th are 1500W and 0.01667s (one line-cycle) for both the converters;

V1 is 570V for the nine-switch converter and 400V for the twelve-switch converter.

Considering V2 = 0.85V1 (i.e. 15% drop of DC-link voltage), Cdc is calculated as 0.554mF

and 1.12mF for the nine-switch converter and the twelve-switch converter respectively.

Note that the twelve-switch converter’s 400V DC-link is realized by only one 1.2mF,

450V capacitor, whereas the nine-switch converter’s 570V DC-link is realized by four

159

4.6. Cost Comparison

ix iy iz


ix (2A/div) iy (2A/div) iz (2A/div)

5μs/div)


Figure 4.28: Resonant tank currents showing interleaved operation of the three half-bridge DC-DC resonant converters.

(b) with single-carrier modulation(a) with three-carrier modulation

ΔVo,p-p = 0.6V0.2V/div

20μs/div

0.2V/div

ΔVo,p-p = 1.6V

20μs/div

Figure 4.29: Comparison of output voltage ripple for proposed three-carrier modulationvs. standard single-carrier modulation.

160


2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0

8 6

8 8

9 0

9 2

9 4

Meas

ured e

fficien

cy (%

)

O u t p u t p o w e r ( W )

M e a s u r e d e f f i c i e n c y E n e r g y S t a r 8 0 P L U S p l a t i n u m e f f .

Figure 4.30: Experimental efficiency plot of the proposed nine-switch converter.

Table 4.5: Comparison of Manufacturing Cost between the Nine-Switch Converter andthe Twelve-Switch Converter

Component Part number Manufacturer Nine-switch converter Twelve-switch BTB converterQuantity (EA) Cost (USD) Cost (USD) Cost (USD)

CAP ALUM 1200UF20% 450V SCREW LNX2W122MSEF Nichicon 0 0 10,000 254,963.60

CAP ALUM 560UF20% 315V SNAP LGY2F561MELC Nichicon 40,000 248,960.00 0 0

OPTOISO 3.75KVGATE DRIVER 6SO ACPL-P343-500E Broadcom

Limited 90,000 136,152.00 120,000 181,536.00

DC/DC CONVERTER15V -5V 2W MGJ2D121505SC Murata Power

Solutions Inc. 90,000 598,500.00 120,000 798,000.00

MOSFETN-CH 900V 11.5A C3M0280090D Cree/Wolfspeed 90,000 292,500.00 120,000 390,000.00

Total 1,276,112.00 1,624,499.60

0.56mF, 315V capacitors connected in two parallel branches of two series connected

capacitors resulting in a resultant capacitance of 0.56mF, 630V.

It is clear from Table 4.5 that, even though the DC-link voltage of nine-switch con-

verter is higher and it requires four capacitors as compared to only one in case of

twelve-switch converter, the nine-switch converter yields about 21.4% cost saving.

4.7 Results with 380V DC Output Voltage

While the 48 V DC output results presented in the previous sections are good enough to

show the practicality of the proposed converter in data center applications, the discussion

remains incomplete without experimentally showing the 380 V DC output voltage as

well. It has been discussed that the future DC based data centers are envisioned to be

operating at a room-level distribution voltage of 380 V DC. A separate 1.5 kW prototype

was built and tested for this purpose using the same printed circuit board (PCB) with

the specifications shown in Table 4.6.

Some of the key features of this 380 V set-up, which are different from the 48 V

161

4.7. Results with 380V DC Output Voltage

Table 4.6: Converter Parameters for Design of the Proposed Single-Stage Nine-SwitchConverter with 380 V Output

Parameter name Symbol ValueRated power Po 1.5 kWInput voltage (line-neutral, rms) vs 120 V, 60 HzOutput voltage Vo 380 VSwitching frequency fs 100 kHzLoad resistance RL 96.267 ΩInput boost inductance Ls 1.5 mHDC-link voltage Vdc 420 VDC-link capacitance Cdc 0.605 mFUpper converter duty ratio mup 0.7Lower converter duty ratio mlo 0.28Transformer turns ratio N 0.4258Resonant inductance Lr 106 µHResonant capacitance Cr 23.87 nFSwitch output capacitance Coss 48 pFDeadtime td 160 nsTransformer magnetizing inductance Lm 0.5 mHOutput filter capacitance Co 0.22 mFd-current controller kp,id + ki,id/s 0.2+2000/sq-current controller kp,iq + ki,iq/s 0.2+2000/sDC-link voltage controller kp,vdc + ki,vdc/s 0.1+5/sOutput voltage controller kp,vo + ki,vo/s 0.1+500/sSampling frequency fsamp 100 kHz

set-up discussed so far are as follows.

1. To show the improvement of THD of the three-phase input currents with increasing

switching frequency, the switching frequency of the 380 V converter is chosen as

100 kHz. It should be noted that the proposed three-carrier modulation is being

used in this case aw well.

2. Instead of Sinusoidal PWM (SPWM), the 380 V converter is modulated with Space

Vector PWM (SVPWM). This has resulted in reduction of the DC-link voltage

from 570 V to 420 V. The details of implementation of SVPWM is presented in

Appendix B.

3. The upper converter duty ratio mup and the lower converter duty ratio mlo have

been chosen as 0.7 and 0.28 respectively. There is no significant reason for this,

other than keeping the DC-link voltage well below 450 V, so that the commonly

available and relatively cheaper 450 V rated electrolytic capacitors could be used

in the DC-link.

Since all the operating waveforms of the 380 V case are similar to the 48 V case, only

the key waveforms are presented here, without repeating all of them. Fig. 4.31 shows

the input and output waveforms of the test set-up. It is observed that the system is

162


va (100V/div) ia (4A/div)

Vo (100V/div)

Io (1A/div)

5ms/div

Figure 4.31: Key input and output waveforms of the 380 V converter at full-load con-dition.

va (100V/div)

ia, b, c (4A/div)

Vo (400V/div)

Io (4A/div) 5ms/div

Figure 4.32: Key input and output waveforms along with three-phase balanced inputcurrents of the 380 V converter at full-load condition.

operating at close-to-unity power factor and the output DC voltage and currents are

stable at 380 V and 3.9 A respectively.

The three-phase input currents along with the phase-a voltage are shown in Fig.

4.32. It is clear that even with the proposed three-carrier modulation scheme the input

currents are well-balanced.

The harmonic profile of the input current at full load is shown in Fig. 4.33. The

THD is noted as 3.27%, which is much better than that of the 48 V case, where the

switching frequency was 60 kHz. This is in perfect compliance with Fig. 4.7, which

claimed that the THD of input current can be controlled within 5% if the switching

frequency is increased.

4.8 Summary

This chapter has proposed a novel single-stage AC-DC isolated converter applicable to

the DC based power architecture of data centers. Not only does it reduce the active

163

4.8. Summary

Freq (Hz)0 100 200 300 400 500 600 700 800 900 1000

Mag

(%

of p

eak

of fu

ndam

enta

l)

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

180 Hzm=0, n=3

900 Hzm=0, n=15360 Hz

m=0, n=6

540 Hzm=0, n=9

720 Hzm=0, n=12

Fundamental: 60 Hz, THD = 3.27%

Figure 4.33: Harmonic spectrum of input current of the 380 V converter at full-loadcondition.

switch count as compared to conventional topologies, it allows higher power density with

reduced output voltage ripple by interleaved operation of the three DC-DC converters

of the proposed system. The main contributions of this chapter are summarized below.

1. Integration of a three-phase active front-end (AFE) boost PFC rectifier and three

phase-interleaved half-bridge DC-DC resonant converters into a single-stage iso-

lated three-phase AC-DC converter using only 9 switches, which would otherwise

require 12 switches. Thus a saving of 25% in device count is achieved, which

translates into a cost saving of roughly 21.4%.

2. Introduction and implementation of a novel three-carrier modulation with saw-

tooth carrier for controlling both the PFC stage and the interleaved DC-DC stage

in a nine-switch converter. Thus the output voltage ripple is reduced by 67%

without any additional hardware for modulation and control. It has been shown

in this paper that the choice of sawtooth carrier wave over triangular carrier wave

leads to reduced switching loss for this converter.

3. Despite being a single-stage topology, the PFC stage of the converter operates in

CCM, and thus eliminates all the issues related to DCM.

With the currently available high-voltage and high-current rated SiC MOSFET devices

164


that allow operation under high frequency and high blocking voltage, the proposed three-

carrier modulation scheme also easily meets the harmonics requirement as imposed by

IEC 61000-3-2 standard for Class A type loads. The constant frequency APWM oper-

ation of the half-bridge DC-DC resonant converters with magnetizing current assisted

ZVS, apart from causing minimal loss, simplifies the design as compared to frequency-

controlled resonant converters.

165

Chapter 5

Effect of Three-Carrier

Modulation in Input Current

Harmonics

The three-carrier modulation proposed in Chapter 4, although reduces the size of output

filter, comes at the cost of deteriorated THD performance for the proposed nine-switch

single-stage converter. At the surface level, it is evident that increasing the switching

frequency can limit the overall THD of the input current [120] (refer to Fig. 4.7). How-

ever, the switching frequency can not be increased beyond a certain limit because of

the lack of complete range of soft-switching of the nine-switch converter. A mathemat-

ical analysis is therefore required to investigate the effect of switching frequency in this

particular three-carrier modulation technique. A detailed account of THD analysis for

PWM AC-DC converters has been presented in [120]. Following this, a similar analyt-

ical model is constructed here and studied for the proposed three-carrier modulation

technique.

5.1 Introduction

Reference [120] has given detailed analytical models for all the following three PWM

techniques that essentially encompass all the possibilities of fixed-frequency modulation

systems, including Space Vector Modulation.

1. Naturally Sampled PWM: In this case the switching occurs at the intersection of

a low-frequency target reference waveform and a high-frequency carrier. This can

166

5. Effect of Three-Carrier Modulation in Input Current Harmonics

be sub divided into two cases:

(a) Trailing-edge or Single-edge naturally sampled PWM: This uses a sawtooth

carrier waveform to compare against the reference waveform.

(b) Double-edge naturally sampled PWM: The more common form of naturally

sampled PWM uses a triangular carrier instead of a sawtooth carrier to com-

pare against the reference waveform. With this type of carrier, both sides of

the switched output pulse from the phase leg are modulated, which consid-

erably improves the harmonic performance of the pulse train.

2. Regular Sampled PWM: In this case the switching occurs at the intersection be-

tween a regularly sampled reference waveform and a high-frequency carrier. This

can be sub divided into three cases:

(a) Trailing-edge or Single-edge regular sampled PWM: This uses a sawtooth

carrier to compare against the regularly sampled reference waveform. The

sampling occurs as the carrier waveform falls at the end of the ramping period.

(b) Symmetrical regular sampled PWM: This uses a triangular carrier to com-

pare against the regularly sampled reference waveform. Here, the sampled

reference is taken at either the positive or the negative peak of the carrier

and held constant for the entire carrier interval.

(c) Asymmetrical regular sampled PWM: This uses a triangular carrier to com-

pare against the regularly sampled reference waveform. Here, the reference

is re-sampled every half carrier interval at both the positive and the negative

carrier peak.

3. Direct PWM: In this case, the switching is determined such that the integrated

area of the target reference waveform over one carrier interval is the same as the

integrated area of the converter switched output (the average volt-second over

a switching period). The method is not usually practical to implement since it

requires integration over the carrier interval.

Even though [120] has not discussed multi-carrier modulation explicitly, the theory

presented therein can be extended for the proposed three-carrier modulation in all the

above-mentioned techniques. However, the discussion hereafter is confined only to the

following most popular techniques.

1. Double-edge naturally sampled PWM

167

5.2. For Double-edge Naturally Sampled PWM

Cdc

+

Vdc

-

n

p

vab

Sa Sb Sc

Sa' Sb' Sc’

ab

c+

Vdc

-

z

vbc

vca

R-L Load

Figure 5.1: Simulated three-phase inverter with M = 1, fc/f0 = 1050/50 = 21, Vdc =50V and R = 1Ω. Source: [120].

2. Single-edge regular sampled PWM

3. Symmetrical regular sampled PWM

To compare the three-carrier modulation vs. the single-carrier modulation, the system

as shown in Fig. 5.1 was simulated with the parameters as mentioned. Here, M is the

modulation index, fc is the carrier frequency and f0 is the fundamental frequency of the

sinusoidal reference waveform.

5.2 For Double-edge Naturally Sampled PWM

The complete harmonic solution for double-edge naturally sampled modulation of a half-

bridge phase leg can be found from (5.1). The time varying switched phase leg voltage

with respect to the midpoint of DC bus vaz(t) can be expressed in terms of its harmonic

components as:

vaz(t) = Vdc +VdcM cos (ω0t+ θ0) + 4Vdcπ

∞∑m=1

∞∑n=−∞

1mJn

(mπ

2M)× sin

([m+ n]π2

)× cos (m[ωct+ θc] + n[ω0t+ θ0]) (5.1)

Here, ωc = 2πfc and ωo = 2πfo are the angular carrier frequency and angular

reference frequency respectively, and θc and θo are their respective phase angles. The

indices m and n are integers representing multiples of carrier frequency and reference

frequency respectively, they correspond to particular harmonics in the FFT spectrum.

Jn(ξ) is the standard Bessel function [126]of order n and argument ξ, as shown in Fig.

5.2.

The line-to-line voltage in this case can be derived from (5.1 with vab = vaz − vbz.

168


ζ

0 2 4 6 8 10-0.5

0

0.5

1

J0

J1

J2 J

3 J4 J

5 J6 J

7

Figure 5.2: Bessel functions Jn(ξ) for n = 0, 1, ..., 7.

Single Carrier For single carrier operation, we set θc = 0 and θ0 = 0,−2π/3, 2π/3,

and so we have:

vab(t) =√

3VdcM cos(ω0t+ π

6

)+ 8Vdc

π

∞∑m=1

∞∑n=−∞

1mJn

(mπ

2M)× sin

([m+ n]π2

)× sin

(nπ

3

)× cos

(mωct+ n[ω0t−

π

3 ] + π

2

)(5.2)

Overall, the following phase leg harmonic components will not appear in the line-to-

line output voltage:

• Carrier harmonics, since they are the same for all phase legs.

• Side-band harmonics with even combinations of [m ± n] . More precisely, these

harmonics are eliminated within each phase leg by the sin([m+ n]π2 ) terms.

• Triplen side-band harmonics, where n is a multiple of 3. The phase angles of these

harmonics rotate by multiples of 2π for all phase legs and hence are the same for

all phase legs.

Fig. 5.3 presents the line-to-line voltage harmonic spectrum for double-edge naturally

sampled PWM with a single-carrier modulation, which clearly verifies all the aforemen-

tioned claims.

169

5.2. For Double-edge Naturally Sampled PWM

Figure 5.3: Harmonics of line-to-line voltage for triangular double-edge naturally sam-pled PWM with a single-carrier modulation.

Three Carrier For three-carrier operation, we set θc = 0− 2π/3, 2π/3 and also θ0 =

0,−2π/3, 2π/3, and so we have:

vab(t) =√

3VdcM cos(ω0t+ π

6

)+ 8Vdc

π

∞∑m=1

∞∑n=−∞

1mJn

(mπ

2M)× sin

([m+ n]π2

)× sin

([m+ n]π3

)× cos

(mωct+ nω0t− [m+ n]π3 ] + π

2

)(5.3)

In a similar way, it can be inferred that the following phase leg harmonic components

will-not appear in the line-to-line output voltage:

• Side-band harmonics with even combinations of [m ± n] . More precisely, these

harmonics are eliminated within each phase leg by the sin([m+ n]π2 ) terms.

• Side-band harmonics, where [m + n] is a multiple of 3. This is the only differ-

ence with single-carrier operation. The triplen side-band harmonics will not be

completely removed here.

Note that carrier harmonics are not the same for all phase legs in case of three-carrier

modulation. Hence they may not always be canceled. Only those carrier harmonics

where [m + n], and therefore m (since n = 0 for carrier harmonics), is a multiple of 2

or 3 will be canceled. Thus the 1st, 5th, 7th, 11th... carrier harmonics will be present

in this case. This is shown clearly in Fig. 5.4. It is worth noting that the THD in

Fig. 5.4 has increased for three-carrier modulation as compared to that of single-carrier

modulation in Fig. 5.3.

170


Figure 5.4: Harmonics of line-to-line voltage for triangular double-edge naturally sam-pled PWM with proposed three-carrier modulation.

5.3 For Regular Sampling

One major limitation with naturally sampled PWM is the difficulty of its implementa-

tion in a digital modulation system, common nowadays. Therefore, from the practical

implementation point, the two most popular cases are - Sawtooth Regular Sampling and

Triangular Symmetrical Regular Sampling. These two cases are discussed here with a

comparison of single-carrier vs. three-carrier modulation.

5.3.1 Single-edge Regular Sampled PWM

For one leg:

vaz(t) = 2Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωcπM)

[sin(nπ2 ) cos(n[ω0t+ θ0])− cos(nπ2 ) sin(n[ω0t+ θ0])

]+2Vdc

π

∞∑m=1

1m

[cos(mπ)−J0(mπM)] sin(m[ωct+θc])+2Vdcπ

∞∑m=1

∞∑n=−∞,n6=0

Jn([m+ nω0ωc

]πM)m+ nω0

ωc

×[sin(nπ2 ) cos(m[ωct+ θc] + n[ω0t+ θ0])− cos(nπ2 ) sin(m[ωct+ θc] + n[ω0t+ θ0])

](5.4)

The line-to-line voltage in this case can be derived from (5.4) with vab = vaz − vbz.

171

5.3. For Regular Sampling

Figure 5.5: Harmonics of line-to-line voltage for sawtooth single-edge regular sampledPWM with a single-carrier modulation.


and so we have

vab(t) = 4Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωcπM) sin(nπ3 ) sin(nω0t− 5nπ6 −

π

2 )

+ 4Vdcπ

∞∑m=1

∞∑n=−∞

Jn([m+ nω0ωc

]πM)m+ nω0

ωc

sin(nπ3 ) sin(mωct+ nω0t− 5nπ6 −π

2 ) (5.5)

So, the absentees are:

• All the carrier harmonics, because n = 0 for them.

• The side-band harmonics for n = 3x, x = 1, 2, 3...

This is shown clearly in Fig. 5.5.


0,−2π/3, 2π/3, and so we have

vab(t) = 4Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωcπM) sin(nπ3 ) sin(nω0t− 5nπ6 −

π

2 )

+ 4Vdcπ

∞∑m=1

1m

[cos(mπ)− J0(mπM)] sin(mπ

3 ) cos(mωct−mπ

3 )

+4Vdcπ

∞∑m=1

∞∑n=−∞,n6=0

Jn([m+ nω0ωc

]πM)m+ nω0

ωc

sin([m+n]π3 ) sin(mωct+nω0t−[m+n]π3−[n+1]π2 )

(5.6)

The first term corresponds to m = 0, i.e. all the harmonics below the switching

172


Figure 5.6: Harmonics of line-to-line voltage for sawtooth single-edge regular sampledPWM with the proposed three-carrier modulation.

frequency; the second term corresponds to n = 0, i.e. all the multiples of switching

frequency; and the third term corresponds to all the side-band harmonics (m 6= 0, n 6= 0).


• The carrier harmonics for m = 3x, x = 1, 2, 3...

• The side-band harmonics form + n = 3x, along with m = 3x and n = 3x, x =

1, 2, 3...

However, as shown in Fig. 5.6 the cancellation of the aforementioned harmonics are not

complete. The reason is that the chosen fc/fo = 1050/50 = 21 is quite low, therefore

even if a certain side-band harmonic is absent for a particular m, it may be present as a

side-band due to the neighboring m. In practical cases, as in our proposed nine-switch

converter, the ratio fc/fo is much higher (1000 or more), and this effect is reduced.

5.3.2 Symmetrical Regular Sampled PWM

Here, the sampled reference is taken at either the positive or the negative peak of the

triangular carrier and held constant for the entire carrier interval. For one leg:

vaz(t) = 4Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωc

π

2M) sin(n[1 + ω0

ωc]π2 ) cos(n[ω0t+ θ0])

+4Vdcπ

∞∑m=1

1mJ0(mπ

2M) sin(mπ

2 ) cos(m[ωct+θc])+4Vdcπ

∞∑m=1

∞∑n=−∞,n6=0

Jn([m+ nω0ωc

]π2M)m+ nω0

ωc

× sin([m+ nω0

ωc+ n]π2 ) cos(m[ωct+ θc] + n[ω0t+ θ0]) (5.7)

173

5.3. For Regular Sampling

Figure 5.7: Harmonics of line-to-line voltage for triangular symmetrical regular sampledPWM with a single-carrier modulation.

The line-to-line voltage in this case can be derived from (5.7) with vab = vaz − vbz.


and so we have

vab(t) = 8Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωc

π

2M) sin(n[1 + ω0

ωc]π2 ) sin(nπ3 ) cos(nω0t− n

π

3 + π

2 )

+8Vdcπ

∞∑m=1

∞∑n=−∞

Jn([m+ nω0ωc

]π2M)m+ nω0

ωc

sin([m+nω0

ωc+n]π2 ) sin(nπ3 ) cos(mωct+nω0t−n

π

3 +π

2 )

(5.8)


• All the carrier harmonics, because n = 0 for them.

• Side-band harmonics for n = 3x, x = 1, 2, 3...

Fig. 5.7 shows the harmonics spectrum in this case, which very similar to that of saw-

tooth single-carrier regular sampled PWM as shown in Fig. 5.5. However, as expected,

the THD is lesser in this case than that of sawtooth modulation.

174


Figure 5.8: Harmonics of line-to-line voltage for triangular symmetrical regular sampledPWM with the proposed three-carrier modulation.


0,−2π/3, 2π/3, and so we have

vab(t) = 8Vdcπ

∞∑n=1

1(nω0

ωc)Jn(nω0

ωc

π

2M) sin(n[1 + ω0

ωc]π2 ) sin(nπ3 ) cos(nω0t− n

π

3 + π

2 )

+8Vdcπ

∞∑m=1

1mJ0(mπ

2M) sin(mπ

2 ) sin(mπ

3 ) cos(mωct−mπ

3 +π

2 )+8Vdcπ

∞∑m=1

∞∑n=−∞,n6=0

Jn([m+ nω0ωc

]π2M)m+ nω0

ωc

× sin([m+ nω0

ωc+ n]π2 ) sin([m+ n]π3 ) cos(mωct+ nω0t− [m+ n]π3 + π

2 ) (5.9)


• The carrier harmonics for m = 3x and m = 3x, x = 1, 2, 3...

• The side-band harmonics form + n = 3x, along with m = 3x and n = 3x, x =

1, 2, 3...

This is shown in Fig. 5.8. The cancellations are more prominent in this case than that

of sawtooth three-carrier regular sampled PWM as shown in Fig. 5.6. Also, as expected,

the THD is highr in this case than that of single-carrier modulation as shown in Fig.

5.7. Interestingly though, the THD in Fig. 5.8 triangular three-carrier regular sampled

PWM is almost same as that of sawtooth three-carrier regular sampled PWM in Fig.

5.6. Therefore, the choice of carrier between sawtooth and triangular did not make much

difference in this case of three-carrier regular sample modulation.

175

5.4. Validation of the Three-Carrier Modulation in the Proposed Nine-SwitchConverter

18

0 H

z, m

=0, n=

3

36

0 H

z, m

=0, n=

6

54

0 H

z, m

=0, n=

9

72

0 H

z, m

=0, n=

12


3-carrier PWM

Single-carrier PWM

(a) Frequency up to 1200 Hz.


99.82 kHz, m=1, n=3

3-carrier PWM

Single-carrier PWM

(b) Frequencies centered around first carrier harmonic at 100 kHz.

Figure 5.9: FFT of the input current obtained from the simulation of the proposednine-switch converter at full load.

5.4 Validation of the Three-Carrier Modulation in

the Proposed Nine-Switch Converter

To corroborate the theory developed so far, the FFT spectra of the input line current

from simulation as well as experiment of the proposed single-stage nine-switch converter

with three-carrier modulation is presented here. The parameters for the simulation

and experiment are same as presented in Table 4.6. It should be noted that in both

simulation and experiment, the carrier waveform chosen was sawtooth.

Fig. 5.9 shows the FFT of the input current obtained from the simulation of the

proposed nine-switch converter at full load. It is found that, while the side-band har-

monics for n = 3x (x = 1, 2, 3...) are almost canceled in case of single-carrier PWM,

this cancellation is not complete in case of three-carrier PWM for the reason explained

before.

Fig. 5.10 shows the FFT of the input current obtained from the experimental set-up

176


of the proposed nine-switch converter at full load. The experiment was done only for

three-carrier modulation. Note that the carrier harmonic at 300 kHz is absent, since

m = 3 in this case. Also, the THD obtained from the experiment is slightly higher than

that from the simulation.

5.5 Summary

Based on the above discussion, the following conclusions can be drawn regarding the

proposed three-carrier modulation.

1. The basic operation of a three-phase pulse-width-modulated inverter/rectifier is

not affected with three-carrier modulation.

2. In general, THD in case of three-carrier modulation is higher than the THD in

case of single-carrier modulation.

3. In case of three-carrier regular sample modulation, the choice of carrier between

sawtooth and triangular wave does not make much difference in terms of THD

performance.

Therefore, this chapter corroborates the claim of Chapter 4 that the use of three-carrier

modulation for the proposed nine-switch single-stage AC-DC converter does not affect

the PFC operation; rather, it facilitates the interleaved operation of the output rectifiers,

which is unique to this single-stage converter. This completes the discussion on the AC-

DC and DC-DC converter solutions proposed in this thesis for the DC powered data

centers.

177

5.5. Summary

Freq (Hz)0 100 200 300 400 500 600 700 800 900 1000

Mag

(%

of p

eak

of fu

ndam

enta

l)

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

180 Hzm=0, n=3

900 Hzm=0, n=15360 Hz

m=0, n=6

540 Hzm=0, n=9

720 Hzm=0, n=12


(a) Frequency up to 1000 Hz.

Freq (Hz) ×105

0 0.5 1 1.5 2 2.5 3 3.5

Mag

(%

of p

eak

of fu

ndam

enta

l)

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

100 kHzm=1, n=0

200 kHzm=2, n=0

300 kHzm=3, n=0


(b) Frequency up to 350 kHz.

Figure 5.10: FFT of the input current obtained from the experimental set-up of theproposed nine-switch converter at full load.

178

Chapter 6

Conclusions and Future Works

This chapter concludes the thesis. It briefly restates the motivation of the thesis work,

the identified problem areas and the various proposed solutions in each problem area.

Finally, it shows the direction of future research in this regard.

6.1 Summary of Work Done

This thesis has proposed novel AC-DC and DC-DC power electronic converters to im-

prove the efficiency and power density of the power supply architectures of DC based

data centers. Chapter 1 starts with the importance of reduction of heat generation,

especially from the power systems inside the data center, by improving the efficiency of

the power converters used. Comparative review of AC powered and DC powered data

center shows that migration towards a DC based power architecture is promising in this

regard, mainly because of reduction of number of conversion stages, and the absence

of phase balancing and harmonic issues of the AC systems. The two DC voltage levels

found to be suitable for power distribution inside a data center are 48 V and 380 V. A

literature review is then carried out for the three-phase PFC rectifiers and the isolated

DC-DC converters – the two stages commonly used for converting the utility three phase

AC to regulated and isolated DC in a two stage conversion scheme. It is identified that

integration of the functions of the aforementioned two stages in a single-stage power

converter can be a smarter choice for DC based data centers because of the potential

reduction of the cost and size associated with the two-stage AC-DC power conversion.

However, the review of the existing single-stage converters shows that obtaining a 48

V or 380 V isolated DC from three-phase universal AC supply in a single stage always

comes at the cost of inefficient DCM of the input currents, which poses many design

179

6.1. Summary of Work Done

challenges. To overcome these challenges, this work proposes a single stage AC-DC

converter for data center applications, which is based on a nine-switch bridge topology

and features CCM of the input currents. It also goes on to propose a novel design

methodology of the APWM HB DC-DC resonant converter to improve the efficiency of

the PUPS or the PoL converters inside the ICT equipment of data centers.

This work also brings out the significance of the use of WBG devices, especially

the SiC MOSFETs, in realizing the proposed nine-switch single-stage converter. The

constraints in the modulation of the nine-switch converter, as discussed in Chapter 2,

result into higher than usual DC-link voltage (more than 750 V for universal input

voltage). Moreover, the interleaved modulation strategy adopted in this work requires

high switching frequency operation to limit the input current THD. Such high voltage

and high frequency operation has been feasible only with the recently commercialized

SiC MOSFETs rated for 900 V and above.

Chapter 2 gives an overall review of the nine-switch converter and its basic operation,

and discusses the issues with the switching of three switches in a leg. The nine-switch

converter is a multi-port converter having two three-phase terminals and a DC link,

similar to a twelve-switch BTB converter, but with 25% reduction of active switch count.

However, the reduction from twelve-switch to nine-switch may not always be an efficient

choice considering losses in the switches. Only the load-source combination for the AC-

AC Common Frequency (AC-AC CF) mode and the source-source combination for the

AC-DC Different Frequency (AC-DC DF) mode have been reported, so far, to yield

relatively lower loss for the nine-switch converter. Chapter 2 shows that the nine-switch

converter can have relatively lower loss even with a load-source combination, instead

of only source-source combination in its AC-DC DF mode – when the upper terminal

is connected to a DC load and the lower terminal is connected to an AC source. This

configuration also meets all the requirements of a non-isolated AC-DC power supply for

data center loads. Mathematical proof is presented with derivation of the particular

operating parameters for which the nine-switch converter will have comparatively lower

losses. The analysis is validated with simulation and experimental results from a 1 kW

non-isolated power converter prototype for data center loads. Results are presented

for different cases of load sharing to indicate the most efficient load sharing conditions.

Finally, the benchmark of the application criteria of the nine-switch converter for having

lower conduction loss than the BTB converter is updated in Chapter 2.

Chapter 3 proposes a novel design procedure for the standard APWM HB resonant

topology, that uses the magnetizing current and eliminates the need of extra compo-

180

6. Conclusions and Future Works

nents (like LC network) that are otherwise used for ensuring ZVS over wide range of

line and load variation. This design procedure has been used for the PoL converters

inside the ICT equipment, as well as for the lower converters of the proposed nine-

switch single-stage AC-DC converter in Chapter 4. The converter with the proposed

design methodology operates at the resonant frequency of the tank and features load-

independent ZVS for a wide range of input voltage variation with minimal magnetizing

current. Empirical formulae are derived to design the resonant network and the magne-

tizing inductance of the high-frequency transformer systematically in a flow-chart based

manner. The proposed design is validated using simulations as well as experiments and

is compared with a reference APWM HB series resonant converter design that uses an

auxiliary LC circuit for ZVS. Two separate experimental prototypes of the two convert-

ers rated for 30W, 48V/5V with a switching frequency of 500 kHz were built and tested

in the laboratory. It was found that the converter with the proposed design method-

ology, apart from having lower component-count, is about 3% more efficient than the

reference topology at the rated power.

Chapter 4 introduces the proposed nine-switch single-stage three-phase AC-DC con-

verter for data center applications. The proposed converter is based on a nine-switch

bridge topology, which integrates a three-phase active front-end boost PFC rectifier and

three phase-interleaved half-bridge DC-DC resonant converters in a single stage. In

a conventional two-stage configuration this integration requires twelve switches, which

implies that the proposed converter yields a 25% saving in device count. A novel mod-

ulation scheme using three separate 120 phase shifted high frequency carriers for the

three legs of the proposed converter is developed to drive the switches. It is shown that

such modulation scheme leads to interleaved operation of the three DC-DC resonant

converters integrated within the proposed topology resulting in 67% lower output DC

voltage ripple than the conventional two-stage configuration. Then the design procedure

of the converter is presented including the design of the controllers. Justification with

loss comparison is provided for the choice of SiC MOSFET as the enabling technology

for the converter along with the identification of soft-switching areas of the switches in a

line-cycle, and a theoretical loss analysis of the converter. Chapter 4 also shows that the

choice of sawtooth carrier wave over triangular carrier wave leads to reduced switching

loss for this converter. Moreover, despite being a single-stage topology, the PFC stage

of the converter operates in CCM, and thus eliminates all the issues related to DCM.

Proposed converter with the modulation scheme is validated with 1.5 kW laboratory

prototypes and results are presented for both 48 V DC output and 380 V DC output,

181

6.2. Prospective Research Work

which meet the Energy Star 80PLUS platinum efficiency standard of data centers. A

comparison of cost of manufacturing of 10,000 units of the proposed nine-switch single-

stage converter and its equivalent two-stage twelve-switch BTB converter shows 21.4%

savings in case of the proposed nine-switch single-stage AC-DC converter.

Chapter 5 discusses the impact of the proposed three-carrier modulation scheme

on the harmonics of the three-phase input currents. The mathematical expressions for

the complete harmonic solutions of the pole voltages with three-carrier modulation for

different scenarios of natural sampling and regular sampling are developed, and the THD

performance is compared with the standard single-carrier modulation scheme for each

case. Finally, with the use of the proposed three-carrier modulation in the proposed

nine-switch single-stage converter, it is shown that the basic operation of a three-phase

pulse-width-modulated inverter/rectifier is not affected by the three-carrier modulation.

6.2 Prospective Research Work

This thesis has demonstrated the performances of the proposed AC-DC and DC-DC

converters experimentally with laboratory prototypes. However, given the stringent

specifications of data center power supplies, it requires further research before the pro-

posed power converters could be applied in practical data centers. It is needed to study

their behaviour in different scenarios and make necessary modifications in their structure

and control to maximize their potential. The prospective research work can be focused

broadly on the following areas.

6.2.1 Benchmarking of Nine-Switch Converter against BTB Con-

verter

Although a cost comparison has been performed in Chapter 4 between the nine-switch

converter and the twelve-switch BTB converter, cost can not be the sole metric for

benchmarking the performance of the proposed nine-switch single-stage converter. Es-

pecially, when it comes to ease of control and reliability, the BTB converter is clearly

the preferred choice so far. Therefore the exact BTB equivalent of the proposed con-

verter as shown in Fig. 6.1(b) needs to be built and tested with the same input-output

conditions. Moreover, both of them should be designed for universal three-phase AC

input (210V AC ~ 480V AC), which is beneficial from product development point.

182


SA SB SC

SAX SBY SCZ

SZSYSX

Cdc

Ls

Lr

vS

+

Vdc

-

AB

C

ZY

X

N

P

CoRL

+

Vo

-

Cr

(a) Proposed nine-switch converter.

SA SB SC

SA’ SB’ SC’

Cdc

LsvS

+

Vdc

-

AB

C

N

P

Lr

Co RL

+

Vo

-

Cr

SX’ SY’ SZ’

SX SY SZ

XY

Z

(b) Equivalent twelve-switch BTB converter.

Figure 6.1: Proposed nine-switch single-stage converter and its equivalent twelve-switchback-to-back (BTB) converter.

6.2.2 Bi-directional Battery Charger

The proposed converter shown in Fig. 6.1(a) is essentially unidirectional. In the author’s

opinion this converter also has the potential of bi-directional power flow when the diode

rectifiers on the secondary side of the transformers are replaced with active half-bridge or

full-bridge converters. Of course, the modulation strategy has to be modified to facilitate

a bi-directional resonant operation of the lower converters. Such a converter can be used

as a bi-directional battery charger in electric vehicles (EV), and can support vehicle-to-

grid (V2G) operation with peak shaving feature. Since the converter has higher than

usual DC-link voltage as compared to a BTB converter, high amount of 0.5CV 2 energy

can be stored in relatively lesser volume of capacitance by the use of ultra capacitors

in the DC-link. Ultra capacitors are usually good in supplying high impulse currents.

Therefore this converter can better support the grid voltage fluctuations that require

a lot of impulse energy, thereby improving the lifetime of the Lithium-ion battery on

board.

6.2.3 Study on Phase-Shedding

An important feature for high power converter (especially for three-phase converter) is

phase shedding to improve the low-load efficiency of the converter. For example, for

183

6.2. Prospective Research Work

battery charging applications, one really do not need to run the converter in full power

for the whole charge cycle, so the converter should be able to operate even in the absence

of one or more phases. Suitable control strategy has to be developed to enable phase

shedding operation in the proposed converter. A crude idea is to control the current of

each phase individually, instead of going for d− q control.

6.2.4 Reliability Study of the Converters

The three switches in a leg of the proposed nine-switch converter experience different

stresses in terms of conduction loss and switching loss. Same is true for the two switches

of the proposed APWM HB PoL converter. This of course translates into poor reliability

of the converters. While this unequal switching stress is almost unavoidable in any nine-

switch converter as well as APWM converter, a careful study can lead to the findings

of acceptable limits of unequal stresses among the switches which can give reasonable

reliability of the converters and the whole system.

6.2.5 Improvement of DC Bus Utilization

It is a known problem for the nine-switch topology that the DC bus is not properly

utilized because of the lower modulation indices for the two parts of the converter.

In some literature it is found that the DC bus utilization is improved by 15% by the

use of the Space Vector Modulation Technique [127] or the Third-Harmonic Injection

Technique [83, 84]. The same has also been validated in Chapter 4 of this thesis using

SVM. However, the DC-link voltage is still higher than that of a BTB converter, simply

because the modulation indices are lesser than 1 in case of nine-switch converter.

A single-phase counterpart of the nine-switch converter, the six-switch converter, is

also being studied by many researchers [128, 129], mainly for DC bus ripple compensa-

tion. In [128], it has been shown that with a special Space Vector Modulation technique,

the DC bus utilization can be improved further in certain cases. Such a technique has

not been extended for the nine-switch topology so far. Effort can be put to develop the

said technique and also investigate the potential of implementing it for the particular

area of application that this work is based on.

6.2.6 Hold Up Time (HUT) Analysis

During input utility line drop-outs, the data center power system should be able to feed

the load at the rated maximum power for a certain minimum amount of time (typically

one line cycle or 20 ms) which is known as Hold Up Time (HUT) of the data center power

184


system. This feature is extremely important for modern data centers having increasingly

complex and faster routers with extended reset times and consequent backing of data

during power drop out.

The integration of a resonant topology in the proposed nine-switch converter not only

decreases the switching loss of the converter, but also gives the possibility of an improved

HUT operation. The advantage of having an elevated DC-link voltage as compared to

a BTB converter is that the DC-link can store high amount of 0.5CV 2 energy, which

is necessary for HUT operation. The frequency controlled series and parallel resonant

DC-DC converters are usually not preferred for HUT operations because of their large

circulating current. The proposed converter being duty controlled and operating at the

resonant frequency, has very less circulating current, which can make this a very good

candidate for extended HUT operations. However, this has to be validated properly

with elaborate simulations and experiments.

185

Appendix A

High Step-up APWM

Converter for Integration of

PV Module to Data Center

A.1 Introduction

It was claimed in Chapter 3 that the novel design methodology presented therein for

the APWM HB series resonant converter with magnetizing current assisted ZVS is

universally applicable for any combination of input voltage, output voltage, rated power

and operating frequency of the converter. To validate the claim, we developed a separate

prototype of the APWM HB series resonant converter for step-up voltage conversion.

This converter is aimed at interfacing Photo Voltaic (PV) modules to the 380 V DC

bus of the data centers. The design procedure of this converter is exactly the same as

that of the PoL converter presented in Chapter 3. Therefore, without repeating the

design section, only the performance of the converter is studied in this appendix by

presentation of simulation and experimental results.

Conventional PV systems are powered by a centralized PV array, which comprises

tens of thousands of PV cells. The system is based on the assumption that all solar

cells are identical and perform the same. However, significant power loss has been

reported for centralized PV systems due to unbalanced generation among PV panels.

The mismatch commonly results from various and unpredictable resources, which is

difficult to handle [130]. Thus, the concept of distributed maximum power point tracking

(DMPPT) has attracted significant research attention to address the above issues. The

186

A. High Step-up APWM Converter for Integration of PV Module to Data Center

distributed structure of maximum power point trackers have widely been accepted in

commercial PV inverter products at the PV string and module level. Fine granularity

is also proposed at the PV module and sub-module level, where the power electronics

and MPPT algorithm can be applied to isolate individual non-performing generators

and maximize solar energy harvest [131].

Commercial PV modules are commonly constructed by 60 or 72 solar cells for power

systems. The nominal voltage ranges from 28V to 45V, which is significantly lower than

the DC distribution voltage of 380 V in data centers. High conversion ratio is demanded

to achieve the fine granularity for the highest solar energy harvest [132]. The research

challenge becomes the high voltage conversion ratio, simple topology, low-cost, along

with, high conversion efficiency.

For PV applications, unidirectional DC-DC converters are required, which are com-

monly classified as non-isolated and isolated topologies, [133, 134]. To reach a high

conversion ratio of voltage, non-isolated topologies usually utilize coupled inductors or

transformers in the non-isolated form, [135–137]. However, galvanic isolation is impor-

tant for system grounding to ensure safety, robustness, and reliability. Many topologies

have been developed using high frequency transformers to achieve high voltage gain and

high conversion efficiency. Conventional topologies include forward, push-pull, flyback,

half-bridge, and full-bridge converters.

The asymmetrical pulse-width-modulated half-bridge (APWM-HB) series resonant

topology has shown superiority over the conventional topologies since it utilizes a simple

isolated topology [53, 58, 103]. It features low component count while allowing zero

voltage switching (ZVS) of the primary-side switches for all load conditions at a fixed

switching frequency. Other advantages include low voltage stress on the switches, zero-

current switching of the secondary-side diodes, and simple capacitive output filter [53,

58,59,103,105]. These merits make APWM-HB an attractive candidate for high step-up

conversion of voltage to interface PV modules with the DC bus of the data centers.

This appendix presents the design and utilization of the APWM-HB series resonant

converter that can excel the efficiency profile of the existing topologies. The objective is

to achieve the maximum voltage gain and minimum circulating current in the resonant

tank without affecting the ZVS feature of the switches. The performance of the proposed

converter is also evaluated with an experimental prototype of 240W to demonstrate its

efficacy and relevance in the proposed application.

187

A.2. Converter Details

Figure A.1: APWM half-bridge series-resonant converter interfacing the PV module tothe 380V bus of the DC data center.

Table A.1: Specifications for the Converter Interfacing PV Module

Parameter Name Symbol ValueInput voltage Vi 30− 40 VOutput voltage Vo 380 VOutput power Po 240 WSwitching frequency fs 100 kHz

A.2 Converter Details

The PV system is shown in Fig. A.1, which includes an APWM-HB resonant converter

interfacing the PV module to the 380 V bus of the DC data center. The converter

specifications are shown in Table A.1 and the circuit parameters in Table A.2. The

parameter ω is the relative operating frequency referred to the resonant frequency, ωr.

The charge-equivalent output capacitance (Coss) of the MOSFETs are calculated based

on [59,138]. As mentioned before, the circuit parameters for this converter are calculated

using the same design equations presented in Chapter 3, and therefore are not repeated

here.

Table A.2: Design Values for the Converter Interfacing PV Module

Parameter Name Symbol ValueRelative operating freq. ω 1.0Full load quality factor Qo 1.57Maximum duty ratio D 0.45Deadtime td 96 nsSwitch output capacitance Coss 1.0 nFTransformer turns-ratio N 0.038Resonant inductance Lr 1.85 µHResonant capacitance Cr 1.367 µFMagnetizing inductance Lm 4 µHOutput filter capacitance Co 0.12 mF

188


Table A.3: Key Components used for the Prototype of the Converter Interfacing PVModule

Component Name Symbol Part No. QtyMOSFET S1, S2 EPC2102 2Driver U2 LM5113 1Diode D1, D2 SCS206AGC 2Resonant capacitor Cr R82IC3220AA60J 6

A.3 Results and Discussions

A.3.1 Simulation

The software, PLECS is used for concept proof and parameterization. It is important to

note that the value of magnetizing inductance used in Table A.2 is much lower than the

calculated value according to (3.25). This is because the ringing between the transformer

secondary winding leakage inductance and the output diode capacitance in a practical

converter is not considered in (3.25). The effect of these two parasitic elements is

demonstrated in Fig. A.2.

Fig. A.2(a) shows the ideal case where the calculated value of Lm = 34µH works

perfectly and S1 is able to achieve valley switching (ZVS). On the other hand, a leak-

age inductance of 38 µH (measured value) for the secondary winding and a junction-

capacitance of 30 pF (extrapolated from the diode datasheet SCS206AGC) for each

output diode is considered in the second case. Figs. A.2(b) and (c) demonstrate that a

magnetizing inductance of 6.7 µH or less is required to attain ZVS of S1 for this practical

case. For the prototyped converter, Lm is fixed at 4 µH to facilitate ZVS of S1 at the

input voltage of 30 V.

A.3.2 Experiment

Following the converter parameters in Table A.1, a prototype was built and tested, of

which the photo is illustrated in Fig. A.3. Key components used in the prototype are

given in Table A.3 and Table A.4. To achieve the desired inductances and avoid core

saturation, appropriate air-gaps were provided in the inductors and transformers. The

value of resonant inductance provided in Table A.2 is the sum of the transformer leakage

inductance and the external series inductance added. The peak operating flux density

for both the magnetic components is chosen about 0.1 Tesla to keep the core losses below

100 mW/cm3.

The converter is expected to operate at the resonant frequency of the tank to avoid

any circulating power within the system. The resonant frequency is determined by

189

A.3. Results and Discussions

vpri

iLr

vg1

vds1

Valley switching

(a) Ideal case with no parasitic elements. Calculated value of Lm = 34µH worksperfectly and S1 is able to achieve valley switching (ZVS).

vpri

iLr

vg1

vds1

Hard switching

(b) With secondary leakage inductance of 38 µH and diode capacitance of 30 pF.Calculated value of Lm = 34µH does not work and S1 is hard-switched.

vpri

iLr

vg1

vds1

Valley switching

(c) With secondary leakage inductance of 38 µH and diode capacitance of 30 pF. AnLm of 6.7 µH had to be chosen to attain ZVS of S1.

Figure A.2: Demonstration of the effect of ringing between the transformer secondaryleakage inductance and the diode capacitance, on the ZVS of primary-side switches.

190


TransformerResonant

inductor

Input

terminal

Output

terminal

Output

capacitor

Output

diodes

EPC-9038

Figure A.3: Experimental prototype of the proposed APWM half-bridge series-resonantconverter interfacing the PV module.

Table A.4: Details of Magnetic Components used for the Prototype of the ConverterInterfacing PV Module

Component DetailsMaterial 3C95Transformer core PQ32/30Primary winding 2 turns of 840 x 0.063mm litz wireSecondary winding (52+52) turns of 40 x 0.063mm litz wireResonant inductor core PQ26/25Resonant inductor winding 3 turns of 840 x 0.063mm litz wire

characterizing the resonant converter with the secondary winding of the transformer

shorted. The impedance characteristic of the tank is measured and shown in Fig. A.4.

It indicates that the resonant frequency is 100 kHz, which is used as the switching

frequency of the converter.

Fig. A.5 captures the key waveforms of the converter operating at the rated con-

ditions. Meanwhile, Figs. A.6 and A.7 demonstrate the ZVS turn-on of the top and

the bottom switch, respectively. The ZVS turn-on of the top switch is assisted solely

by the small magnetizing current, whereas that of the bottom switch is assisted by the

resultant of resonant current and magnetizing current. It should be noted from these

figures that, the turn-off transitions of the switches are hard-switched, and the turn-off

current of the top switch is higher than that of the bottom switch. This causes a slightly

higher turn-off loss in the top switch.

The operating waveforms of the converter at 50% load are illustrated in Figs. A.8

and A.9. In this case, the ZVS of the switches is well realized with the decreasing load

because of the negative shift in the magnetizing current of the transformer. Another

case study is based on the input voltage of 40 V, which results from the typical 72-cell

PV module. It is clear that the output voltage is regulated at 380 V and both switches

191


Figure A.4: Resonant tank impedance characteristic showing the resonant frequency of100 kHz.

Vi (10V/div) Vo (100V/div)

Ii (5A/div) Io (0.5A/div)

iLr (25A/div)

t:100us/div

Figure A.5: Key waveforms showing the operation of the PV interfacing converter atthe rated conditions.

t:1us/div

Vo (200V/div)

vds1 (10V/div)

vg1 (2V/div)

iLr (10A/div)

Figure A.6: ZVS turn-on of top switch of the proposed PV interfacing converter at fullload.

192


t:1us/div

Vo (200V/div)

vds2 (10V/div)

vg2 (2V/div)iLr (10A/div)

Figure A.7: ZVS turn-on of bottom switch of the proposed PV interfacing converter atfull load.

t:1us/div

Vo (200V/div)

vds1 (10V/div)vg1 (2V/div)

iLr (10A/div)

Figure A.8: ZVS turn-on of top switch of the proposed PV interfacing converter at 50%load.

undergo ZVS. The measured waveforms are presented in Fig. A.10.

Fig. A.11 shows the key voltage and current waveforms of the resonant tank oper-

ating at the rated conditions. It is evident that the magnitude of the negative peak of

resonant capacitor voltage is less than the transformer primary voltage. This is one of

the design requirements as explained in Chapter 3.

The loss mechanism of the converter at full-load condition is estimated and shown

in Fig. A.12. The measured efficiency is shown in Fig. A.13 with the variation of power

conversion from 10% to 100% of the rated capacity. The peak efficiency happens at 50%

of the rated power, which can be explained by the loss distribution in Fig. A.12. The

most dominant losses of the converter are the copper losses in the resonant inductor and

the transformer primary winding, which are proportional to the square of the resonant

tank current. Therefore, at 50% of rated power, these two values reduce to one-fourth

of their full-load values, giving rise to the peak efficiency of the converter.

Since the operation of a PV power system depends on environmental conditions,

the efficiency of the system at a single operating point cannot be the best index to

193


t:1us/div

Vo (200V/div)

vds2 (10V/div)

vg2 (2V/div)

iLr (10A/div)

Figure A.9: ZVS turn-on of bottom switch of the proposed PV interfacing converter at50% load.

t:1us/div

Vo (200V/div)

vds1 (20V/div)

vg1 (2V/div)

iLr (10A/div)

Figure A.10: Operation of the of the proposed PV interfacing converter at 40 V inputand full load of 240 W. The output voltage is regulated at 380 V and both the switchesundergo ZVS. Duty ratio required D = 0.3.

t:2us/div

vCr (20V/div)

vLr (20V/div)vpri (10V/div)

iLr (25A/div)

Figure A.11: Voltages across the resonant capacitor (vCr ), resonant inductor (vLr ) andtransformer primary winding (vpri) at full load. Note that the magnitude of the negativepeak of resonant capacitor voltage is less than the transformer primary voltage.

194


0

0.5

1

1.5

2

2.5

3

3.5

Pow

er lo

ss (

W)

Total Loss = 10.2W

Figure A.12: Theoretical loss distribution of the proposed PV interfacing converter atthe rated power of 240 W.

Table A.5: Different efficiencies of the Converter Interfacing PV Module

Efficiency ValueFull-load eff. 95%Peak eff. 96.8% (at 50% load)European eff. (EU) 95.56%Calif. Energy Commission eff. (CEC) 96.03%

represent its performance. Therefore, the weighted efficiency for PV power systems has

been defined by the European Efficiency (EU) and the California Energy Commission

efficiency (CEC), which are expressed in (A.1) and (A.2), respectively. The symbol ηx%

represents the efficiency measured at x% of the rated power, with η100% being the rated

power efficiency.

ηeu = 0.03×η5%+0.06×η10%+0.13×η20%+0.10×η30%+0.48×η50%+0.20×η100% (A.1)

ηcec = 0.04×η10%+0.05×η20%+0.12×η30%+0.21×η50%+0.53×η75%+0.05×η100% (A.2)

The distributed coefficients indicate the importance of the efficiency at each power

level based on assumptions about how often the PV converter will function at that power

level. They also reflect the abundance of solar resource in a particular geographical

location. Following the efficiency curve in Fig. A.13, a comprehensive evaluation of the

prototyped converter are summarized in Table A.5.

Furthermore, Table A.6 shows a qualitative comparison of the proposed converter

with a reference converter presented in [139], which was designed for the dc-dc stage

195

A.4. Summary

91

92

93

94

95

96

97

98

0 50 100 150 200 250

Effi

cie

ncy

(%

)

Load Power (W)

Figure A.13: Efficiency plot of the proposed PV interfacing converter with variation ofload.

Table A.6: Comparison of the Proposed PV Interfacing Converter with a ReferenceConverter

Parameter Converter in [139] Proposed ConverterNo. of MOSFETs 4 2No. of diodes 4 2Transformer core volume 11.5 cm3 (E41/17/12) 12.5 cm3 (PQ32/30)Resonant inductor volume 0 6.53 cm3 (PQ26/25)Switching frequency 50–110 kHz (variable) 100 kHz (fixed)Peak efficiency 97.6% 96.8%Design process Iterative and complex Equation-based and simple

of a solar microinverter with almost same specifications. It is clear that the proposed

converter features a simpler equation-based design with fixed-frequency operation as well

as a lower number of MOSFETs and diodes. The only visible drawback of the proposed

converter is the use of an external resonant inductor that also caused a slightly lower

efficiency. Nevertheless, this can be avoided by carefully integrating the series inductance

into the transformer, which has been done in the reference converter.

A.4 Summary

This appendix has investigated the feasibility of the usage of the APWM half-bridge se-

ries resonant DC-DC converter in modular PV power applications that demand a high

voltage conversion ratio and high conversion efficiency. The topology demonstrates the

advantages of low device-count, high modularity, high reliability, soft-switching, and rel-

atively low voltage stress on the switching devices. The experimental results demonstrate

that, with careful design of the high-frequency transformer, the proposed converter can

196


satisfy this requirement with an efficiency at par with the existing topologies and show

potential for further improvement. The prototyped system shows the peak efficiency of

96.80% and the CEC weighted efficiency of 96.03%.

197

Appendix B

Implementation of Control in

TI DSP F28335

A significant portion of time and effort of this Ph.D. work was allocated to the design

and implementation of control of the power converters in digital platforms. Although

dSPACE was used in the initial phase, it has many limitations for high-frequency con-

verters, which motivated us to migrate to the popular microcontroller F28335 from

Texas Instruments. The controller codes are presented here which may be of use to

fellow power electronics researchers.

B.1 The Problem with Generation of XOR-ed Pulses

It has been discussed in Chapters 2 and 4 that the gate pulses for the middle switches

of the nine-switch converter have to be generated by the logical XOR of the pulses for

the top switch and the bottom switch. However, since the PWM blocks/modules are

the terminal blocks of any microcontroller, no further logical operation is allowed on

the generated pulses in the microcontroller. The XOR has to be performed outside in a

separate software/hardware. In the initial phase of this PhD work, this was accomplished

by the hardware set-up as shown in Fig. B.1.

It is obvious that this external hardware adds additional complexities to the system,

like propagation delay, noise etc.

198

B. Implementation of Control in TI DSP F28335

Figure B.1: Hardware for generation of XOR pulses for the middle switches of thenine-switch converter: version-1 (left) and version-2 (right).

CMPA = RefU

Top

Mid

Bot

CMPB = RefD

Down count

Figure B.2: Switching logic for generation of XOR pulses in F28335 controller with adown-count mode of the counter (sawtooth carrier).

B.2 Indirect XOR-ed Pulses from F28335 Microcon-

troller

In the later phase of our work, we were able to figure out that with proper assignment

of duty-values to the Compare Registers (CMPA and CMPB) and also, proper decision

of events for the Action Qualifier Registers (AQCTLA and AQCTLB) it is possible to

achieve XOR pulses directly from the ePWM modules of the F28335 microcontroller.

Fig. B.2 shows the switching logic for a down-count mode of the counter (sawtooth

carrier). Let us take the example for the first leg of the converter. ePWM1 is used for

generation gate pulses for the top and bottom switches (SA and SX). In particular, pulse

from ePWM1A is given to SA and that from ePWM1B is given to SX . The switching

logic can be obtained by setting the following actions for the Action Qualifier Registers.

For AQCTLA:

199

B.2. Indirect XOR-ed Pulses from F28335 Microcontroller

Action when CTR = 0 −−−> Do nothing (00)

Action when CTR = PRD −−−> Clear (01)

Action when CTR = CMPA on UP Count −−−> Do nothing (00)

Action when CTR = CMPA on DOWN Count −−−> Set (10)

Action when CTR = CMPB on UP Count −−−> Do nothing (00)

Action when CTR = CMPB on DOWN Count −−−> Do nothing (00)

Therefore ,

EPwm1Regs .AQCTLA. a l l = 0000 00 00 10 00 01 00 ( binary ) = 0x0084 ( hex )

For AQCTLB:


Action when CTR = PRD −−−> Set (10)


Action when CTR = CMPA on DOWN Count −−−> Do nothing (00)


Action when CTR = CMPB on DOWN Count −−−> Clear (01)

Therefore ,

EPwm1Regs .AQCTLB. a l l = 0000 01 00 00 00 10 00 ( binary ) = 0x0408 ( hex )

However , with the deadband module in a c t i v e high complementary mode ,

EPwm1Regs .AQCTLB. a l l = 0000 10 00 00 00 01 00 ( binary ) = 0x0804 ( hex )

Similarly, ePWM2 and ePWM3 are used for the top and bottom switches of the sec-

ond and the third leg of the converter. For middle switches of the converter, ePWM4A,

ePWM5A and ePWM6A are used. For instance, pulse from ePWM4A is given to switch

SAX . The following actions for the Action Qualifier Registers are to be configured.

For AQCTLA:


Action when CTR = PRD −−−> Do nothing (00)


Action when CTR = CMPA on DOWN Count −−−> Clear (01)


Action when CTR = CMPB on DOWN Count −−−> Set (10)

200


Therefore ,

EPwm4Regs .AQCTLA. a l l = 0000 10 00 01 00 00 00 ( binary ) = 0x0840 ( hex )

B.3 The Controller Code

This section provides the entire code for both sinusoidal PWM (SPWM) as well as Space

Vector PWM (SVPWM). Many of the functions used in the code are taken from the

C28x Solar Library released by Texas Instruments Inc. [140]. Therefore it is important

that this library is installed and included in the compiler.

B.3.1 Sinusoidal PWM

The directories included in the build settings are:

1. "C:\tidcs\c28\DSP2833x\v131\DSP2833x_common\include"

2. "C:\tidcs\c28\DSP2833x\v131\DSP2833x_headers\include"

3. "C:\tidcs\c28\solar\v1.2\float\include"

Following is the complete code for this case.

//−−−−−−−−−Star t o f code−−−−−−−−−−

#inc lude "DSP2833x_Device . h "

#inc lude "math . h "

#inc lude " Solar_F . h "

extern void I n i t Sy sCt r l ( void ) ;

extern void I n i tP i eC t r l ( void ) ;

extern void In i tP ieVectTable ( void ) ;

extern void InitCpuTimers ( void ) ;

extern void ConfigCpuTimer ( s t r u c t CPUTIMER_VARS ∗ , f l o a t , f l o a t ) ;

extern void InitAdc ( void ) ;

// Prototype statements f o r f unc t i on s found with in t h i s f i l e

void I n i t i a l i z e ( void ) ; // sys c t r l , GPIO, EPWM, ADC

void Gpio_select ( void ) ;

void Setup_ePWM( void ) ;

201

B.3. The Controller Code

void adc_setup ( void ) ;

i n t e r r up t void cpu_timer0_isr ( void ) ;

i n t e r r up t void adc_isr ( void ) ; // ADC End o f Sequence ISR

ABC_DQ0_POS_F abc_dq0_pos1 , abc_dq0_pos2 ;

DQ0_ABC_F dq0_abc1 ;

SPLL_3ph_SRF_F s p l l 1 ;

f l o a t T_s = 10e−6;

f l o a t V_a, V_b, V_c, V_dc , V_o, I_a , I_b , I_c ;

f l o a t I_d_err [ 2 ] = 0 . 0 , 0 . 0 , I_q_err [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t V_dc_err [ 2 ] = 0 . 0 , 0 . 0 , V_o_err [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t I_q_ref = 0 . 0 , V_dc_ref = 570 .0 , V_o_ref = 4 8 . 0 ;

f l o a t I_d_ref ; //= 6 . 0 ;

f l o a t V_d, V_q, I_d , I_q , V_d_ref , V_q_ref ;

f l o a t d_decouple , q_decouple ;

f l o a t decouple = 0 . 5652 ; // decouple = 2∗3 .14∗60∗0 .0015 (= 2∗ pi ∗ f ∗L)

f l o a t temp0 , temp1 , temp2 , temp3 , temp4 , temp5 , temp6 , temp7 ;

f l o a t ModuA,ModuB,ModuC, ModuD;

f l o a t V_aoff = 1665 .0 , V_boff = 1693 .0 , V_coff = 1583 . 0 ;

f l o a t V_dcoff = 1624 .0 , V_ooff = 1550 . 0 ;

f l o a t I_ao f f = 2252 . 0 ; // , I_bof f = 2252 .0 , I_co f f = 2252 . 0 ;

f l o a t v_gain_a = 0.1062 , v_gain_b = 0.1062 , v_gain_c = 0 . 1149 ;

f l o a t v_gain_dc = 0 .24 , v_gain_o = 0 . 1 2 5 ;

f l o a t curr_gain = 0 . 01115 ;

f l o a t PI_out_dframe [ 2 ] = 0 . 0 , 0 . 0 , PI_out_qframe [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t PI_out_vdc [ 2 ] = 0 . 0 , 0 . 0 , PI_out_V_o [ 2 ] = 0 . 0 , 0 . 0 ;

//Output vo l tage s en s ing − 3 rd order Butterworth f i l t e r

f l o a t butt_b [ 4 ] = 0 .0200834 ,0 .0401667 ,0 .02008336 ;

f l o a t butt_a [ 4 ] = 1.0000 , −1 .56101807 ,0 .6413515 ;

f l o a t V_o_x [ 4 ] = 0 . 0 , 0 . 0 , 0 . 0 , 0 . 0 ;

f l o a t V_o_y [ 4 ] = 0 . 0 , 0 . 0 , 0 . 0 , 0 . 0 ;

//PI c o n t r o l l e r

202


// f l o a t dq_K_p = 10 .0 , dq_K_i = 1000 . 0 ;

// f l o a t vdc_K_p = 0 .01 , vdc_K_i = 1 . 0 ;

// f l o a t V_o_K_p = 0.00007 , V_o_K_i = 0 . 0 1 ;

//Use o f f i r s t order hold

f l o a t dq_A_0 = 10 .00499 ; //dq_A_0 = dq_K_p∗ ( ( (dq_K_i∗T_s)/(2∗dq_K_p) ) + 1)

f l o a t dq_A_1 = ( −9 .995) ; //dq_A_1 = dq_K_p∗ ( ( (dq_K_i∗T_s)/(2∗dq_K_p) ) − 1)

f l o a t vdc_A_0 = 0 .010005 ;

f l o a t vdc_A_1 = (−0.009995) ;

f l o a t V_o_A_0 = 0.00007005 ;

f l o a t V_o_A_1 = (−0.00006995) ;

void main ( void )

I n i t i a l i z e ( ) ;

//General setup

I n i tP i eC t r l ( ) ; // ba s i c setup o f PIE tab l e from DSP2833x_PieCtrl . c

In i tP ieVectTable ( ) ; // d e f au l t ISR ’ s in PIE

EALLOW;

PieVectTable .TINT0 = &cpu_timer0_isr ; // Into0> CPU timer

PieVectTable .ADCINT = &adc_isr ; // ADC Int

EDIS ;

InitCpuTimers ( ) ; // ba s i c setup CPU Timer0 , 1 and 2

ConfigCpuTimer(&CpuTimer0 , 1 50 , (T_s∗1000000) ) ;

PieCtr lRegs . PIEIER1 . b i t . INTx7 = 1 ; // Cpu Timer

PieCtr lRegs . PIEIER1 . b i t . INTx6 = 1 ; // ADC in t e r r up t i s a s s i gned to epwm

IER |=1;

EINT;

ERTM;

CpuTimer0Regs .TCR. b i t .TSS = 0 ; // s t a r t t imer0

ABC_DQ0_POS_F_init(&abc_dq0_pos1 ) ;


DQ0_ABC_F_init(&dq0_abc1 ) ;

SPLL_3ph_SRF_F_init (60 ,T_s,& s p l l 1 ) ;

203


whi l e (1 )

whi l e (CpuTimer0 . InterruptCount == 0 ) ;

CpuTimer0 . InterruptCount = 0 ;

EALLOW;

SysCtrlRegs .WDKEY = 0x55 ; // s e r v i c e WD #1

EDIS ;

i n t e r r up t void cpu_timer0_isr ( void )

CpuTimer0 . InterruptCount++;

EALLOW;

SysCtrlRegs .WDKEY = 0xAA; // s e r v i c e WD #2

EDIS ;

PieCtr lRegs .PIEACK. a l l = PIEACK_GROUP1;

abc_dq0_pos1 . a = V_a;

abc_dq0_pos1 . b = V_b;

abc_dq0_pos1 . c = V_c;

abc_dq0_pos1 . s i n = ( f l o a t ) s i n ( ( s p l l 1 . theta [ 1 ] ) ) ;

abc_dq0_pos1 . cos = ( f l o a t ) cos ( ( s p l l 1 . theta [ 1 ] ) ) ;

ABC_DQ0_POS_F_FUNC(&abc_dq0_pos1 ) ;

V_d = abc_dq0_pos1 . d ;

V_q = abc_dq0_pos1 . q ;

s p l l 1 . v_q [ 0 ] = ( abc_dq0_pos1 . q ) ;

SPLL_3ph_SRF_F_FUNC(& s p l l 1 ) ;

abc_dq0_pos2 . a = I_a ;

abc_dq0_pos2 . b = I_b ;

abc_dq0_pos2 . c = I_c ;


204




I_d = abc_dq0_pos2 . d ;

I_q = abc_dq0_pos2 . q ;

d_decouple = decouple ∗I_d ;

q_decouple = decouple ∗I_q ;

V_o_err [ 0 ] = V_o_ref − V_o;

PI_out_V_o [ 0 ] = (V_o_A_0∗V_o_err [ 0 ] ) + (V_o_A_1∗V_o_err [ 1 ] )

+ PI_out_V_o [ 1 ] ;

i f (PI_out_V_o[0 ] >0 .35) PI_out_V_o [ 0 ] = 0 . 3 5 ;

i f (PI_out_V_o [0 ] <(0 . 01 ) ) PI_out_V_o [ 0 ] = 0 . 0 1 ;

V_o_err [ 1 ] = V_o_err [ 0 ] ; PI_out_V_o [ 1 ] = PI_out_V_o [ 0 ] ;

ModuD = PI_out_V_o [ 0 ] ;

// i f ( I_d_ref <2.5) ModuD = 0 . 3 5 ;

V_dc_err [ 0 ] = V_dc_ref − V_dc ;

PI_out_vdc [ 0 ] = (vdc_A_0∗V_dc_err [ 0 ] ) + (vdc_A_1∗V_dc_err [ 1 ] )

+ PI_out_vdc [ 1 ] ;

i f (PI_out_vdc [0 ] >10 .00) PI_out_vdc [ 0 ] = 10 . 0 0 ;

i f (PI_out_vdc [0 ] <(−10.00)) PI_out_vdc [ 0 ] = ( −10 .00) ;

V_dc_err [ 1 ] = V_dc_err [ 0 ] ; PI_out_vdc [ 1 ] = PI_out_vdc [ 0 ] ;

I_d_ref = PI_out_vdc [ 0 ] ;

I_d_err [ 0 ] = I_d_ref − I_d ;

I_q_err [ 0 ] = I_q_ref−I_q ;

PI_out_dframe [ 0 ] = (dq_A_0∗ I_d_err [ 0 ] ) + (dq_A_1∗ I_d_err [ 1 ] )

+ PI_out_dframe [ 1 ] ;

i f ( PI_out_dframe [0 ] >100 .00) PI_out_dframe [ 0 ] = 100 . 0 0 ;

i f ( PI_out_dframe [0] <(−100.00)) PI_out_dframe [ 0 ] = (−100.00) ;

I_d_err [ 1 ] = I_d_err [ 0 ] ; PI_out_dframe [ 1 ] = PI_out_dframe [ 0 ] ;

205


PI_out_qframe [ 0 ] = (dq_A_0∗ I_q_err [ 0 ] ) + (dq_A_1∗ I_q_err [ 1 ] )

+ PI_out_qframe [ 1 ] ;

i f ( PI_out_qframe [0 ] >100 .00) PI_out_qframe [ 0 ] = 100 . 0 0 ;

i f ( PI_out_qframe [0] <(−100.00)) PI_out_qframe [ 0 ] = (−100.00) ;

I_q_err [ 1 ] = I_q_err [ 0 ] ; PI_out_qframe [ 1 ] = PI_out_qframe [ 0 ] ;

V_d_ref = V_d − PI_out_dframe [ 0 ] + q_decouple ;

V_q_ref = V_q − PI_out_qframe [ 0 ] − d_decouple ;

V_d_ref = V_d_ref ∗0 . 0067 ; // i d e a l l y i t should be = V_d_ref/V_dc

V_q_ref = V_q_ref ∗0 . 0067 ; // i d e a l l y i t should be = V_q_ref/V_dc

i f (V_d_ref>0.99) V_d_ref = 0 . 9 9 ;

i f (V_d_ref<(−0.99)) V_d_ref = ( −0 .99) ;

i f (V_q_ref>0.99) V_q_ref = 0 . 9 9 ;

i f (V_q_ref<(−0.99)) V_q_ref = ( −0 .99) ;

dq0_abc1 . d = V_d_ref ;

dq0_abc1 . q = V_q_ref ;

dq0_abc1 . z = 0 . 0 ;

dq0_abc1 . s i n = ( f l o a t ) s i n ( ( s p l l 1 . theta [ 1 ] ) ) ;

dq0_abc1 . cos = ( f l o a t ) cos ( ( s p l l 1 . theta [ 1 ] ) ) ;

DQ0_ABC_F_FUNC(&dq0_abc1 ) ;

ModuA = 0.3∗ dq0_abc1 . a+0.7 ; // ModuA=(0.6∗( dq0_abc1 . a ) )/2+0 .7 ;

ModuB = 0.3∗ dq0_abc1 . b+0.7 ;

ModuC = 0.3∗ dq0_abc1 . c +0.7 ;

EPwm1Regs .CMPA. ha l f .CMPA = (ModuA)∗EPwm1Regs .TBPRD; //epwm1A f o r switch A

EPwm2Regs .CMPA. ha l f .CMPA = (ModuB)∗EPwm2Regs .TBPRD; //epwm2A f o r switch B

EPwm3Regs .CMPA. ha l f .CMPA = (ModuC)∗EPwm3Regs .TBPRD; //epwm3A f o r switch C

EPwm1Regs .CMPB = (ModuD)∗EPwm1Regs .TBPRD; //epwm1B f o r switch X

EPwm2Regs .CMPB = (ModuD)∗EPwm2Regs .TBPRD; //epwm2B f o r switch Y

EPwm3Regs .CMPB = (ModuD)∗EPwm3Regs .TBPRD; //epwm3B f o r switch Z

EPwm4Regs .CMPA. ha l f .CMPA = (ModuA)∗EPwm4Regs .TBPRD; //epwm4A f o r switch AX

EPwm5Regs .CMPA. ha l f .CMPA = (ModuB)∗EPwm5Regs .TBPRD; //epwm5A f o r switch BY

EPwm6Regs .CMPA. ha l f .CMPA = (ModuC)∗EPwm6Regs .TBPRD; //epwm6A f o r switch CZ

206


EPwm4Regs .CMPB = (ModuD)∗EPwm4Regs .TBPRD;



i n t e r r up t void adc_isr ( void )

// A phase VOLTAGE sens ing

temp0 = (AdcMirror .ADCRESULT0) − V_aoff ;

V_a = temp0∗v_gain_a ;

// B phase VOLTAGE sens ing

temp1 = (AdcMirror .ADCRESULT1) − V_boff ;

V_b = temp1∗v_gain_b ;

// C phase VOLTAGE sens ing

temp2 = (AdcMirror .ADCRESULT2) − V_coff ;

V_c = temp2∗v_gain_c ;

// DC l i n k VOLTAGE sens ing

temp6 = (AdcMirror .ADCRESULT6) − V_dcoff ;

V_dc = temp6∗v_gain_dc ;

// Output VOLTAGE sens ing

temp7 = (AdcMirror .ADCRESULT7) − V_ooff ;

temp7 = temp7∗v_gain_o ;

//Third order low pass Butterworth f i l t e r

V_o_x [ 0 ] = temp7 ;

V_o_y [ 0 ] = butt_b [ 0 ] ∗V_o_x [ 0 ] + butt_b [ 1 ] ∗V_o_x [ 1 ] + butt_b [ 2 ] ∗V_o_x [ 2 ]

− butt_a [ 1 ] ∗V_o_y [ 1 ] − butt_a [ 2 ] ∗V_o_y [ 2 ] ;

V_o = V_o_y [ 0 ] ;

V_o_x [ 2 ] = V_o_x [ 1 ] ; V_o_x [ 1 ] = V_o_x [ 0 ] ;

V_o_y [ 2 ] = V_o_y [ 1 ] ; V_o_y [ 1 ] = V_o_y [ 0 ] ;

// A phase CURRENT sens ing

207


temp3 = (AdcMirror .ADCRESULT3) − I_ao f f ;

I_a = temp3∗ curr_gain ;

// B phase CURRENT sens ing


I_b = temp4∗ curr_gain ;

// C phase CURRENT sens ing


I_c = temp5∗ curr_gain ;

// R e i n i t i a l i z e f o r next ADC sequence

AdcRegs .ADCTRL2. b i t .RST_SEQ1 = 1 ; // Reset SEQ1

AdcRegs .ADCST. b i t . INT_SEQ1_CLR = 1 ; // Clear INT SEQ1 b i t

PieCtr lRegs .PIEACK. a l l = PIEACK_GROUP1; // Acknowledge i n t e r r up t to PIE

void I n i t i a l i z e ( void )

I n i t Sy sCt r l ( ) ; // Bas ic Core I n i t from DSP2833x_SysCtrl . c

EALLOW;

SysCtrlRegs .WDCR= 0x00AF ; // Re−enable the watchdog

EDIS ; // 0x00AF to NOT d i s ab l e the Watchdog , P r e s c a l e r = 64

DINT; // Disab le a l l i n t e r r up t s

Gpio_select ( ) ;

Setup_ePWM( ) ;

InitAdc ( ) ;

adc_setup ( ) ;

void Gpio_select ( void )

EALLOW;

GpioCtrlRegs .GPAMUX1. a l l = 0 ; // GPIO15 . . . GPIO0 = General Puropse I /O

208


GpioCtrlRegs .GPAMUX1. b i t .GPIO0 = 1 ; // ePWM1A ac t i v e

GpioCtrlRegs .GPAMUX1. b i t .GPIO1 = 1 ; // ePWM1B ac t i v e











GpioCtrlRegs .GPAMUX2. a l l = 0 ; // GPIO31 . . . GPIO16 = Gen . Purpose I /O

GpioCtrlRegs .GPBMUX1. a l l = 0 ; // GPIO47 . . . GPIO32 = Gen . Purpose I /O


GpioCtrlRegs .GPCMUX1. a l l = 0 ; // GPIO79 . . . GPIO64 = Gen . Purpose I /O


GpioCtrlRegs .GPADIR. a l l = 0 ; // GPIO0−31 as inputs

GpioCtrlRegs .GPADIR. b i t .GPIO9 = 1 ; // p e r i ph e r a l e xp l o r e r : LD1 at GPIO9



GpioCtrlRegs .GPBDIR. a l l = 0 ; // GPIO63−32 as inputs

GpioCtrlRegs .GPBDIR. b i t .GPIO34 = 1 ; // p e r i ph e r a l e xp l o r e r : LD3 at GPIO34


GpioCtrlRegs .GPCDIR. a l l = 0 ; // GPIO87−64 as inputs

EDIS ;

void Setup_ePWM( void )

209


//epwm1

//epwm1A f o r switch A & epwm1B f o r switch X

EPwm1Regs .TBCTL. b i t .CLKDIV = 0 ; // CLKDIV = 1

EPwm1Regs .TBCTL. b i t .HSPCLKDIV = 0 ; // HSPCLKDIV = 1

EPwm1Regs .TBCTL. b i t .CTRMODE = 1 ; // down mode

EPwm1Regs .AQCTLA. a l l = 0x0084 ;

EPwm1Regs .AQCTLB. a l l = 0x0804 ;

EPwm1Regs .TBPRD = 2490 ; // 60 .24 kHz , TBPRD = 150MHz/60.24kHz

EPwm1Regs .CMPA. ha l f .CMPA = EPwm1Regs .TBPRD/2 ; // 50% duty cy c l e f i r s t

//Dead band f o r epwm1

EPwm1Regs .DBRED = 62 ; // 415 ns de lay f o r r i s i n g edge

EPwm1Regs .DBFED = 62 ; // 415 ns de lay f o r f a l l i n g edge

EPwm1Regs .ETSEL. a l l = 0 ;

EPwm1Regs .DBCTL. b i t .OUT_MODE = 3 ; // RED and FED (DBM f u l l y enabled )

EPwm1Regs .DBCTL. b i t .POLSEL = 2 ; // Active high complementary

EPwm1Regs .DBCTL. b i t .IN_MODE = 2 ; // 1A f o r RED, 1B f o r FED

//epwm2

//epwm2A f o r switch B & epwm2B f o r switch Y














210



//epwm3

//epwm3A f o r switch C & epwm3B f o r switch Z















//epwm4

//epwm4A f o r switch AX





//EPwm4Regs .AQCTLB. a l l = 0x0408 ;





EPwm4Regs .DBFED = 00 ; // No delay f o r f a l l i n g edge



211


EPwm4Regs .DBCTL. b i t .POLSEL = 0 ; // Active high

EPwm4Regs .DBCTL. b i t .IN_MODE = 0 ; // ePWM4A = source f o r both RED & FED

//epwm5

//epwm5A f o r switch BY















//epwm6

//epwm6A f o r switch CZ












212





//phase s h i f t

EPwm1Regs .TBCTL. b i t .SYNCOSEL = 1 ; // generate a syncout i f CTR = 0

EPwm2Regs .TBCTL. b i t .PHSEN = 1 ; // enable phase s h i f t f o r ePWM2

EPwm2Regs .TBCTL. b i t .SYNCOSEL = 0 ; // sync in = syncout

EPwm2Regs .TBPHS. h a l f .TBPHS = 830 ; // 120 phase s h i f t













void adc_setup ( void )

AdcRegs .ADCTRL1. a l l = 0 ;

AdcRegs .ADCTRL1. b i t .ACQ_PS = 7 ; // 8 x ADCCLK

AdcRegs .ADCTRL1. b i t .SEQ_CASC = 1 ; // cascaded sequencer

AdcRegs .ADCTRL1. b i t .CPS = 0 ; // d iv id e by 1

AdcRegs .ADCTRL1. b i t .CONT_RUN = 0 ; // s i n g l e run mode

213



AdcRegs .ADCTRL2. b i t .INT_ENA_SEQ1 = 1 ; // enable SEQ1 in t e r r up t

AdcRegs .ADCTRL2. b i t .EPWM_SOCA_SEQ1 = 1 ; // SEQ1 s t a r t from ePWM_SOCA t r i g

AdcRegs .ADCTRL2. b i t .INT_MOD_SEQ1 = 0 ; // i n t e r r up t a f t e r every end o f seq

AdcRegs .ADCTRL3. b i t .ADCCLKPS = 3 ;

AdcRegs .ADCMAXCONV. a l l = 7 ; // 8 conve r s i on s from Sequencer 1

AdcRegs .ADCCHSELSEQ1. b i t .CONV00 = 0 ; // ADCINA0 as 1 s t SEQ1 conv

AdcRegs .ADCCHSELSEQ1. b i t .CONV01 = 1 ; // ADCINA1 as 2nd SEQ1 conv

AdcRegs .ADCCHSELSEQ1. b i t .CONV02 = 2 ; // ADCINA2 as 3 rd SEQ1 conv

AdcRegs .ADCCHSELSEQ1. b i t .CONV03 = 3 ; // ADCINA3 as 4 th SEQ1 conv





EPwm2Regs .ETPS. a l l = 0x0100 ; // Conf igure ADC s t a r t by ePWM2

EPwm2Regs .ETSEL. a l l = 0x0F00 ; // Enable SOCA to ADC

//−−−−−−−−−End o f code−−−−−−−−−−

B.3.2 Space Vector PWM

The SVPWM is implemented in similar way as described in [141]. Also to reduce the

execution time of the code the fastRTS library is used here, which should be properly

configured in the build settings as described in [142]. The directories included in the

build settings are:

1. "C:\ti\ccsv6\tools\compiler\c2000_15.12.3.LTS\include"

2. "C:\ti\controlSUITE\libs\math\FPUfastRTS\V100\include"

3. "C:\tidcs\c28\DSP2833x\v131\DSP2833x_common\include"

4. "C:\tidcs\c28\DSP2833x\v131\DSP2833x_headers\include"

5. "C:\tidcs\c28\solar\v1.2\float\include"

214


Following is the complete code for this case.

//−−−−−−−−−Star t o f code−−−−−−−−−−

#inc lude "DSP2833x_Device . h "

#inc lude "math . h "

#inc lude " Solar_F . h "

#inc lude "C28x_FPU_FastRTS . h "

extern void I n i t Sy sCt r l ( void ) ;

extern void I n i tP i eC t r l ( void ) ;

extern void In i tP ieVectTable ( void ) ;

extern void InitCpuTimers ( void ) ;

extern void ConfigCpuTimer ( s t r u c t CPUTIMER_VARS ∗ , f l o a t , f l o a t ) ;

extern void InitAdc ( void ) ;

// Prototype statements f o r f unc t i on s found with in t h i s f i l e

void I n i t i a l i z e ( void ) ; // sys c t r l , GPIO, EPWM, ADC

void Gpio_select ( void ) ;

void Setup_ePWM( void ) ;

void adc_setup ( void ) ;

i n t e r r up t void cpu_timer0_isr ( void ) ;

i n t e r r up t void adc_isr ( void ) ; // ADC End o f Sequence ISR

ABC_DQ0_POS_F abc_dq0_pos1 , abc_dq0_pos2 ;

iPARK_F ipark1 ;

SPLL_3ph_SRF_F s p l l 1 ;

f l o a t T_s = 10e−6;

f l o a t p i = 3 .1416 , twopi = 6 .2832 , p ibythree = 1 . 0472 ;

f l o a t twopibythree = 2 .0944 , f ou rp iby th r e e = 4 . 1888 ;

f l o a t f i v e p i b y t h r e e = 5 .2360 , twobythree = 0 . 6667 ;

f l o a t s q r t t h r e e = 1 .732 , onebysqr t three = 0 . 5774 ;

f l o a t V_a, V_b, V_c, V_dc , V_o, I_a , I_b , I_c ;

f l o a t I_d_err [ 2 ] = 0 . 0 , 0 . 0 , I_q_err [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t V_dc_err [ 2 ] = 0 . 0 , 0 . 0 , V_o_err [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t I_q_ref = 0 . 0 , V_dc_ref = 420 .0 , V_o_ref = 380 . 0 ;

215


f l o a t I_d_ref ; //= 6 . 0 ;

f l o a t V_alpha , V_beta ,V_mag,V_ang , Sector , S e c t o r_o f f s e t ;

f l o a t alpha , ta , tb , taon , tbon , tcon ;

f l o a t onebyvdc , t_const ;

f l o a t V_d, V_q, I_d , I_q , V_d_ref , V_q_ref ;

f l o a t d_decouple , q_decouple ;

f l o a t decouple = 0 . 5652 ; // decouple = 2∗3 .14∗60∗0 .0015 (= 2∗ pi ∗ f ∗L)

f l o a t temp0 , temp1 , temp2 , temp3 , temp4 , temp5 , temp6 , temp7 ;

f l o a t ModuA,ModuB,ModuC, ModuD;

f l o a t V_aoff = 1665 .0 , V_boff = 1693 .0 , V_coff = 1583 . 0 ;

f l o a t V_dcoff = 1624 .0 , V_ooff = 1550 . 0 ;

f l o a t I_ao f f = 2252 . 0 ; // , I_bof f = 2252 .0 , I_co f f = 2252 . 0 ;

f l o a t v_gain_a = 0.1062 , v_gain_b = 0.1062 , v_gain_c = 0 . 1149 ;

f l o a t v_gain_dc = 0 .24 , v_gain_o = 0 . 1 2 5 ;

f l o a t curr_gain = 0 . 01115 ;

f l o a t PI_out_dframe [ 2 ] = 0 . 0 , 0 . 0 , PI_out_qframe [ 2 ] = 0 . 0 , 0 . 0 ;

f l o a t PI_out_vdc [ 2 ] = 0 . 0 , 0 . 0 , PI_out_V_o [ 2 ] = 0 . 0 , 0 . 0 ;

//Output vo l tage s en s ing − 3 rd order Butterworth f i l t e r

f l o a t butt_b [ 4 ] = 0 .0200834 ,0 .0401667 ,0 .02008336 ;

f l o a t butt_a [ 4 ] = 1.0000 , −1 .56101807 ,0 .6413515 ;

f l o a t V_o_x [ 4 ] = 0 . 0 , 0 . 0 , 0 . 0 , 0 . 0 ;

f l o a t V_o_y [ 4 ] = 0 . 0 , 0 . 0 , 0 . 0 , 0 . 0 ;

//PI c o n t r o l l e r

// f l o a t dq_K_p = 10 .0 , dq_K_i = 1000 . 0 ;

// f l o a t vdc_K_p = 0 .01 , vdc_K_i = 1 . 0 ;

// f l o a t V_o_K_p = 0.00007 , V_o_K_i = 0 . 0 1 ;

//Use o f f i r s t order hold

f l o a t dq_A_0 = 10 .00499 ; //dq_A_0 = dq_K_p∗ ( ( (dq_K_i∗T_s)/(2∗dq_K_p) ) + 1)

f l o a t dq_A_1 = ( −9 .995) ; //dq_A_1 = dq_K_p∗ ( ( (dq_K_i∗T_s)/(2∗dq_K_p) ) − 1)

f l o a t vdc_A_0 = 0 .010005 ;

f l o a t vdc_A_1 = (−0.009995) ;

f l o a t V_o_A_0 = 0.00007005 ;

f l o a t V_o_A_1 = (−0.00006995) ;

216


void main ( void )

I n i t i a l i z e ( ) ;

//General setup

I n i tP i eC t r l ( ) ; // ba s i c setup o f PIE tab l e from DSP2833x_PieCtrl . c

In i tP ieVectTable ( ) ; // d e f au l t ISR ’ s in PIE

EALLOW;

PieVectTable .TINT0 = &cpu_timer0_isr ; // Into0> CPU timer

PieVectTable .ADCINT = &adc_isr ; // ADC Int

EDIS ;

InitCpuTimers ( ) ; // ba s i c setup CPU Timer0 , 1 and 2

ConfigCpuTimer(&CpuTimer0 , 1 50 , (T_s∗1000000) ) ;

PieCtr lRegs . PIEIER1 . b i t . INTx7 = 1 ; // Cpu Timer

PieCtr lRegs . PIEIER1 . b i t . INTx6 = 1 ; // ADC in t e r r up t i s a s s i gned to epwm

IER |=1;

EINT;

ERTM;

CpuTimer0Regs .TCR. b i t .TSS = 0 ; // s t a r t t imer0



iPARK_F_init(& ipark1 ) ;

SPLL_3ph_SRF_F_init (60 ,T_s,& s p l l 1 ) ;

whi l e (1 )

whi l e (CpuTimer0 . InterruptCount == 0 ) ;

CpuTimer0 . InterruptCount = 0 ;

EALLOW;

SysCtrlRegs .WDKEY = 0x55 ; // s e r v i c e WD #1

EDIS ;

217


i n t e r r up t void cpu_timer0_isr ( void )

CpuTimer0 . InterruptCount++;

EALLOW;

SysCtrlRegs .WDKEY = 0xAA; // s e r v i c e WD #2

EDIS ;

PieCtr lRegs .PIEACK. a l l = PIEACK_GROUP1;

abc_dq0_pos1 . a = V_a;

abc_dq0_pos1 . b = V_b;

abc_dq0_pos1 . c = V_c;




V_d = abc_dq0_pos1 . d ;

V_q = abc_dq0_pos1 . q ;

s p l l 1 . v_q [ 0 ] = ( abc_dq0_pos1 . q ) ;

SPLL_3ph_SRF_F_FUNC(& s p l l 1 ) ;

abc_dq0_pos2 . a = I_a ;

abc_dq0_pos2 . b = I_b ;

abc_dq0_pos2 . c = I_c ;




I_d = abc_dq0_pos2 . d ;

I_q = abc_dq0_pos2 . q ;

d_decouple = decouple ∗I_d ;

q_decouple = decouple ∗I_q ;

V_o_err [ 0 ] = V_o_ref − V_o;

218


PI_out_V_o [ 0 ] = (V_o_A_0∗V_o_err [ 0 ] ) + (V_o_A_1∗V_o_err [ 1 ] )

+ PI_out_V_o [ 1 ] ;

i f (PI_out_V_o[0 ] >0 .28) PI_out_V_o [ 0 ] = 0 . 2 8 ;

i f (PI_out_V_o [0 ] <(0 . 01 ) ) PI_out_V_o [ 0 ] = 0 . 0 1 ;

V_o_err [ 1 ] = V_o_err [ 0 ] ; PI_out_V_o [ 1 ] = PI_out_V_o [ 0 ] ;

ModuD = PI_out_V_o [ 0 ] ;

// i f ( I_d_ref <2.5) ModuD = 0 . 2 8 ;

V_dc_err [ 0 ] = V_dc_ref − V_dc ;

PI_out_vdc [ 0 ] = (vdc_A_0∗V_dc_err [ 0 ] ) + (vdc_A_1∗V_dc_err [ 1 ] )

+ PI_out_vdc [ 1 ] ;

i f (PI_out_vdc [0 ] >10 .00) PI_out_vdc [ 0 ] = 10 . 0 0 ;

i f (PI_out_vdc [0 ] <(−10.00)) PI_out_vdc [ 0 ] = ( −10 .00) ;

V_dc_err [ 1 ] = V_dc_err [ 0 ] ; PI_out_vdc [ 1 ] = PI_out_vdc [ 0 ] ;

I_d_ref = PI_out_vdc [ 0 ] ;

I_d_err [ 0 ] = I_d_ref − I_d ;

I_q_err [ 0 ] = I_q_ref−I_q ;

PI_out_dframe [ 0 ] = (dq_A_0∗ I_d_err [ 0 ] ) + (dq_A_1∗ I_d_err [ 1 ] )

+ PI_out_dframe [ 1 ] ;

i f ( PI_out_dframe [0 ] >100 .00) PI_out_dframe [ 0 ] = 100 . 0 0 ;

i f ( PI_out_dframe [0] <(−100.00)) PI_out_dframe [ 0 ] = (−100.00) ;

I_d_err [ 1 ] = I_d_err [ 0 ] ; PI_out_dframe [ 1 ] = PI_out_dframe [ 0 ] ;

PI_out_qframe [ 0 ] = (dq_A_0∗ I_q_err [ 0 ] ) + (dq_A_1∗ I_q_err [ 1 ] )

+ PI_out_qframe [ 1 ] ;

i f ( PI_out_qframe [0 ] >100 .00) PI_out_qframe [ 0 ] = 100 . 0 0 ;

i f ( PI_out_qframe [0] <(−100.00)) PI_out_qframe [ 0 ] = (−100.00) ;

I_q_err [ 1 ] = I_q_err [ 0 ] ; PI_out_qframe [ 1 ] = PI_out_qframe [ 0 ] ;

V_d_ref = V_d − PI_out_dframe [ 0 ] + q_decouple ;

V_q_ref = V_q − PI_out_qframe [ 0 ] − d_decouple ;

ipark1 . d = V_d_ref ;

219


ipark1 . q = V_q_ref ;

ipark1 . z = 0 . 0 ;

ipark1 . s i n = ( f l o a t ) s i n ( ( s p l l 1 . theta [ 1 ] ) ) ;

ipark1 . cos = ( f l o a t ) cos ( ( s p l l 1 . theta [ 1 ] ) ) ;

iPARK_F_FUNC(&ipark1 ) ;

V_alpha = ipark1 . alpha ;

V_beta = ipark1 . beta ;

V_mag = sq r t (V_alpha∗V_alpha + V_beta∗V_beta ) ;

V_ang=atan2 (V_beta , V_alpha ) ;

V_ang=V_ang+twopi ;

i f (V_ang>twopi ) V_ang = V_ang−twopi ;

i f (V_ang>=0.0) Sector = 1 . 0 ;

i f (V_ang>pibythree ) Sector = 2 . 0 ;

i f (V_ang>twopibythree ) Sector = 3 . 0 ;

i f (V_ang>pi ) Sector = 4 . 0 ;

i f (V_ang>fourp iby th r e e ) Sector = 5 . 0 ;

i f (V_ang>f i v ep i by t h r e e ) Sector = 6 . 0 ;

S e c t o r_o f f s e t = pibythree ∗( Sector − 1 . 0 ) ;

alpha = V_ang − Se c t o r_o f f s e t ;

i f (V_dc_ref<=0) V_dc_ref = 1 . 0 ;

onebyvdc = 1/V_dc_ref ;

t_const = sq r t t h r e e ∗V_mag∗onebyvdc ;

ta= t_const ∗( f l o a t ) s i n ( p ibythree−alpha ) ;

i f ( ta >1.0) ta =1.0 ;

tb = t_const ∗( f l o a t ) s i n ( alpha ) ;

i f ( tb >1.0) tb = 1 . 0 ;

taon = 0 .5∗ (1 − ta − tb ) ;

tbon = taon + ta ;

220


tcon = tbon + tb ;

i f ( Sector==1.0)

ModuA = taon ;

ModuB = tbon ;

ModuC = tcon ;

i f ( Sector==2.0)

ModuA =1 − tbon ;

ModuB = taon ;

ModuC = tcon ;

i f ( Sector==3.0)

ModuA = tcon ;

ModuB = taon ;

ModuC = tbon ;

i f ( Sector==4.0)

ModuA = tcon ;

ModuB = 1 − tbon ;

ModuC = taon ;

i f ( Sector==5.0)

ModuA = tbon ;

ModuB = tcon ;

ModuC = taon ;

i f ( Sector==6.0)

ModuA = taon ;

221


ModuB = tcon ;

ModuC = 1 − tbon ;

ModuA = 1 − ModuA;

ModuB = 1 − ModuB;

ModuC = 1 − ModuC;

ModuA = 0.7∗ModuA + 0 . 3 ;

ModuB = 0.7∗ModuB + 0 . 3 ;

ModuC = 0.7∗ModuC + 0 . 3 ;

EPwm1Regs .CMPA. ha l f .CMPA = (ModuA)∗EPwm1Regs .TBPRD; //epwm1A f o r switch A

EPwm2Regs .CMPA. ha l f .CMPA = (ModuB)∗EPwm2Regs .TBPRD; //epwm2A f o r switch B

EPwm3Regs .CMPA. ha l f .CMPA = (ModuC)∗EPwm3Regs .TBPRD; //epwm3A f o r switch C

EPwm1Regs .CMPB = (ModuD)∗EPwm1Regs .TBPRD; //epwm1B f o r switch X

EPwm2Regs .CMPB = (ModuD)∗EPwm2Regs .TBPRD; //epwm2B f o r switch Y

EPwm3Regs .CMPB = (ModuD)∗EPwm3Regs .TBPRD; //epwm3B f o r switch Z

EPwm4Regs .CMPA. ha l f .CMPA = (ModuA)∗EPwm4Regs .TBPRD; //epwm4A f o r switch AX

EPwm5Regs .CMPA. ha l f .CMPA = (ModuB)∗EPwm5Regs .TBPRD; //epwm5A f o r switch BY

EPwm6Regs .CMPA. ha l f .CMPA = (ModuC)∗EPwm6Regs .TBPRD; //epwm6A f o r switch CZ




i n t e r r up t void adc_isr ( void )

// A phase VOLTAGE sens ing

temp0 = (AdcMirror .ADCRESULT0) − V_aoff ;

V_a = temp0∗v_gain_a ;

// B phase VOLTAGE sens ing

temp1 = (AdcMirror .ADCRESULT1) − V_boff ;

V_b = temp1∗v_gain_b ;

222


// C phase VOLTAGE sens ing

temp2 = (AdcMirror .ADCRESULT2) − V_coff ;

V_c = temp2∗v_gain_c ;

// DC l i n k VOLTAGE sens ing

temp6 = (AdcMirror .ADCRESULT6) − V_dcoff ;

V_dc = temp6∗v_gain_dc ;

// Output VOLTAGE sens ing

temp7 = (AdcMirror .ADCRESULT7) − V_ooff ;

temp7 = temp7∗v_gain_o ;

//Third order low pass Butterworth f i l t e r

V_o_x [ 0 ] = temp7 ;

V_o_y [ 0 ] = butt_b [ 0 ] ∗V_o_x [ 0 ] + butt_b [ 1 ] ∗V_o_x [ 1 ] + butt_b [ 2 ] ∗V_o_x [ 2 ]

− butt_a [ 1 ] ∗V_o_y [ 1 ] − butt_a [ 2 ] ∗V_o_y [ 2 ] ;

V_o = V_o_y [ 0 ] ;

V_o_x [ 2 ] = V_o_x [ 1 ] ; V_o_x [ 1 ] = V_o_x [ 0 ] ;

V_o_y [ 2 ] = V_o_y [ 1 ] ; V_o_y [ 1 ] = V_o_y [ 0 ] ;

// A phase CURRENT sens ing


I_a = temp3∗ curr_gain ;

// B phase CURRENT sens ing


I_b = temp4∗ curr_gain ;

// C phase CURRENT sens ing


I_c = temp5∗ curr_gain ;

// R e i n i t i a l i z e f o r next ADC sequence

AdcRegs .ADCTRL2. b i t .RST_SEQ1 = 1 ; // Reset SEQ1

AdcRegs .ADCST. b i t . INT_SEQ1_CLR = 1 ; // Clear INT SEQ1 b i t

223


PieCtr lRegs .PIEACK. a l l = PIEACK_GROUP1; // Acknowledge i n t e r r up t to PIE

void I n i t i a l i z e ( void )

I n i t Sy sCt r l ( ) ; // Bas ic Core I n i t from DSP2833x_SysCtrl . c

EALLOW;

SysCtrlRegs .WDCR= 0x00AF ; // Re−enable the watchdog

EDIS ; // 0x00AF to NOT d i s ab l e the Watchdog , P r e s c a l e r = 64

DINT; // Disab le a l l i n t e r r up t s

Gpio_select ( ) ;

Setup_ePWM( ) ;

InitAdc ( ) ;

adc_setup ( ) ;

void Gpio_select ( void )

EALLOW;

GpioCtrlRegs .GPAMUX1. a l l = 0 ; // GPIO15 . . . GPIO0 = General Puropse I /O













224


GpioCtrlRegs .GPAMUX2. a l l = 0 ; // GPIO31 . . . GPIO16 = Gen . Purpose I /O





GpioCtrlRegs .GPADIR. a l l = 0 ; // GPIO0−31 as inputs




GpioCtrlRegs .GPBDIR. a l l = 0 ; // GPIO63−32 as inputs



GpioCtrlRegs .GPCDIR. a l l = 0 ; // GPIO87−64 as inputs

EDIS ;

void Setup_ePWM( void )

//epwm1

//epwm1A f o r switch A & epwm1B f o r switch X






EPwm1Regs .TBPRD = 1500 ; // 100 kHz , TBPRD = 150MHz/100kHz





225






//epwm2

//epwm2A f o r switch B & epwm2B f o r switch Y















//epwm3

//epwm3A f o r switch C & epwm3B f o r switch Z










226







//epwm4

//epwm4A f o r switch AX















//epwm5

//epwm5A f o r switch BY









227








//epwm6

//epwm6A f o r switch CZ















//phase s h i f t

EPwm1Regs .TBCTL. b i t .SYNCOSEL = 1 ; // generate a syncout i f CTR = 0







228











void adc_setup ( void )


AdcRegs .ADCTRL1. b i t .ACQ_PS = 7 ; // 8 x ADCCLK

AdcRegs .ADCTRL1. b i t .SEQ_CASC = 1 ; // cascaded sequencer

AdcRegs .ADCTRL1. b i t .CPS = 0 ; // d iv id e by 1

AdcRegs .ADCTRL1. b i t .CONT_RUN = 0 ; // s i n g l e run mode


AdcRegs .ADCTRL2. b i t .INT_ENA_SEQ1 = 1 ; // enable SEQ1 in t e r r up t

AdcRegs .ADCTRL2. b i t .EPWM_SOCA_SEQ1 = 1 ; // SEQ1 s t a r t from ePWM_SOCA t r i g

AdcRegs .ADCTRL2. b i t .INT_MOD_SEQ1 = 0 ; // i n t e r r up t a f t e r every end o f seq

AdcRegs .ADCTRL3. b i t .ADCCLKPS = 3 ;

AdcRegs .ADCMAXCONV. a l l = 7 ; // 8 conve r s i on s from Sequencer 1

AdcRegs .ADCCHSELSEQ1. b i t .CONV00 = 0 ; // ADCINA0 as 1 s t SEQ1 conv

AdcRegs .ADCCHSELSEQ1. b i t .CONV01 = 1 ; // ADCINA1 as 2nd SEQ1 conv

AdcRegs .ADCCHSELSEQ1. b i t .CONV02 = 2 ; // ADCINA2 as 3 rd SEQ1 conv




229




EPwm2Regs .ETPS. a l l = 0x0100 ; // Conf igure ADC s t a r t by ePWM2

EPwm2Regs .ETSEL. a l l = 0x0F00 ; // Enable SOCA to ADC

//−−−−−−−−−End o f code−−−−−−−−−−

230

List of Publications

Journal

1. Kawsar Ali, Pritam Das and Sanjib Kumar Panda, “A Special Application Crite-

rion of Nine-Switch Converter with Reduced Conduction Loss,” IEEE Transactions

on Industrial Electronics, vol. 65, no. 4, pp. 2853-2862, Apr. 2018.

2. Kawsar Ali, Ravi Kiran Surapaneni, Pritam Das and Sanjib Kumar Panda,

“A SiC MOSFET based Nine-Switch Single-Stage Three-Phase AC-DC Isolated

Converter,” IEEE Transactions on Industrial Electronics, vol. 64, no. 11, pp.

9083-9093, Nov. 2017.

3. Kawsar Ali, Pritam Das and Sanjib Kumar Panda, “Analysis and Design of

APWM Half-Bridge Series Resonant Converter with Magnetizing Current Assisted

ZVS,” IEEE Transactions on Industrial Electronics, vol. 64, no. 3, pp. 1993-2003,

Mar. 2017.

Conference

1. Kawsar Ali, Pritam Das and Sanjib Kumar Panda, “A Special Application Cri-

terion of Nine-Switch Converter with Improved Thermal Performance,” IEEE

APEC, USA, 2017.

2. Kawsar Ali, Sandeep Kolluri, Naga Brahmendra Yadav Gorla, Pritam Das and

Sanjib Kumar Panda, “Design of a Novel APWM Half-Bridge DC-DC Resonant

Converter with Load-Independent Soft-Switching and Reduced Circulating Cur-

rent,” IEEE APEC, USA, 2016.

3. Kawsar Ali, Pritam Das and Sanjib Kumar Panda, “A Nine-Switch Interleaved

Three-Phase AC-DC Single Stage Isolated Converter Implemented with SiC MOS-

FETs,” IEEE INTELEC, Japan, 2015.

231

List of Publications

4. Naga Brahmendra Yadav Gorla, Kawsar Ali, Pritam Das and Sanjib Kumar

Panda, “Analysis of Active Power Decoupling in Single-Phase Rectifier Using Six-

Switch Topology,” IEEE SPEC, New Zealand, 2016.

5. Naga Brahmendra Yadav Gorla, Kawsar Ali, Chia Chew Lin and Sanjib Kumar

Panda, “Improved Utilization of Grid Connected Voltage Source Converters in

Smart Grid through Local VAR Compensation,” IEEE IECON, Japan, 2015.

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HIGH PERFORMANCE THREE PHASE AC/DC CONVERTERS FOR DATA CENTERS 1cm