IPRM 20121

High Performance Substitutional-Gate MOSFETs Using MBE Source-Drain Regrowth and Scaled Gate Oxides

Sanghoon Lee1*, A. D. Carter1, J. J. M. Law1,D. C. Elias1, V. Chobpattana2, Hong Lu2, B. J. Thibeault1, W. Mitchell1, S. Stemmer2, A. C. Gossard2, and M. J.

W. Rodwell1

1ECE and 2Materials DepartmentsUniversity of California, Santa Barbara, CA

2012 Conference on Indium Phosphide and Related MaterialsUCSB, Santa Barbara, CA

08/28/2012

*sanghoon_lee@ece.ucsb.edu

IPRM 20122

Outline Motivation: Why III-V MOSFETs?

Key Design Considerations- Process : Gate-last

- Channel Design : Composite channel

- Gate dielectric

Process Flow Measurement Results

- I-V Characteristics

- Gate leakage and TLM measurement

Conclusion

IPRM 20123

Why III-V MOSFETs in VLSI ?

more transconductance per gate widthmore current→ speedor reduced Vdd → reduced poweror reduced FET widths→ reduced IC size

increased transconductance from:low mass→ high velocitieslower density of states→ less scatteringhigher mobility in N+ regions → lower access resistance

Other advantagesstrong heterojunctions→ carrier confinementwide range of available materialsepitaxy→ atomic layer control

IPRM 20124

Key Design Considerations

Gate Dielectric:Thinner EOT : scaled high-k dielectric Low Dit : surface passivation6), reduced damage process7)

Channel Design:Thinner wavefunction depth: Thin channel, less pulse doping.More density of state: L-vally transport channel4)

Higher injection velocity: high In-content channel 5)

Process: Scalability (~10 nm-Lg,<30 nm contact pitch) : self-aligned S/D, very low ρc 2) Carrier supply: heavily doped N+ source region3)

Shallow junction: regrown S/D3) or Trench-gate

1) M. Wistey et al. EMC 2009; 2) A. Baraskar et al. IPRM 2010 ; 3) U. Singisetti et at. EDL 2009 ; 4) M. Rodwell et at., DRC 20105) S. Lee et al. EDL 2012 (accepted); 6) A. Carter et at. APEX 2011; 7) G. Burek, et al, JVST 2011.

IPRM 20125

Process : Why Gate-Last process?

Gate-First Fully self-aligned transistor at nm dimensions

Process damage during gate stack definition

Large ungated region: High pulse doing Large leakage current and Decrease Cdepth

Gate-LastLow-damage process: Thermal gate metal, No Plasma process after gate dielectric deposition

Rapid turn-around rapid learning.

A. Carter et at., DRC 2011

IPRM 20126

Channel Design: Composite Channel

Average In-content high → Source-to-channel hetero-barrier suppressed

Mean depth of wave function → reduce surface scattering

Lower bound state m* → higher injection velocity

S. Lee et al. EDL 2012

IPRM 20127

Gate Dielectric : Dit Passivation

A. Carter et al., APEX 2012

Cyclic hydrogen plasma / TMA treatments before dielectric growth 50 cycle (~5 nm Al2O3) growth, 400oC anneal, Ni metallization

“False inversion”

A. Carter et al., APEX 2012

IPRM 20128

Gate Dielectric : Dielectric Scaling

Courtesy of Gift in Stemmer’s Group

Using H2+TMA+H2 treatment and Al2O3/HfO2 bilayer

~40% Thinner EOT with similar dispersion

3.3/1.5 nmAl2O3/HfO2

1.65 nm EOT

1.1/4.0 nmAl2O3/HfO2

1.15 nm EOT

IPRM 20129

1.1/4.0 nm Al2O3/HfO2(Experimental) 1.15 nm EOT

Gate Dielectric : Calculation for Dielectric scaling

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.20.40.60.81.01.21.41.61.82.02.2

Norm

aliz

ed I d/W

g

Equivalent Oxide Thickness ( nm )

Dit (/cm2) 1e12 5e12 10e12

3.3/1.5 nm Al2O3/HfO2(Control) 1.65 nm EOT

Assuming Ballistic FETs in the limit of degenerate carrier concentrations.

Given a 7.5 nm channel, reducing 1.65 nm to 1.15 nm EOT

→ ~25% increase in Id/Wg

IPRM 201210

Process Flow

Channel

Al2O3/HfO2

BarrierSubstrate

N+ S/D

Strip dummy gate Deposit dielectricAneal

Channel

SiO2

BarrierSubstrate

N+ S/D

Regrow source/drain

Channel

Ni

BarrierSubstrate

N+ S/D

Lift-off gate metal

Channel

Ni

BarrierSubstrate

N+ S/D

Ti/Pd/Au

DepositS/D contacts

Channel

SiO2

BarrierSubstrate

Pattern Dummy gate

Channel

SiO2

BarrierSubstrate

Deposit SiO2 as a dummy gate

Channel

SiO2

BarrierSubstrate

N+ S/D

Planarize amorphousInAs on dummy gates

IPRM 201211

-1.0 -0.5 0.0 0.5 1.00.0

0.2

0.4

0.6

0.8

1.0

1.2VDS = 0.1 V to 0.7 V 0.2 V increment

Gm

(mS/m

)Cu

rren

t Den

sity

(mA/

m)

Gate Bias (V)0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.0 mS/µm at Vds = 0.5 V : ~40% increase in transconductance.

0.8 mA/um at Vgs-Vth =0.8 V and Vds=0.5V : ~25% increase in on-current.

Experimental : 1.1 nm Al2O3 / 4.0 nm HfO2 (1.15 nm EOT) , 50 nm-Lg (as drawn)

Control : 3.3 nm Al2O3 / 1.5 nm HfO2 (1.65 nm EOT), 50 nm-Lg (as drawn)

Measurement : I-V Curves for 50 nm-Lg devices

0.0 0.2 0.4 0.6 0.8 1.00.00.20.40.60.81.01.21.41.61.8

VGS = 0 V to 1.4 V 0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)-1.0 -0.5 0.0 0.5 1.010-5

10-4

10-3

10-2

10-1

100

101

VDS = 0.1 V to 0.7 V 0.2 V increment

SS=~200 mV/dec at VDS=0.1VCu

rren

t Den

sity

(mA/

m)

Gate Bias (V)

0.0 0.2 0.4 0.6 0.8 1.00.00.20.40.60.81.01.21.41.61.8

VGS = 0 V to 1.4 V 0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)-1.0 -0.5 0.0 0.5 1.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2VDS = 0.1 V to 0.7 V 0.2 V increment

Gm

(mS/m

)Cu

rren

t Den

sity

(mA/

m)

Gate Bias (V)0.0

0.2

0.4

0.6

0.8

1.0

1.2

-1.0 -0.5 0.0 0.5 1.010-5

10-4

10-3

10-2

10-1

100

101

VDS = 0.1 V to 0.7 V 0.2 V increment

SS=~200 mV/dec at VDS=0.1VCu

rren

t Den

sity

(mA/

m)

Gate Bias (V)

IPRM 201212

-1.0 -0.5 0.0 0.5 1.00.00.10.20.30.40.50.60.70.8

VDS = 0.1 V to 0.7 V 0.2 V increment

Gm

(mS/m

)Cu

rren

t Den

sity

(mA/

m)

Gate Bias (V)0.00.10.20.30.40.50.60.70.8

~130 mV/dec SS for 1.15 nm EOT device : Dit and back-barrier leakage

Experimental : 1.1 nm Al2O3 / 4.0 nm HfO2 (1.15 nm EOT), 200 nm-Lg (as drawn)

Control : 3.3 nm Al2O3 / 1.5 nm HfO2 (1.65 nm EOT) , 200 nm-Lg (as drawn)

Measurement : I-V Curves for 200 nm-Lg devices

0.0 0.2 0.4 0.6 0.8 1.00.00.10.20.30.40.50.60.70.8

VGS = 0 V to 1.4 V 0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)-1.0 -0.5 0.0 0.5 1.010-5

10-4

10-3

10-2

10-1

100

101

VDS = 0.1 V to 0.7 V 0.2 V increment

SS=~130 mV/dec at VDS=0.1V

Curr

ent D

ensi

ty (m

A/m

)Gate Bias (V)

0.0 0.2 0.4 0.6 0.8 1.00.00.10.20.30.40.50.60.70.8

VGS = 0 V to 1.4 V 0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)-1.0 -0.5 0.0 0.5 1.0

0.00.10.20.30.40.50.60.70.8

VDS = 0.1 V to 0.7 V 0.2 V increment

Gm

(mS/m

)Cu

rren

t Den

sity

(mA/

m)

Gate Bias (V)0.00.10.20.30.40.50.60.70.8

-1.0 -0.5 0.0 0.5 1.010-5

10-4

10-3

10-2

10-1

100

101

VDS = 0.1 V to 0.7 V 0.2 V increment

SS=~165 mV/dec at VDS=0.1VCu

rren

t Den

sity

(mA/

m)

Gate Bias (V)

IPRM 201213

Measurement : Gate leakage and TLM measurement

0 5 10 15 20 250

100

200

300

400

500

Gap (m)

Resi

stan

ce (O

hm*

m)

Y = 7.6 + 17.9 * Xc = 0.8 m2

Rsh = 17.9 /sq.

Smaller gate leakage in 1.15 nm EOT device : slightly thick

For both cases, gate leakage <10 nA/µm at all bias range

~1.0 Ohm-µm2 metal-semiconductor contact resistivity

~20 Ohm of sheet resistance

-1.0 -0.5 0.0 0.5 1.01E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8 3.3/1.5 nm Al

2O

3/HfO

2

1.1/4.0 nm Al2O

3/HfO

2

Gat

e le

akag

e Cu

rren

t (A/

m)

Gate Voltage (V)

VDS = 0.5 V50 nm Lg (as drawn)

IPRM 201214

Conclusion

Developed Gate-last MOSFETs using MBE S/D regrowth

Decreasing EOT gives better performance with lower leakage

gm = ~ 1.0 mS/μm at Vds=0.5 V for a 50 nm-Lg device

Jd = 0.8 mA/μm at Vgs-Vth =0.8 V and Vds=0.5 V for a 50 nm-Lg device

Future work: Thinner dielectric, Dit passivation, and S/D leakage current

IPRM 201215*sanghoon_lee@ece.ucsb.edu

Thanks for your attention!Questions?

This research was supported by the SRC Non-classical CMOS Research Center (Task 1437.006). A portion of this work was done in the UCSB nanofabrication facility, part of NSF funded NNIN network and MRL Central Facilities supported by the MRSEC Program of the NSF under award No. MR05-20415.

IPRM 201216

Backup Slide

IPRM 201217

Device Physics : Ballistic transport

CoxCdep Cdos

CDit

Ef

Ewell

Ns

2DEG electron density

Injection velocity

Density of state capacitance

Wavefunction depth C

Efermi-Ewell#1Surface potential

2/3)(/ thgs VVKWI gd 2/1))(2/3(/ thgsm VVKWg g

In the limit of degenerate carrier concentrations

( Here, K is a function of m*, channel and dielectric thickness, and D it )

injsgd NqWI /