IKC Showcase

High performance, solution-processed organic transistor circuits

Henning Sirringhaus

Organic transistors – Introduction

• Performance enhancement from exploration of SC H

SiR3 R=iPr

• Performance enhancement from exploration of

rich organic materials chemistry & better

understanding of charge transport physics -

S

CnH2n+1H2n+1Cn

Cn- BTBT

S

S

CnH2n+1H2n+1Cn

SiR3 R=Et

SiR3

TIPS-pentacene

S

S S

S

HMTTF

understanding of charge transport physics

Tuning of molecular structure to optimise functionCn- DNTT

Si

S

SiR3

TMTES-pentacene

N

N

NNN

N N

N

OS

S S

• Naturally abundant, sustainable elements Si

diF-TESADT

S

SFF

TiOPc

S

S

S

DTBDT

S

R

S S

• Inherently low-temperature and flexible materialsS

SS

R

nPBTTT

S

S

N

S S

C8H17

C8H17

O

BDT-BT

S S S S

nC12H25 C12H25

N

SS

NS

SSS

n

C12H25

C12H25

C12H25

C12H25

• Compatibility with large-area, solution-processing

and printing CDT-BTZ

S S

NS

NC16H33 C16H33

n

DPP-TT-T

N S

C8H17

C8H17

O nPQTBTz-C12

RN

SS

OC12H25OO

n

S

S

N

S

S

C12H25C12H25

C8H17

n

PHBT12 C12H25ODTP-BT

Organic transistors – Advances in performance

T = 150° C

• Recent demonstration that both with soluble molecular crystals and solution-processible polymers mobilities > 1-10

2/V hi blMcCulloch, Kronemeijer, et al. (2012)

= 2-4 cm2/Vscm2/Vs are achievable.

S

SCnH2n+1H2n+1Cn

Cn- BTBT

Ong, Liu et al. (2012)

= 3-10 cm2/Vs

Organic transistors – Mechanical flexibility

• Organic materials exhibit excellent gmechanical flexibility – better than ITO.

• Demonstration of functioning transistor 100circuits down to 100 m.

• Might in the future enable foldable electronics/displays ?electronics/displays ?

Sekitani et al., Nat. Mat. 9, 1015 (2010)Plastic Logic ( )

CIKC projects in organic circuits

• CIKC has enabled us to translate experience in high performance discrete organic FETs to addressing challenges in system integration:challenges in system integration:

• Printed device architectures for high performance and high yield

• Integration of high performance OFET circuits

• Functional integration (sensors, displays, power)Functional integration (sensors, displays, power)

P j t f ll d ti f CIKC ith ll• Projects run over full duration of CIKC with a small, focussed team.

Demonstration of complex OTFT logic circuits

• Circuit applications of OTFT technology: pp gyRFID, integrated sensors, display driver circuits

• Demonstration of 128 bit, anti-collision standard compatible RFID tag with 2 kb/s

• Demonstration of an 8-bit microprocessor; similar to Intel 4004 (1971), 2000 x slower (40 operations/s with pentacene = 0.15 cm2/Vs)

• P-type only, unipolar logic – Need for complementary integration to improve noise margin

Myny et al, IMEC/Holstmargin

Complementary logic circuits

Highly integrated circuits require high CMOS inverter• Highly integrated circuits require high gain and noise margin.

n-type• Complementary logic based on

combining p-type and n-type TFTs: Good gain and noise margin, low power

n type

p-type

consumption.

• Increasing range of high mobility n-type

G. Gelinck, et al., Adv. Mat., Vol. 22 (2010)

Increasing range of high mobility n type organic TFTs available.

B t I d l it i• But: Increased complexity in process integration

Ambipolar logic circuits

CMOS inverter Ambipolar inverter

• Ambipolar logic requires only one type of TFT capable of both n-type and p-t ti E f f t

p

n-typetype operation – Ease of manufacture

• Good gain and noise margin, power

n type

p-type

g g , pconsumption not as low as CMOS

But: No high mobility ambipolar• But: No high mobility ambipolar semiconductors available

G Gelinck et al Adv Mat Vol 22 (2010)G. Gelinck, et al., Adv. Mat., Vol. 22 (2010)

Diketopyrrolopyrrole copolymers - DPPT-TT

Z Chen et alZ. Chen, et al. Adv. Mat. 24, 647 (2012)

PMMA

• Balanced electron and hole mobilities (e = 1 9 cm2/Vs h = 1 2 cm2/Vs)1.9 cm /Vs, h 1.2 cm /Vs)

PSeDPPBT: a narrow bandgap ambipolar polymer

Absorption UPS

X S SX= Se, S

Mn/Mw(kDa)

Eg(eV)

Eg (eV) HOMO(eV)

LUMO(eV) 0.3-0.55 eV

LUMOPSeDPPBT

Φau = -4.85 eV ΦPSeDPPBT = -5.6 V

30/69 1.05 1.3 -5.6 -4.3/-4.55 0.75 eV

Eg = 1.05-1.3 eV

HOMOPSeDPPBTPSeDPPBT

High mobility ambipolar PSeDPPBT TFTs

W / L = 1000 / 20 µmDielectric 450 nm thick PMMA

Kronemeijer, Gili, et al., Adv Mat 24 1558 (2012)

• Ambipolar polymer semiconductor with hole mobility μh = 0.46 cm2/Vs and electron mobility μe = 0.84 cm2/Vs

Adv Mat. 24, 1558 (2012)

Capacitance reduction through self-aligned gate

VINVO

Drain interconnect 

DielectricDielectric

Gate interconnect Gate Gate

Source Drain

Gate

Source Source DrainDrainSubstrate

1 µm

VDD

Substrate

Gate

Photosensitive dielectric• Self Aligned Gate provides low

parasitic capacitance, low leakage currents and improved reliability

UV light

currents and improved reliability

g

Capacitance reduction through self-aligned gate

VINVO

D i i

On-chip capacitance measurements:Overlap capacitance reduction by a factor of 6

Drain interconnect 

DielectricDielectric

Gate interconnect Gate Gate

90

factor of 6Source Source DrainDrain

VDD

Substrate

60

70

80

DD

20

30

40

50

C [pF]

PEN ‐Without SAGPEN ‐With SAGGlass ‐With SAG

0

10

20

100000 200000 300000 400000 500000 600000Area [µm2]ea [µ ]

PSeDPPBT FETs with self-aligned gate

Source-drain: Au, photolithography (L=5m)VIN

VO

Drain interconnect 

Gate interconnect G t

V 10 20 30 V V 10 20 30 V

p g p y ( )Gate dielectric: 150 nm PMMAGate interconnects: Inkjet printed Ag

Source Source Drain

Dielectric

Drain

VDD

Substrate

Dielectric

Gate Gate

VD = 10, 20, 30 V VD = -10, -20, -30 V

• Undegraded performance, mobility unchanged• Very low gate leakage due to self-aligned gatey g g g g

PSeDPPBT, self-aligned gate ambipolar inverters

300 µmµ

Gain ≈ 50Noise margin

3.25 V at VDD = 10V DD(65% of 0.5 VDD)5.75 V at VDD = 20V (57% of 0.5 VDD)

NOR and NAND gates

8

10

NOR gate

2

4

6

8

V A[V]

NOR gate

00 10 20 30

t [s]

8

10

0

2

4

6

VB[V]

VA VB OR NOR0 0 0 1

00 10 20 30

t [s]

6

8

10

V]

VDD = 10 V

0 1 1 01 0 1 01 1 1 0 0

2

4

6

0 10 20 30

V OUT[V

t [s]

PSeDPPBT, self-aligned gate ambipolar ring oscillators

VOUTVDD

5-stage ring oscillator on PENStage delay = (2*n*f)-1

1 1 mm

Ring oscillator performance

10000.00.6

100.0

1000.0

lay [µs]

Glass ‐ td=150 nm ‐3 stages

Glass ‐ td=150 nm ‐5 stages0.2

0.30.40.5

V OUT[V]

1.0

10.0

Stage de

l 5 stages

Glass ‐ td=70 nm ‐3 stages

PEN ‐ td=150 nm ‐5 stages

00.1

0 1 2 3 4 5 6 7 8 9 10t [µs]

f = 384 kHz

0.110 20 30 40 50 60

VDD [V]100.00

1000.00

Glass ‐ td=150 nm ‐

S = 0.43 µs

1.00

10.00

f [kH

z]

3 stagesGlass ‐ td=150 nm ‐5 stagesGlass ‐ td=70 nm ‐3 stagesPEN d 150

Shortest stage delay reported for ring oscillators using ambipolar

0.01

0.10

10 20 30 40 50 60V [V]

PEN ‐ td=150 nm ‐5 stages

ring oscillators using ambipolar organic semiconductors

VDD [V]

Acknowledgements

• Enrico Gili, Antony Sou, Sungjune Jung

• Auke Kronemeijer, Vincenzo Pecunia – PSeDPPBT

• Guillaume Fichet, Jerome Joimel, Mike Banach - Plastic Logic

• Hugo Bronstein, Munazza Shahid, Martin Heeney, Iain McCulloch - Imperial CollegeCollege

• Funding: EPSRC (CIKC), Plastic Logic, TSB