Solid-State Electronics 88 (2013) 2–8

Contents lists available at SciVerse ScienceDirect

Solid-State Electronics

journal homepage: www.elsevier .com/locate /sse

High mobility CMOS technologies using III–V/Ge channels on Si platform

0038-1101/$ - see front matter � 2013 Elsevier Ltd. All rights reserved.http://dx.doi.org/10.1016/j.sse.2013.04.020

⇑ Corresponding author.E-mail address: takagi@ee.t.u-tokyo.ac.jp (S. Takagi).

S. Takagi a,⇑, S.-H. Kim a, M. Yokoyama a, R. Zhang a, N. Taoka a, Y. Urabe b, T. Yasuda b, H. Yamada c,O. Ichikawa c, N. Fukuhara c, M. Hata c, M. Takenaka a

a Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japanb National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japanc Sumitomo Chemical Co. Ltd., 6 Kitahara, Tsukuba, Ibaraki 300-3294, Japan

a r t i c l e i n f o a b s t r a c t

Article history:Available online 29 April 2013

Keywords:MOSFETMobilityStrainSiGeGeIII–V Semiconductors

MOSFETs using channel materials with high mobility and low effective mass have been regarded asstrongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nmregime. From this viewpoint, attentions have recently been paid to Ge and III–V channels. In this paper,possible solutions for realizing III–V/Ge MOSFETs on the Si platform are presented. The high quality III–Vchannel formation on Si substrates can be realized through direct wafer bonding. The gate stack forma-tion is constructed on a basis of atomic layer deposition (ALD) Al2O3 gate insulators for both InGaAs andGe MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAsand Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

� 2013 Elsevier Ltd. All rights reserved.

1. Introduction

It has been well recognized that new device engineering isindispensable in overcoming difficulties of advanced CMOS andrealizing high performance LSIs under 10 nm regime. Here, thechannel materials with high mobility and, more essentially, loweffective mass, are preferable under quasi-ballistic transport ex-pected in ultra-short channel regime [1]. From this viewpoint,strong attentions have recently been paid to Ge and III–V semicon-ductor channels. Because of extremely high electron mobility andlow electron effective mass of Ge and III–V semiconductors suchas GaAs, InP, InGaAs and InAs and extremely high hole mobilityand low hole effective mass of Ge, Ge and III–V materials are suit-able for high performance CMOS applications. The ITRS 2011 ispredicting that the timeline for introducing Ge and InGaAs chan-nels is set at 2018 [2].

One of the ultimate CMOS structures can be the combination ofIII–V nMOSFETs and Ge pMOSFETs, as shown in Fig. 1 [1,3,4]. Here,MOSFETs using these materials must be fabricated on Si substratesin order to utilize Si CMOS platform, meaning the necessity of theco-integration of III–V/Ge on Si, which is often called heteroge-neous integration. Also, those channels must be ultrathin bodystructures such as ultrathin films, Fin structures or nano-wirestructures, because of the suppression of short channel effects.The gate stacks composed of high k gate insulators and metal gatesare regarded as mandatory for scaled CMOS. The formation of

source/drain (S/D) regions with low resistance and leakage currentis also a critical issue for ultrathin body structure. One promisingstructure is metal S/D, which inherently provides the low S/Dresistance.

Here, one of the most important requirements of III–V/Ge chan-nel MOSFETs on the Si platform is to form these channel materialswith high crystal quality on a large size Si wafer, in order to fullyutilize the present Si CMOS platform and to realize LSIs. This is be-cause the advanced fabrication facilities and LSI design platformare mandatory for realizing highly-integrated systems. As a result,the co-integration of the III–V and Ge channel materials on a Sisubstrate, in other words, the heterogeneous integration, is indis-pensable. Fig. 2 shows a variety of possible applications of III–V/Ge materials on the Si CMOS platform [4]. The CMOS devices usingthose non-Si material channels are corresponding to the so-calledMore Moore approach pursuing for higher current drive. Thereare currently many possibilities in the CMOS configuration. III–Vn-MOSFET and Ge p-MOSFET can be combined with strained-Si de-vices, aggressively developed so far. Also, if high performance Ge n-MOSFET or III–V p-MOSFET are realized, Ge CMOS or III–V CMOS isalso viable in terms of the simplicity of the channel structures.Also, one of the ultimate CMOS structure can be a combination ofIII–V channel n-MOSFET and Ge channel p-MOSFET [3], as pro-posed in Fig. 1. Which device structures will be adopted is stronglydependent on the progress in the device technologies of each MOS-FET and the integration technologies and, finally, on the balancebetween the performance merit and the fabrication cost.

This heterogeneous integration is, on the other hand, expectedto create novel LSIs or SoC utilizing a variety of device families

III-V-OI nMOSFET

Si sub.

Metal GMetal GHigh-k gateinsulator

BOX

MetalS/D

strained GOI pMOSFET

III-V-OI n-FinFET or TriGate n-FET

strained GOI p-FinFETor TriGate p-FET

Si sub.BOX

Fig. 1. Ultimate CMOS device structure composed of III–V nMOSFET and GepMOSFET.

Fig. 2. Possible evolution scenario for III–V/Ge devices on Si platform throughheterogeneous integration.

Fig. 3. Critical issues for realizing III–V/Ge MOSFETs on the Si platform.

S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8 3

along the More-than-Moore and the Beyond-CMOS approaches, inaddition to the More-Moore approach, as seen in Fig. 1. One typicalexample of the beyond CMOS devices is tunneling FETs aiming atultra-low power applications. However, one of the drawbacks ofthe tunneling FETs is the low drive current due to low tunnelingprobability of electron through the band-gap. Since Ge and InGaAshave the lower band-gap than Si, the much higher on-current is ex-pected in tunneling FET using these channel materials [5,6].

Also, Ge and III–V materials are more suitable for optical devicesand ultra high frequency analog devices. In addition to them, avariety of functional devices based on non-Si materials can be inte-grated with Si digital CMOS, leading to new SoCs along the More-than-Moore approach. Possible near-term applications could be (1)integration with optical interconnects by using Ge or III–V opticaldevices like detectors and modulators (2) integration with ultra-fast III–V analog devices. As a result, the heterogeneous integrationcan be expected to yield various and versatile semiconductor chipsand markets. Among these applications, the most fundamental de-vice structure is Ge/III–V MOSFETs on Si substrates.

In order to realize this CMOS structure, however, there are stillmany technological issues to be solved for realizing Ge/III–V MOS-FETs on Si substrates. Fig. 3 summarizes critical issues for realizingIII–V/Ge MOSFETs on the Si platform, which are listed as follows

[3,4]; (1) high quality Ge/III–V film formation on Si substrates (2)gate insulator formation with superior MOS/MIS interface quality(3) low resistivity source/ drain (S/D) formation (4) total CMOSintegration. It should be noted here that the ultrathin body Ge/III–V channels such as extremely-thin-body-on-insulator struc-tures, Fin structures and nano-wire structures are mandatory forapplying Ge/III–V MOSFETs to scaled CMOS in order to suppressshort channel effects (SCEs).

In this paper, we present several possible and viable solutionsfor the above critical issues. First, we give several technologiesfor realizing III–V MOSFETs on Si substrates and present the deviceproperties. Next, we touch on the Ge gate stack technologies,which is one of the critical issues of Ge MOSFETs. Finally, we pres-ent an example of the integration of Ge and III–V MOSFETs on asame wafer through the combination of the developed fabricationtechnologies.

2. III–V mosfet technologies

The high quality III–V channel formation on the Si platform isvery challenging. While there are many approaches in III–V chan-nel formation on Si such as wafer-level hetero-epitaxy [7–9], selec-tive hetero-expitaxy [10–15] and epitaxial transfer [16,17], we arecurrently employing the direct wafer bonding (DWB) process ofInGaAs/InP wafers with Si substrates for fabricating the InGaAs-on-Insulator (InGaAs-OI) substrates [18–29]. ECR-plasma SiO2

[18,19,24] and ALD Al2O3 films [20–23,25–29] have been used asburied-oxide (BOX) layers. We can precisely control the thicknessof the BOX layers, because the bonded SiO2 or Al2O3 layers are usedas BOX layers. Fig. 4a and b shows the schematic fabrication pro-cess of the InGaAs-OI substrates and a cross-sectional transmissionelectron microscope (TEM) micrograph of the bonded interface[23,25], respectively. The 3.2-nm-thick InGaAs-OI layer showsexcellent uniformity with the smooth and abrupt interfaces. Thethickness of the ultrathin BOX layer was approximately 7.7 nm.We could not find any serious damages in the extremely-thin body(ETB) InGaAs-OI layers, indicating that the developed DWB processis suitable for fabricating the high quality extremely-thin body III–V-OI on Si wafers, which is effective in suppressing SCEs. Also, theultrathin BOX allows us to utilize the freedom of the thresholdvoltage control by back bias and impurity doping in Si substratesand to easily integrate III–V-OI devices with Si ones.

We have succeeded in fabricating the InGaAs-OI n-MOSFETswith InGaAs thickness of 100 nm under front-gate configuration[23,25]. The S/D regions were formed by standard Si ion implanta-tion. Fig. 5a shows the effective mobility of InGaAs-OI MOSFETs

(a)

(b)

Fig. 4. (a) Fabrication process of InGaAs-OI substrates (b) cross-sectional TEMmicrograph of 3.2-nm-thick extremely-thin body (ETB) InGaAs-OI on Si wafer witha 7.7-nm-thick ultrathin buried oxide (UTBOX) layer.

4 S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8

with InGaAs thickness of 100 nm in comparison with those ofMOSFETs on bulk p-InGaAs and p-Si substrates. We have foundthe maximum electron mobility of �3000 and �2000 cm2/Vs fori- and p-InGaAs-OI, respectively [21,22]. Also, ETB (3.5 and 9 nm)InGaAs-OI MOSFETs on Si substrates with Al2O3 ultrathin BOX lay-ers have been fabricated [23,25]. Fig. 5b shows ID–VG characteris-tics of the 3.5-nm-thick ETB InGaAs-OI MOSFETs with donorconcentration of 1017 cm�3 under the double-gate operation. TheIon/Ioff ratio, defined by the ratio of the highest- and the lowest-cur-rent, and S factor are estimated to be approximately 107 and150 mV/dec, respectively. Also, Ioff as low as 0.1 pA/lm wasrealized.

As for the performance of III–V-OI MOSFETs, on the other hand,an important issue is the mobility reduction in thinner III–V-OIchannel thickness. This problem can be more serious in III–V chan-nels than in Si and Ge ones, because much lighter electron effective

400

600

8001000

3000

1012 101

Effe

ctiv

e M

obili

ty, µ

eff (c

m2 /V

s)

Surface Carrier Density, Ns (/cm2)

i-InGaAs-OIp-InGaAs-OIp-InGaAs bulk

Si nMOSFET N

D=4x1015 cm-3

4.6x

2.5x

3.0x

(a)

Fig. 5. (a) Effective mobility of InGaAs-OI MOSFETs with InGaAs thickness of 100 nm anconcentration of 1017 cm�3.

mass of III–V channels lead to thicker inversion layer thickness [1],which causes the mobility reduction by channel thickness fluctua-tion in a much thicker channel range [23,30]. In order to improvethis mobility reduction in thinner InGaAs-OI channels, we haveintroduced composite channel structures with MOS interface buf-fers, which are composed of a thin In-rich channel layer sand-wiched by lower In content buffer layers [26,28,29]. Highelectron mobility of 3180 cm2/Vs has been obtained for a 3-nm-thick InAs channel sandwiched by 3-nm thick In0.3Ga0.7As buffers[28]. However, the uniform channel formation and smooth MOSinterfaces are still critical issues for maximizing the current drivein ETB III–V channel structures.

Another concern in the high performance III–V MOSFETs is lowresistivity S/D formation, which becomes more important for ETBchannels. We would consider that metal S/D scheme can be thebest solution for III–V MOSFETs and also III–V/Ge CMOS integrationfrom the viewpoint of Fermi level pinning positions of metals onIII–V and Ge [31] as well as minimizing parasitic resistance includ-ing S/D sheet resistance and contact resistance. Here, the formationof metal S/D strongly requires the self-aligned formation processlike silicide S/D in Si CMOS processes, which is mandatory for dee-ply scaled MOSFETs. Recently, we have found that a Ni-InGaAs al-loy formed by direct reaction of Ni and InGaA is one of thematerials allowing us to fabricated self-aligned metal S/D struc-tures for InGaAs MOSFETs [26–29,32,33]. Ni-InGaAs alloy layersexhibited low sheet resistance of around 25 X/square, which islower by 1/3 than that of InGaAs layers doped with n-type impuri-ties up to the solid solubility (�80 X/square). In addition, we havefound that Ni can be selectively etched by HCl solution withoutetching the Ni-InGaAs alloy, allowing us to employ the salicide-likeself-aligned metal S/D formation process. Also, InxGa1�xAs withhigher Indium content, x, is expected to provide lower Schottkybarrier height (SBH) or ideally no barrier, because of the lower con-duction band minima with higher Indium contents [34]. The sche-matic diagram of SBH in InGaAs and the experimental results ofSBH between Ni-InGaAs and InGaAs as a function of the Indiumcontent are shown in Fig. 6a and b, respectively. We have con-firmed that SBH of almost 0 eV is obtained at Indium content of0.7 and 0.8, indicating that the SBH engineering utilizing InGaAschannels with higher Indium contents is promising [26–29].

We have employed this technique to ultrathin body InGaAs/InAs-OI channels [26–29], for which metal S/D is mandatory. Theschematic fabrication flow and TEM photographs of the Ni-InGaAs

10-1410-1310-1210-1110-1010-910-810-710-610-510-4

-3 -2 -1 0 1 2 3

Dra

in C

urre

nt, I

D (A/µµ

m)

Gate Voltage, VG (V)

dInGaAs

~ 3.5 nm1 V

0.01 V

Ion

/Ioff

~ 107

150 mV/dec

ID

IS

3

(b)

d (b) ID–VG curves of a 3.5-nm-thick ETB InGaAs-OI nMOSFET with donor impurity

0

0.1

0.2

0.3

0.4

0.3 0.4 0.5 0.6 0.7 0.8 0.9

Barri

er h

eigh

t for

ele

ctro

n [e

V]

Indium content

As-deposited

RTA at 250oC for 1min

(a) (b)

Fig. 6. (a) Schematic diagram of Schottky barrier height of InGaAs as a function of indium content (b) Schottky barrier height of Ni-InGaAs alloy/n-InxGa1�xAs diodes with andwithout RTA at 250 �C for 1 min as a function of Indium content, x.

Ta

Si

Ni for S/D Ni-InGaAs

In0.7Ga0.3AsTa

Si

In0.7Ga0.3AsTa

Si

(a)

(b)Fig. 7. (a) Fabrication process of self-aligned InGaAs-OI MOSFETs with metal S/Dstructure using Ni-InGaAs alloy (b) a cross-sectional TEM image of fabricatedIn0.7Ga0.3As-OI MOSFETs with a MOS interface buffer layer with body thickness of 2/5/3 nm (In0.3Ga0.7As/In0.7Ga0.3As/In0.3Ga0.7As).

S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8 5

S/D InGaAs-OI channels with the MOS buffer layers are shown inFig. 7a and b, respectively. We have confirmed excellent perfor-mance of the ETB MOSFET with channel thickness down to 3 nm,

1010

1011

1012

1013450

Energy(eV)

Inte

rface

trap

den

sity

(eV

—1cm

—2)

550

500

Ev Midgap

575

Ec

2

—0.2 0 0.2

((a)

Fig. 8. (a) Oxidation temperature dependency of the energy distribution of the interface s(100) Ge n-MOSFET. The (100) Si electron mobility is also shown.

because of low resistance and low thermal budget Ni-InGaAs metalS/D.

3. Ge gate stack technologies

Among a variety of gate insulators and/or interface control lay-ers on Ge, attention has recently been paid more to GeO2/Ge inter-faces [35–50], because of the superior interface properties. Wehave already shown that GeO2/Ge interfaces with a quite low inter-face state density (Dit) can be realized by direct thermal oxidationof Ge substrates [36,41–44,47,49]. Fig. 8a shows the energy distri-bution of the interface state density of GeO2/Ge interfaces as aparameter of oxidation temperature. It is found that minimumDit values of 1011 eV�1 cm�2 or less can be obtained without anyinterface passivation annealing and that the almost symmetric U-shape distribution is promising for both n- and p-MOSFET applica-tions. As a result, that thermal oxide GeO2, leading to low Dit, canbe one of the most promising interfacial control layers. Actually,high electron and hole mobility of Ge n- [44,47] and p-channelMOSFETs [42,49], respectively, have already been realized withthe GeO2/Ge interfaces fabricated by thermal oxidation. Fig. 6bshows one example of the effective electron mobility of GeO2/Gen-MOSFETs. The peak electron mobility of as high as 1020 cm2/

0

200

400

600

800

1000

1200

0 1x1012 2x1012 3x1012 4x1012

Elec

tron

Mob

ility

(cm

/Vs)

Ns (cm-2)

(100) Si electron mobilityNsub.= 8x1015cm-2

Nsub.= 1x1016cm-2

x1.4

01x1012 2x1012 3x1012 4x1012

(100) Si electron mobilityNsub.= 8x1015cm-2

Ge nMOSFETstNsub.= 1x1016cm-2

x1.4

(100) surface

b)

tate density of GeO2/Ge interfaces (b) Electron mobility versus Ns characteristics in a

Ge

Al2O3

O2O2

O2

ECRplasma

GeOx

Ge

Al2O3

Al2O3 ALD on Ge

GeOx formation by post plasma oxidation

Fig. 9. Novel Al2O3/GeOx/Ge gate stack formation process by using oxygen plasmathrough a thin ALD Al2O3 layer.

6 S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8

V s was achieved, corresponding to the 1.4 time enhancementagainst the (100) Si n-MOSFET mobility [47]. Also, high hole effec-tive mobility of 575 cm2/V s has also been obtained for GeO2/Ge p-MOSFETs [49]. These high mobilities are attributed to the GeO2/GeMOS interface with low Dit.

On the other hand, the interfaces used in these MOSFETs havestill employed thick GeO2 layers. Thus, the combination of high kand ultrathin Ge oxide inter layers (ILs) is preferable from theviewpoints of both thin equivalent oxide thickness (EOT) and lowDit. Therefore, we have proposed a novel IL formation process

0

1

2

3

650 W, 10 s

Vg (V)

C (µ

F/cm

2 )

1M 500k 100k 10kHz

EOT=1.09 nm

1 nm Al2O3

(100) p-Ge

-2 -1 0 1

((a)

Fig. 10. C–V characteristics of Au/Al2O3/GeOx/p-

11-2

-1

-0.3 0.0 0.31010

1011

1012

1013

EV EC

Dit (

cm-2

eV-1)

Energy (eV)

Al2O3/Ge

Postoxidation

650 W, 10 s(a) (b

Fig. 11. (a) Dit distribution along with energy in the band gap, obtained using Au/Al2O3/G0.2 eV than the midgap as a function of IL GeOx thickness for Al2O3/GeOx/Ge MOS interf

employing ECR oxygen plasma to form GeOx ILs through a thinhigh-k dielectric layer, aiming at realizing low Dit and thin EOT atthe same time [51–54]. The basic process flow is shown in Fig. 9.Here, plasma post oxidation forms a thin GeOx IL by oxidizing aGe surface beneath an ALD Al2O3 layer using ECR oxygen plasmaexposure. In this process, the Al2O3 layer serves as a protectinglayer to prevent subsequent damage to GeOx IL and also as a suffi-cient oxygen barrier that suppresses the growth of unnecessarilythick GeOx IL.

Ultrathin EOT Al2O3/GeOx/Ge gate stacks with superior GeOx/GeMOS interfaces have been fabricated by this method. Fig. 10a and bshows the C–Vg characteristics of Au/Al2O3/GeOx/p- and n-Ge MOScapacitors with EOT of 1.1 nm, respectively, at room temperature,fabricated by post plasma oxidation for 10 s through 1 nm Al2O3.The excellent C–Vg characteristics with small frequency dispersionhave been obtained. Fig. 11a shows the energy distribution of Dit

for Au/Al2O3/GeOx/Ge MOS capacitors on p- and n-Ge substrates.It is found that post oxidation significantly reduces Dit down toless than 1011 eV�1 cm�2, quite similar to the GeO2/Ge MOS inter-faces fabricated by thermal oxidation, for both n- and p-Ge sub-strates. Fig. 11b shows Dit at the energy level higher by 0.2 eVthan the midgap as a function of the IL GeOx thickness for Al2O3/GeOx/Ge MOS interfaces with different oxidation conditions. It isconfirmed that precise GeOx thickness control can be realized bypost plasma oxidation through Al2O3. We have found that there

-1 0 1 20

1

2

3

C (µ

F/cm

2 )

Vg (V)

650 W, 10 s 1M 500k 100k 10kHz

EOT=1.14 nm

1 nm Al2O3

(100) n-Ge

b)

and n-Ge gate stacks at room temperature.

0

5

10

150.0 0.3 0.6 0.9

EOT (nm)

650 W 500 W 300 W

Dit (

10 c

meV

)

GeOx thickness (nm)

Fixed Al2O3

(1.3 nm), 500 W

@Ei-0.2 eV

0.0 0.5 1.0 1.5

)

eOx/Ge MOS capacitors on p- and n-Ge substrates (b) Dit at the energy level higher byaces.

10-3

10-2

10-1

100

Vd=-0.05 V Vd=-0.2 V

I d ( µA/

µm)

Vg (V)

EOT=0.98 nm

W/L=120 µm/50 µm

-1.2 -0.8 -0.4 0.0 0.8 1.0 1.20

200

400

600

J. Mitard, et al.VLSI, 2009

R. Xie, et al.IEDM, 2008.

Hol

e m

obilit

y (c

m2 /V

s)

EOT (nm)

Y. Kamata, et al.VLSI, 2009.

This work (100) (110) (111)

(a) (b)

Fig. 12. (a) Id–Vg of Ge p-MOSFETs with an Al2O3/GeOx/Ge gate stack having an EOT of 0.98 nm on (100) Ge. (b) Peak hole mobility of Ge p-MOSFETs with Al2O3/GeOx/Ge gatestacks as a function of EOT.

Al2O3

InGaAsAl2O3

TaAl2O3

Ta

Ge(100)Ni-Ge Ni-Ge

Ni-InGaAsNi-InGaAs

Ge pMOSFET InGaAs nMOSFET

Ta Gate

Ni-Ge S/D Ni-InGaAs S/D5 µµm

sAaGnIrefaweGlayer

Fig. 13. Schematic view of fabricated CMOS structure of InGaAs-OI n-MOSFET andGe p-MOSFET and a photograph of the top view.

-6

-3

00

6

12

-2 -1 0 1 2

ID (mA

/mm

)I D (mA

/mm

)

VD (V)

-0.5 V-1 V

-1.5 V

-2 V

Ge pMOSFET InGaAs n MOSFET2 V

1.5 V

1 V

0.5 V

0 V

W/L = 100/50 µµm

Fig. 14. ID–VD characteristics of a Ge p-MOSFET and a 20-nm-thick InGaAs-OI n-MOSFET.

S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8 7

is a universal relationship between the Dit at GeOx/Ge interface andthe GeOx thickness and that 0.5-nm-thick GeOx (0.35 nm EOT) issufficient to suppress Dit.

The Ge n- and p-MOSFETs using the Al2O3/GeOx/Ge gate stacksare fabricated on (100), (110) and (111) Ge [52–54]. Fig. 12ashows Id–Vg characteristics of Ge p-MOSFETs with Al2O3/GeOx/Gegate stacks having EOT of 0.98 nm on (100) Ge. The fabricatedGe n- and p-MOSFETs with sub-nm EOT have been realized withrecord high mobilities of 937 cm2/V s and 526 cm2/V s at �1 nm,respectively, indicating that the excellent Al2O3/GeOx/Ge interfacescan contribute to high mobility. Fig. 12b shows the peak holemobility of p-Ge MOSFETs with Al2O3/GeOx/Ge gate stacks as afunction of EOT. Although the decrease of the hole mobility witha decrease in EOT is observed for the values already reported[55–57], the present MOSFETs with the Al2O3/GeOx gate stacks ex-hibit much weaker degradation of mobility with decreasing EOT,which is attributable to the sufficient passivation of Ge MOS inter-faces with reduced scattering centers.

4. Integration of III–V/Ge mosfets

In order to realize the integration of III–V/Ge MOSFETs, we havebonded III–V substrates with Ge substrates [58,59]. Fig. 13 shows

the schematic view of fabricated CMOS structure of an InGaAs-OIn-MOSFET and a Ge p-MOSFET and a photograph of the top view.As the gate stack, we have employed Al2O3 gate insulators for bothInGaAs and Ge MOSFETs. This is partly because ALD Al2O3 is knownto prove superior interface properties in InGaAs MOS structures. Asthe common S/D structure, we have implemented Ni-based metalS/D technologies for both InGaAs and Ge MOSFETs. Fig. 14 showsthe ID–VD characteristics of a Ge pMOSFET and a 20-nm- thick InG-aAs-OI nMOSFET on a same wafer. The electron and hole mobilityof 1800 and 260 cm2/V s and the mobility enhancement against Siof 3.5� and 2.3� have been demonstrated for InGaAs-OI nMOSFETsand Ge pMOSFETs, respectively. As a result, the successful integra-tion of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same waferhas been demonstrated.

5. Conclusions

CMOS family utilizing III–V/Ge channels on Si substrates can bekey devices for high performance and low power advanced LSIs inthe future. The critical issues and the key technologies for realizingGe/III–V-based channel MOSFETs on the Si platform have been ad-dressed. In this paper, the direct wafer bonding for realizing InG-aAs-OI on Si substrates and the Ni-InGaAs metal S/D for lowresistivity self-align S/D formation have been described for III–VMOSFET technologies. We have also addressed the GeOx /Ge

8 S. Takagi et al. / Solid-State Electronics 88 (2013) 2–8

interface formation technology for simultaneously satisfying lowDit and thin EOT by the ECR post plasma oxidation. Finally, theintegration of InGaAs(-OI) nMOSFETs and Ge pMOSFETs on a Gesubstrate and the device operation have been demonstrated bycombining the above technologies. The developed CMOS fabrica-tion processes can open up a way to realize the ultimate highmobility channel CMOS on the Si platform. As a result, we can con-clude that ultrathin-body-based III–V/Ge MOSFETs on the Si CMOSplatform can be a strong candidate as the device structures underthe 15 nm technology node and beyond.

Acknowledgements

This work was partly supported by Grant-in-Aids for ScientificResearch (No. 18063005 and 23246058) from Ministry of Educa-tion, Culture, Sports, Science and Technology, and Innovation Re-search Project on Nano electronics Materials and Structures andResearch and Development Program for Innovative Energy Effi-ciency Technology from New Energy and Industrial TechnologyDevelopment Organization. The authors would like to thank Prof.M. Sugiyama, Prof. R. Nakane, Y. Nakakita, K. Morii, T. Sasada, H.Matsubara, Dr. T. Hoshii, S.-H. Lee, R. Suzuki and J.-K. Suh in theUniversity of Tokyo, Dr. N. Miyata, T. Maeda, H. Ishii, Dr. H. Takagi,in National Institute of Advanced Industrial Science and Technol-ogy and Dr. A. Ohtake in National Institute for Material Sciencefor their collaborations.

References

[1] Takagi S, Irisawa T, Tezuka T, Numata T, Nakaharai S, Hirashita N, et al. IEEETrans Electron Dev 2008;55:21.

[2] International Technology Roadmap for Semiconductors (ITRS); 2010. <http://www.itrs.net/Links/2010ITRS/Home2010.htm>.

[3] Takagi S, Tezuka T, Irisawa T, Nakaharai S, Numata T, Usuda K, et al. Solid-StateElectron 2007;51:526.

[4] Takagi S, Takenaka M. In: IEEE symp on VLSI technol; 2010. p. 147.[5] Seabaugh AC, Zhang Q. Proc IEEE 2010;98:2095.[6] Iida R, Kim S-H, Yokoyama M, Taoka N, Lee S-H, Takenaka M, et al. J Appl Phys

2011;110:124505.[7] Datta S, Dewey G, Fastenau JM, Hudait MK, Loubychev D, Liu WK, et al. IEEE

Electron Dev Lett 2007;28:685.[8] Radosavljevic M, Chu-Kung B, Corcoran S, Dewey G, Hudait MK, Fastenau JM,

et al. In: Electron device meeting, vol. 319; 2009.[9] Hill RJW, Park C, Barnett J, Price J, Huang J, Goel N, et al. In: IEEE int electron

device meeting, vol. 130; 2010.[10] Wu YQ, Xu M, Ye PD, Cheng Z, Li J, Park J-S, et al. Appl Phys Lett

2008;93:242106.[11] Waldron N, Nguyen ND, Lina D, Brammertz G, Vincent B, Firrincieli A, et al. ECS

Trans 2011;35(3):299–309.[12] Hoshii T, Deura M, Sugiyama M, Nakane R, Sugahara S, Takenaka M, et al. Phys

Status Solidi (c) 2008;5:2733.[13] Deura M, Hoshii T, Takenaka M, Takagi S, Nakano Y, Sugiyama M. J Cryst

Growth 2008;310:4768.[14] Deura M, Hoshii T, Yamamoto T, Ikuhara Y, Takenaka M, Takagi S, et al. Appl

Phys Express 2009;2:011101.[15] Kondo Y, Deura M, Terada Y, Hoshii T, Takenaka M, Takagi S, et al. J Cryst

Growth 2010;312:1348.[16] Ko H, Takei K, Kapadia R, Chuang S, Fang H, Leu PW, et al. Nature

2010;468(7321):286–9.[17] Takita H, Hashimoto N, Nguyen C-T, Kudo M, Akabori M, Suzuki T. Appl Phys

Lett 2010;97:012102.[18] Yokoyama M, Yasuda T, Takagi H, Yamada H, Fukuda N, Hata M, et al. In: IEEE

symp on VLSI technol; 2009. p. 242–3.[19] Yokoyama M, Yasuda T, Takagi H, Yamada H, Fukuhara N, Hata M, et al. Appl

Phys Express 2009;2:124501.

[20] Yokoyama M, Yasuda T, Takagi H, Miyata N, Urabe Y, Ishii H, et al. Appl PhysLett 2010;96:142106.

[21] Yokoyama M, Urabe Y, Yasuda T, Takagi H, Ishii H, Miyata N, et al. In: IEEEsymp on VLSI technol; 2010. p. 235–6.

[22] Urabe Y, Yokoyama M, Takagi H, Yasuda T, Miyata N, Yamada H, et al. ApplPhys Lett 2010;97:253502.

[23] Yokoyama M, Iida R, Kim SH, Taoka N, Urabe Y, Yasuda T, et al. In: IEEE intelectron device meeting; 2010. p. 46–9.

[24] Yokoyama M, Yasuda T, Takagi H, Yamada H, Fukuhara N, Hata M, et al. ApplPhys Exp 2011;4:054202.

[25] Yokoyama M, Iida R, Kim S-H, Taoka N, Urabe Y, Takagi H, et al. IEEE ElectronDev Lett 2011;32:1218–20.

[26] Kim SH, Yokoyama M, Taoka N, Iida R, Lee S, Nakane R, et al. IEEE symp on VLSItechnol; 2011. p. 58–9.

[27] Kim S-H, Yokoyama M, Taoka N, Iida R, Lee S-H, Nakane R, et al. Appl Phys Exp2011;4:114201.

[28] Kim SH, Yokoyama M, Taoka N, Nakane R, Yasuda T, Ichikawa M, et al. In: IEEEint electron device meeting; 2011. p. 311–4.

[29] Kim S-H, Yokoyama M, Taoka N, Iida R, Lee S-H, Nakane R, et al. Appl Phys Exp2012;5:014201.

[30] Uchida K, Takagi S. Appl Phys Lett 2003;82:2916–8.[31] Takagi S. IEDM short course; 2011.[32] Kim SH, Yokoyama M, Taoka N, Iida R, Lee S, Nakane R, et al. In: IEEE int

electron device meeting; 2010. p. 596–9.[33] Kim SH, Yokoyama M, Taoka N, Iida R, Lee S, Nakane R, et al. Appl Phys Exp

2011;4:024201.[34] Wieder HH. J Vac Sci Technol B 2003;21:1915.[35] Fukuda Y, Ueno T, Hirono S, Hashimoto S. Jpn J Appl Phys Part I 2005;44:6981.[36] Takagi S, Maeda T, Taoka N, Nishizawa M, Morita Y, Ikeda K, et al.

Microelectron Eng 2007;84:2314.[37] Delabie A, Bellenger F, Houssa M, Conard T, Elshocht SV, Aymax M, et al. Appl

Phys Lett 2007;91:082904.[38] Takahashi T, Nishimura T, Chen L, Sakata S, Kita K, Toriumi A. In: IEDM tech

dig; 2007. p. 697.[39] Kuzum D, Pethe AJ, Krishnamohan T, Oshima Y, Sun Y, McVittie JP, et al. In:

IEDM tech dig; 2007. p. 723.[40] Kita K, Suzuki S, Nomura H, Takahashi T, Nishimura T, Toriumi A. Jpn J Appl

Phys 2008;47:2349.[41] Matsubara H, Sasada T, Takenaka M, Takagi S. Appl Phys Lett 2008;93:032104.[42] Nakakita Y, Nakane R, Sasada T, Matsubara H, Takenaka M, Takagi S. In: IEEE

int electron device meeting; 2008. p. 877.[43] Sasada T, Nakakita Y, Takenaka M, Takagi S. J Appl Phys 2009;106:073716.[44] Morii K, Iwasaki T, Nakane R, Takenaka M, Takagi S. In: IEEE int electron device

meeting; 2009. p. 681.[45] Lee CH, Nishimura T, Saido N, Nagashio K, Kita K, Toriumi A. In: IEEE int

electron device meeting; 2009. p. 457.[46] Nishimura T, Lee CH, Wang SK, Tabata T, Kita K, Nagashio K, et al. In: IEEE symp

on VLSI technol; 2010. p. 209.[47] Morii K, Iwasaki T, Nakane R, Takenaka M, Takagi S. IEEE Electron Dev Lett

2010;31:1092.[48] Lee CH, Nishimura T, Tabata T, Wang SK, Nagashio K, Kita K, et al. In: IEEE int

electron device meeting; 2010. p. 416.[49] Nakakita Y, Nakakne R, Sasada T, Takenaka M, Takagi S. Jpn J Appl Phys

2011;50:010109.[50] Lee CH, Nishimura T, Nagashio K, Kita K, Toriumi A. IEEE Tran Electron Dev

2011;58:1295.[51] Zhang R, Iwasaki T, Taoka N, Takenaka M, Takagi S. Appl Phys Lett

2011;98:112902.[52] Zhang R, Iwasaki T, Taoka N, Takenaka M, Takagi S. In: IEEE symp on VLSI

technol; 2011. p. 56–7.[53] Zhang R, Taoka N, Huang P, Takenaka M, Takagi S. In: IEEE int electron device

meeting; 2011. p. 642–4.[54] Zhang R, Iwasaki T, Taoka N, Takenaka M, Takagi S. IEEE Trans Electron Dev

2012;59(2):335–41.[55] Xie R, Phung TH, He W, Sun Z, Yu M, Cheng Z, et al. In: Tech dig IEDM; 2008. p.

393–6.[56] Mitard J, Shea C, DeJaeger B, Pristera A, Wang G, Houssa M, et al. In: Tech dig

VLSI symp; 2009. p. 82–3.[57] Kamata Y, Ikeda K, Kamimuta Y, Tezuka T. In: Tech dig VLSI symp; 2009. p.

211–2.[58] Yokoyama M, Kim SH, Zhang R, Taoka N, Urabe Y, Maeda T, et al. In: IEEE symp

on VLSI technol; 2011. p. 60–1.[59] Yokoyama M, Kim S-H, Zhang R, Taoka N, Urabe Y, Maeda T, et al. Appl Phys

Exp; 2012.