High-Efficient Multilevel Half-Bridge Converter

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010 943

High-Efficient Multilevel Half-Bridge ConverterIn-Ho Cho, Student Member, IEEE, Kang-Hyun Yi, Member, IEEE, Kyu-Min Cho, Member, IEEE,

and Gun-Woo Moon, Member, IEEE

Abstract—A new high-efficient multilevel half-bridge converteris proposed in this paper. The proposed converter regulates theoutput voltage by adjusting applied voltage on the main trans-former with an auxiliary circuit while main switches are operatedat both fixed duty ratio and switching frequency. Therefore, nomagnetizing dc offset current exists on the main transformer andall switches can be operated with zero voltage switching condition.Furthermore, multilevel voltage shown at the output filter reducesthe output inductance significantly. To verify these features of theproposed circuit, operational principle and experimental resultswill be presented with the 700 W prototype.

Index Terms—Half-bridge converter, multilevel converter, zerovoltage switching (ZVS).

I. INTRODUCTION

R ECENTLY, the efficiency problem in server power sup-plies has become an important issue because of its elec-

tricity consumption growth and cooling cost increase [1]–[5].Especially, the necessity of a high-efficient server power systemis emphasized in the medium power (600–800 W) supplies sincethe server infrastructure has spread to small companies thesedays. For this purpose, several techniques have been proposedto reduce the switching losses and component stresses [6]–[24].Among the proposed techniques, the conventional phase-shiftedfull-bridge (PSFB) converter [6]–[8], the active-clamp forwardconverter [21], and the asymmetric control half-bridge con-verter [23], [24] are chosen as promising candidates for theirzero voltage switching (ZVS) operation, relatively lower cur-rent stress, and simple configuration. However, the usage of thePSFB converter is limited to medium power supplies since itadopts large number of main switches on the primary side. ThePSFB converter increases the cost and decreases the power den-sity of the converter. The active clamp forward converter hassimple structure, but it is also suffered from high-voltage rat-ing of the main switch. The voltage stress of the active clampforward converter is the highest among three ZVS topologies,which increases the cost and degrades the performance of theconverter. The asymmetric half-bridge converter shown in Fig. 1is the most attractive topology among three different techniquesmentioned earlier. It has simple structure and wide ZVS range.

Manuscript received May 8, 2009; revised July 14, 2009. Current versionpublished April 9, 2010. This paper was presented at the Proceedings of the 6thIEEE International Power Electronics and Motion Control Conference, Wuhan,China, May 17– 20, 2009. Recommended for publication by Associate EditorH. S. H. Chung.

The authors are with the Department of Electrical Engineering, Korea Ad-vanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail:[email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2029549

Fig. 1. Schematic diagram of the conventional asymmetric half-bridgeconverter.

Also, the voltage stress of the switches is clamped at its inputvoltage level. As a result, it has been chosen as the most suitabletopology for the server system in middle power range. However,the asymmetric half-bridge converter also contains followingdrawbacks. The remained dc offset current at the magnetizinginductor decreases the transformer utilization, and the unbal-anced voltage-/current stress degrades the performance of therectifier stage. Furthermore, its nonlinear dc conversion charac-teristic requires higher duty variation for the same input variationcompared to other linear converters. It makes the converter oper-ated beyond the optimum operating point at high-input voltagespecifications.

A number of different techniques have been proposed toovercome the drawbacks of the asymmetric half-bridge con-verter [25]–[27]. Employing an auxiliary transformer has beensuggested [25]. With the auxiliary transformer, the converterextended its nominal duty ratio, but the offset problem of themagnetizing current is still remained in the transformers. As aresult, power density and core utilization are severely deterio-rated in the converter. Duty cycle shifted pulsewidth modulation(PWM) control technique proposed in [26] is very simple andable to eliminate magnetizing current offset of the converter.However, one of the two switches in the converter is still op-erated in hard switching condition, and large ripple current isshown in the rectifier. Adopting an auxiliary switch ON the sec-ondary side of the asymmetric half-bridge converter has beenproposed as another solution [27]. The dc offset of magnetizingcurrent problem could be solved effectively with this solution.

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944 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 4, APRIL 2010

Fig. 2. Schematic diagram of the proposed converter.

However, its nominal duty ratio is still limited, and the controlscheme is difficult to realize.

In order to overcome all these drawbacks, a new high-efficientmultilevel half-bridge converter is proposed, as shown in Fig. 2.The proposed converter employs an auxiliary circuit for the out-put regulation. The auxiliary circuit supplies additional voltageto the main transformer when input voltage decreases. Thus,the main switches can be operated at 50% duty ratio and fixedswitching frequency. Since the main switches are always oper-ated at 50% duty ratio, their ZVS operation is easily achieved,and the transformer is effectively utilized with no dc offset ofthe magnetizing current. Moreover, the ZVS operation of theauxiliary switches is easily realized by output inductor energy,and the doubled switching frequency shown at the output filterreduces the output ripple current significantly.

II. FEATURES OF THE PROPOSED CONVERTER

Fig. 2 shows a circuit diagram of the proposed dc/dc con-verter. It is based on the conventional half-bridge converter,and the auxiliary circuit is employed on the primary side ofthe converter. The auxiliary circuit is composed of an auxiliarytransformer (T2) and two auxiliary switches (S1 and S2). Fig. 3represents the basic operation of the proposed converter. Themain switches are always operated at 50% duty ratio, while theoutput voltage is regulated by controlling the phase differencesDeff between the main switches and auxiliary switches. Whenthe input voltage decreases, Deff is extended and additional volt-age is increased to compensate the decreased input voltage, asshown in Fig. 3. As the auxiliary circuit is used only for the reg-ulation, the magnetic size of the auxiliary transformer is muchsmaller than that of the main transformer, and the core loss inthe auxiliary transformer is negligible at nominal operating con-dition. Also, the current which flows into the auxiliary circuit

Fig. 3. Applied voltages on transformers: (a) at nominal input voltage and(b) at minimum input voltage.

is decreased in proportion with the turn ratio of the auxiliarytransformer, thus the current rating of the auxiliary switches ismuch smaller than that of the main switches. In addition, thesymmetric operation of the proposed converter makes the pri-mary current be optimized on the conduction loss and increasesthe utilization of the transformers.

III. OPERATIONAL PRINCIPLES

For the convenience of the mode analysis in steady state,several assumptions are made as follows.

1) The switches M1 , M2 , S1 , and S2 are ideal componentsexcept for their output capacitors and body diodes.

2) The capacitors C1 and C2 are large enough to be consid-ered as constant voltage sources, (1/2)Vin .

3) Turn ratio of the main transformer (T1) is n1 = NP 1 /NS 1and n2 = NP 2 /NS 2 for the auxiliary transformer (T2).

4) The primary current is constant during the very short pe-riod; t1–t2 , t2–t3 , and t4–t5 .

5) The output inductor LO is operated in constant conductionmode.

Each switching cycle can be divided into two half cycles t0–t8and t8–t16 . Because of symmetry, only the first-half cycle is ex-plained and the operating waveforms for the proposed converterillustrated in Fig. 4.


CHO et al.: HIGH-EFFICIENT MULTILEVEL HALF-BRIDGE CONVERTER 945

Fig. 4. Operating waveforms of the proposed converter.

Mode 1 (t0–t1): When commutation is completed at t0 , mode 1begins. In this mode, extra voltage is added to the nominalmain transformer voltage for the regulation of the converter.Thus, the input capacitor voltage Vin /2 and reflected auxiliarytransformer voltage, VS (2) are applied to the main transformer.The primary current increases linearly in this mode with theslope of [(Vin /2+VS (2))/n1−VO ]/LO .

Mode 2 (t1–t2): When S1 is turned off at t1 , mode 2 begins.The output capacitors of the auxiliary switches CS 1 and CS 2are charged and discharged, respectively, in a resonant manner.Since the large output inductor energy is participated in thisresonance, the ZVS condition of S1 and S2 are easily realized.

Mode 3 (t2–t3): After the auxiliary switch S2 is completelydischarged, the current of the auxiliary circuit ipri(2) flowsthrough the body diode of S2 , as shown in Fig. 5. Thus, thevoltage of S2 is sustained at 0 V, and the applied voltage to themain transformer remains at Vin /2.

Mode 4 (t3–t4): When the auxiliary switch S2 is turned onat time t3 , mode 4 begins. Since the output capacitor of S2 iscompletely discharged in the previous mode, it is turned onunder ZVS condition. The primary current decreases followingthe output inductor current in this mode. The primary currentipri is expressed as follows.

ipri(1)(t) =1n1

io(t) (1)

io(t) =

(vS (1) − vo

)Lo

× (t − t0) + ipri(1)(t3) × n1(VS (1) 〈 Vo

). (2)

Mode 5 (t4–t5): The main switch M2 is turn off at the begin-ning of this mode. The voltage of the output capacitor CM 2 is

linearly charged from 0 V, and the voltage of CM 1 is linearlydischarged from Vin at the same time by utilizing the large out-put inductance energy. This mode continues until the time whenthe primary voltage of the transformer reaches to 0 V.

Mode 6 (t5–t6): When the main transformer voltage Vpri(1)is decreased to 0 V, the voltage of main-switch M2 increasesin manner of resonance between Llkg and CM 1 + CM 2 . Thevoltage of M2 and the primary current are expressed as follows

vCM 2 (t) =(

ipri(1)(t5) +1n2

ipri(1)(t5))√

Llkg

CM 1 + CM 2

× sin

(√Llkg

CM 1 + CM 2t

)+ vCM 2 (t5) (3)

ipri(1)(t) = ipri(1)(t5) cos

(√Llkg

CM 1 + CM 2t

). (4)

On the secondary side, both the rectifier diodes start to con-duct and commutation of the two diodes D1 and D2 begin. Thismode ends when voltage of the switch M1 discharges to 0 V.

Mode 7 (t6–t7): In mode 7, the primary current flows throughthe body diode of the main switch, M1 . As the main transformeris regarded as short circuit, all voltages are applied to the leakageinductance and the primary current is sharply decreased. Theprimary current is expressed as

ipri(1)(t) = − (1/2)vin + (1/n2)vin

Llkg(t − t6) + ipri(1)(t6).

(5)Mode 8 (t7–t8): When the main switch M1 is turned on at t7 ,

this mode begins. The primary current, that was flowing thoughthe body diode of M1 in the previous mode changes the pathto the channel of switch M1 . The primary current in this modeis expressed the same as that of the previous equation (5). Thismode continues until following condition is satisfied:

n1 × ipri(1)(t) = iLo(t). (6)

IV. ANALYSIS OF THE PROPOSED CONVERTER

In this section, the key characteristics of the proposed con-verter are presented and they are compared with the character-istics of the asymmetric half-bridge converter.

A. DC Conversion Ratio

Fig. 6 shows the filter voltages in the proposed converterand the asymmetric half-bridge converter. The shaded areas inFig. 5 represent the output inductor voltages in each switchingcycle. According to voltage-second balance rule of the outputinductor, the dc conversion ratios are expressed as follows. Forthe proposed converter:

vO

vin=

1n1

×(

2n2

Deff +12

)(n1 , n2 ≥ 1) (7)



Fig. 5. Equivalent circuits of the proposed converter.



Fig. 6. Applied filter voltages in each converter: (a) he proposed converterand (b) asymmetric half-bridge converter.

where Deff represents the duration of mode1. The dc conversionratio for the asymmetric half-bridge converter is

vO

vin= 2

NS

NP× D(1 − D). (8)

Different from the dc conversion ratio of the asymmetrichalf-bridge converter, the dc conversion ratio of the proposedconverter has linearity, as shown in Fig. 7.

B. DC Offset Current in Magnetizing Inductor

Since the switches of the proposed converter are controlledsymmetrically, the dc offset of the magnetizing current can beeasily eliminated in the proposed converter. Therefore, the trans-former is fully utilized and it increases the power density of thesystem. However, the dc offset current in the magnetizing induc-tor is varied with the duty ratio in the asymmetric half-bridgeconverter. Thus, the utilization of the transformer is severely de-teriorated in the asymmetric half-bridge converter. The dc offsetcurrent for the proposed converter (9) and for the asymmetrichalf-bridge converter (10) are expressed as follows:

Deff

(ILm +

IO

n1

)= Deff

(−ILm+

IO

n1

).·. ILm ,proposed = 0

(9)

ILm ,conventional = (1 − 2 × D) × nS

nPIO. (10)

C. Output Filter Inductor

As shown in Fig. 6, the frequency shown at the output filter ofthe proposed converter is doubled than that of the asymmetrichalf-bridge converter and the applied voltage to the output in-ductor is also decreased. Thus the required output inductance forthe same ripple current condition can be reduced significantlyin the proposed converter compared to that of the asymmetrichalf-bridge converter. This property helps increase the powerdensity of the system. The output inductances required for theproposed converter and the asymmetric half-bridge converterare given by (11) and (12), respectively.

LO =[(0.5Vin + Vin/(1/n2)) /(1/n1)] − VO

∆IODeff T (11)

LO =(1/n1)(1 − D)Vin − VO

∆IODT. (12)

D. Component Stress

Due to the symmetric control of the switches, the proposedconverter has balanced current and voltage stress on its com-ponents, while the asymmetric half-bridge converter has un-balanced stress distribution because of its asymmetric controlmethod. As a result, the proposed converter can adopt primaryswitches with lower current ratings and rectifier diodes withlower voltage ratings than that of the asymmetric half-bridgeconverter. Thus, the cost of the switches can be reduced, and theefficiency of the rectifier diodes is increased with the proposedconverter.

E. ZVS Condition

The ZVS conditions of the auxiliary switches in the proposedconverter are well achieved because the output capacitors of theauxiliary switches are discharged by utilizing the large energystored in the output inductance. For the main switches M1 andM2 , the auxiliary transformer helps increase its ZVS range. Itis because the energy stored in the leakage inductance of theauxiliary transformer has also participated in the ZVS operationwith the energy stored in the leakage inductance of the maintransformer. Hence, the ZVS range can be extended with theleakage inductance of the auxiliary transformer. Fig. 8 showsthe required leakage inductance on every load current condition.As the turn ratio of the auxiliary transformer increases, therequired leakage inductance for ZVS operation is decreased.Therefore, the ZVS range in the proposed converter can beextended by increasing the turn ratio of the auxiliary transformerturn ratio. Also the auxiliary leakage inductance can be addedin the proposed converter to achieve ZVS operation in moreextended load range. The condition to realize the ZVS operationin the proposed converter is presented in (13).

12(2COSS)

(VS − 0.5 VS /

(1 +

1n2

))2

≤ 12Llkg i

2pri(1)

(13)where COSS is output capacitor of main switches. However,the ZVS condition of the asymmetric half-bridge converter isheavily depended on its dc offset of magnetizing current. Due to



Fig. 7. dc conversion ratios of each converter: (a) proposed converter and (b) asymmetric half-bridge converter.

Fig. 8. Relation of the minimum required leakage inductance and load current(at 700 W, Vo = 12 V spec.).

the offset current, the two switches in the same leg have differentZVS condition. The ZVS range of one switch is increased,but the range is decreased to the other switch in the same leg.Thus, to achieve safe ZVS condition in both switches, following

condition (14) must be satisfied.

12(2COSS)

(12VS

)2

≤ 12Llkg (ipri − ILm)2 . (14)

V. DESIGN CONSIDERATIONS

In this section, design guideline of the transformers ispresented.

There are two main factors that must be considered for theselection of turn ratio of the transformers in the proposed con-verter. These are the voltage regulation condition and the loss atthe auxiliary circuit. In the proposed converter, the main trans-former is always operated with its maximum duty ratio andoutput voltage is regulated by controlling the effective duty ra-tio of the auxiliary circuit. When the input voltage decreases, theauxiliary circuit supplies additional voltage to the main trans-former for the compensation of the input voltage. Therefore, tosatisfy the regulation condition, the voltage supplied by the aux-iliary transformer must be able to increase as much as maximuminput differences. This condition is expressed as follows:

Dnom < Deff ,max < 0.5 ( at, Vin,min)

0 < Deff ,min < Dnom (at, Vin,max). (15)

The aforementioned condition is also represented as a graphin Fig. 9. The proper range of the transformer turn ratio can bedetermined with the voltage regulation rule.

The loss at the auxiliary circuit is another factor when de-signing the transformers. To minimize the loss of the auxiliarycircuit, core loss of the auxiliary transformer and conductionloss of the auxiliary switches should be minimized. For the leastcore loss of the auxiliary transformer at nominal operating con-dition, the converter should be able to operate without utilizingthe auxiliary transformer at nominal operating condition. As aresult, the effective duty ratio has to be minimized at nominaloperating condition. Fig. 10 shows the effective duty ratio forthe different turn ratio of the auxiliary transformer. As the turnratio increases the effective duty ratio at nominal operating con-dition decreases. The increased turn ratio also helps extend ZVSrange of the main switches. Therefore, the largest turn ratio of



Fig. 9. Range of the transformer turn ratio (at 700 W, Vo = 12 V spec.).

Fig. 10. Effective duty ratio at nominal operating condition for the differentturn ratio of the auxiliary transformer (at 700 W, Vo = 12 V spec.).

the auxiliary transformer should be selected in the allowablerange in Fig. 9.

The size of the auxiliary transformer is influenced by theload range or the output power. When the auxiliary transformerturn ratio is determined, the core size of the transformer is se-lected by considering the current density of the transformer wire.The current that flows into the auxiliary transformer is reducedin proportion with the turn ratio of the auxiliary transformer.Therefore, the size of the auxiliary transformer is much smallercompared to that of the main transformer, but its size can beincreased followed by increasing output power.

VI. EXPERIMENTAL RESULTS

To verify the operation of the proposed converter and eval-uate performance of the proposed converter and the asymmet-ric half-bridge converter, prototype circuits have been designedwith following specifications: Input voltage : 400 V (330–400 V), output power: 700 W (12 V/58), switching frequency:86 kHz. The magnetic cores used for the proposed topology are

Fig. 11. Experimental waveforms: (a) proposed converter and (b) asymmetrichalf-bridge converter.

Fig. 12. Switch voltages of the proposed converter: (a) half-load conditionand (b) full-load condition.

two overlapped EI3026 (volume: 12 880 mm3 , µ : 2300) coresfor the main transformer and single EI3026 (volume: 6440 mm3 ,µ : 2300) core for the auxiliary transformer. In the asymmetrichalf-bridge converter, two EI3329 cores (volume: 15280 mm3 ,µ : 2070) are used as a transformer. For output inductor,CH234160 (volume: 2281 mm3 , µ : 160) and CH330060 (vol-



Fig. 13. Voltage regulation of the proposed converter: (a) nominal operation(Vin = 400 V) and (b) hold-up time operation (Vin = 330 V).

ume: 5477 mm3 , µ : 60) cores are used in the proposed con-verter and the asymmetric half-bridge converter, respectively.The switch used for the main switches in proposed converter isIPP60R299, and IPP60R600 is used for the auxiliary switches.In order to compare both converters in the same condition, thesame switches used in the proposed converter are adopted to par-allel connected switches in the main switches of the asymmetrichalf-bridge converter. Synchronous switches are also adopted inthe rectifier stage to improve efficiency of the converters. Forthe control of the experimental prototypes, a UCC3895 phase-shift PWM controller is used for the proposed converter anda IRS21844 S half-bridge driver is used for the asymmetrichalf-bridge converter.

Fig. 11 shows experimental waveforms for the proposed con-verter and for the asymmetric half-bridge converter at nominalload condition (12 V/58 A). The experimental results are in goodagreement with the theoretical waveforms. The ZVS conditionof the main switches in the proposed converter and the mainswitches in the asymmetric half-bridge converter are designedto operate ZVS down to half-load condition. The ZVS conditionof the proposed converter is shown in Fig. 12, and voltage reg-ulation operation of the proposed converter is shown in Fig. 13.As discussed earlier, the effective duty increased to its maxi-mum value when the input voltage decreased to the minimumoperation voltage.

Fig. 14 shows the efficiency of the proposed converter, theasymmetric half-bridge converter and the modified proposedconverter, which uses the same filter inductance with that of theasymmetric half-bridge converter. Since the balanced compo-nents stress in the proposed converter decreases the conductionloss of the converter, the proposed converters show higher ef-ficiencies compared to the asymmetric half-bridge converter.Also the efficiency graphs of the proposed converter and themodified proposed converter verify that the characteristic of re-duced filter inductance in the proposed converter helps decreasethe loss of the filter inductor.

Fig. 14. Efficiency comparisons.

VII. CONCLUSION

A new multilevel half-bridge converter was presented and an-alyzed. By employing one small subtransformer and two smalladditional switches, the proposed converter shows better perfor-mance than the asymmetric half-bridge converter in entire loadrange. The proposed converter has lower conduction loss and re-quires smaller filter inductance than the asymmetric half-bridgeconverter. Also, it achieves good ZVS condition, and its sym-metrical operation characteristic balances the voltage/currentstresses on its components and eliminates the dc offset of magne-tizing current, which degrade the utilization of the transformer.Therefore, the proposed converter can be selected as a goodcandidate in middle power server system.

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In-Ho Cho (S’09) was born in Korea in 1982. Hereceived the B.S. degree from Hanyang University,Seoul, Korea, in 2007, and the M.S. degree in electri-cal engineering from the Korea Advanced Institute ofScience and Technology (KAIST), Daejeon, Korea,in 2009. He is currently working toward the Ph.D.degree at the KAIST.

His research interests include dc/dc converter,power-factor-correction, ac/dc converters, and serverpower systems.

Mr. Cho is a member of the Korean Institute ofPower Electronics.

Kang-Hyun Yi (S’05–M’06) was born in Korea in1978. He received the B.S. degree in electrical engi-neering from Hanyang University, Seoul, Korea, in2003, and the M.S. degree in electrical engineeringand computer science from the Korea Advanced In-stitute of Science and Technology (KAIST), Daejeon,Korea, in 2006. He is currently working toward thePh.D. degree in electrical engineering at the KAIST.

His research interests include high-efficiencyplasma display panel driver circuit, dc/dc converters,soft switching technique, and digital display driver.

Mr. Yi is a member of the Korean Institute of Power Electronics.

Kyu-Min Cho (S’08–M’09) was born in Koreain 1978. He received the B.S. degree in electricalengineering from Kyungpook National University,Daegu, Korea, in 2003, and the M.S. degrees in elec-trical engineering from the Korea Advanced Insti-tute of Science and Technology (KAIST), Daejeon,Korea, in 2003. He is currently working toward thePh.D. degree at KAIST.

His research interests include dc/dc converters,power-factor-correction ac/dc converters, backlightinverters of liquid-crystal display television (LCD

TV), driver circuits of LCD TV, PC power supply, and server power systems.Mr. Cho is a member of the Korean Institute of Power Electronics.

Gun-Woo Moon (S’92–M’00) received the M.S.and Ph.D. degrees in electrical engineering from theKorea Advanced Institute of Science and Technol-ogy (KAIST), Daejeon, Korea, in 1992 and 1996,respectively.

He is currently a Professor at the Department ofElectrical Engineering, KAIST. His research inter-ests include modeling, design and control of powerconverters, soft-switching power converters, resonantinverters, distributed power systems, power-factorcorrection, electric drive systems, driver circuits of

plasma display panels, and flexible ac transmission systems.Prof. Moon is a member of the Korean Institute of Power Electronics, the

Korean Institute of Electrical Engineers, the Korea Institute of Telematics andElectronics, the Korea Institute of Illumination Electronics and Industrial Equip-ment, and the Society for Information Display.


Documents

High-Efficient Multilevel Half-Bridge Converter