High-density integration of carbon nanotubesvia chemical self-assemblyHongsik Park*, Ali Afzali*, Shu-Jen Han, George S. Tulevski, Aaron D. Franklin, Jerry Tersoff,

James B. Hannon and Wilfried Haensch

Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications1–7. However, forsuch technologies to be viable, a high density of semiconduct-ing nanotubes must be placed at precise locations on a sub-strate. Here, we show that ion-exchange chemistry can beused to fabricate arrays of individually positioned carbon nano-tubes with a density as high as 1 3 109 cm22—two orders ofmagnitude higher than previous reports8,9. With this approach,we assembled a high density of carbon-nanotube transistors ina conventional semiconductor fabrication line and then electri-cally tested more than 10,000 devices in a single chip. Theability to characterize such large distributions of nanotubedevices is crucial for analysing transistor performance, yieldand semiconducting nanotube purity.

The precise placement of carbon nanotubes on a substrate typi-cally involves one of three techniques: the direct growth of nano-tubes on a substrate10,11, the transfer of nanotubes from a ‘growth’substrate to a device substrate5,6, or the deposition of nanotubesfrom solution onto a device substrate8,9,12–18. Because nanotubescan be metallic or semiconducting, a further consideration forhigh-performance digital logic is the degree to which metallic nano-tubes can be eliminated. Although approaches for enriching sub-strate-supported semiconducting nanotubes during or aftersynthesis have been demonstrated19,20, currently the most effectivetechniques involve processing the nanotubes in solution21.

One promising approach for placing solution-based nanotubes isto selectively position them on a specific substrate by chemicallyfunctionalizing the nanotubes or the substrate14–18. This typicallyinvolves using a patterned surface (such as SiO2/HfO2) such thatnanotubes deposited from solution adhere only to one part of thepattern (the HfO2, for example). Key metrics for determiningthe efficacy of the deposition are the density of individuallyplaced nanotubes, which must exceed 1 × 1010 cm22, with a pitchsmaller than 10 nm for high-performance logic6,7, and the selectiv-ity, which is the degree to which adsorption takes place only on thepattern of interest. In general, however, solution-based approachesthat result in high density exhibit poor selectivity14,16, and thosethat offer high selectivity have low density17,18.

We have developed a selective placement method based on ionexchange between a functional surface monolayer and surfactant-wrapped carbon nanotubes in aqueous solution. Strong electrostaticinteraction between the surface monolayer and the nanotube surfac-tant leads to the placement of individual nanotubes with excellentselectivity and a density of 1 × 109 cm22. Furthermore, theapproach is compatible with the most efficient solution-based sep-aration schemes21, allowing wafer-scale integration using highlypurified carbon nanotubes.

Our nanotube placement using an ion-exchange techniqueis illustrated in Fig. 1a. The surface monolayer is formed from

4-(N-hydroxycarboxamido)-1-methylpyridinium iodide (NMPI)molecules, which were synthesized from commercially availablemethyl isonicotinate (see Methods). The monolayer contains ahydroxamic acid end group that is known to self-assemble onmetal oxide surfaces, but not on SiO2 (refs 17,18,22). We selectivelyself-assembled NMPI on HfO2 regions of a patterned SiO2/HfO2surface. The functionalized surface was then placed in an aqueoussolution of carbon nanotubes. Solubility of the nanotubes wasachieved using an anionic surfactant (sodium dodecyl sulphate,SDS). Excess surfactant in the solution was removed by dialysis.The anion of NMPI (that is, iodide) is exchanged with theanionic surfactant wrapped around the nanotubes, leading to astrong coulombic attraction between the negatively charged surfac-tant and the positively charged monolayer. In this process, theiodide of the monolayer and the sodium ion of the surfactant areremoved as sodium iodide, which is dissolved into the solution.The exchange mechanism was verified using X-ray photoelectronspectroscopy (XPS) measurements made before and after exposureof the monolayer to the surfactant (Supplementary Fig. S1).

To assess the selectivity and density of this placement technique,arrays of long, narrow HfO2 trenches were fabricated on a SiO2 sub-strate. Carbon nanotubes were selectively deposited on HfO2 regionscoated by NMPI (see Methods). Scanning electron microscopy(SEM) and atomic force microscopy (AFM) images recorded afternanotube deposition are shown in Fig. 1b–d. On the larger, openHfO2 areas (Fig. 1b), the deposited nanotubes are well dispersedand form monolayers with extremely high density and excellentselectivity. High density and selectivity are maintained even in thenarrower trenches (200 nm, Fig. 1c,d).

When positioning nanotubes on a substrate, it is critical to beable to control their alignment in addition to their location.Angular misalignment leads to a corresponding variation in thenanotube channel and contact lengths of transistors fabricatedwith the nanotubes, resulting in unacceptable variation in deviceperformance. Achieving high selectivity in the present approachnot only ensures accurate location positioning, but also promotesalignment of the nanotubes along a trench. Figure 2a shows howthe alignment improves as the trench width (Wtr) is reduced. Byreducing Wtr to 70 nm, the angular variation of the nanotubes rela-tive to the trench axis is reduced to less than+308. Figure 2b showsnanotubes selectively placed in an array of 70-nm-wide HfO2trenches with 200 nm pitch.

While placement in long, narrow lines is useful for characterizingalignment and density, device applications require precise confine-ment of nanotubes in both dimensions, that is, on narrow and shortlines. Figure 2c presents an SEM image of nanotubes depositedonto an array of short and narrow trenches with 200 nm pitch inthe x direction and 500 nm pitch in the y direction, correspondingto a density of 1 × 109 sites cm22. This density represents an

IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA. *e-mail: hpark@us.ibm.com; afzali@us.ibm.com

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improvement of two orders of magnitude over previously reportedresults obtained using microcontact printing8, dielectrophoresis9

or a scanning probe12. As determined from more than 350 trenchimages, the placement yield was �90% (that is, 90% of the trenchescontained at least one nanotube). However, a more comprehensiveyield can be evaluated by measuring the electrical properties (forexample, resistance) of transistors fabricated on the placed nano-tubes; for the transistor to work, the nanotube must be properlypositioned in the trench so as to span the defined source anddrain electrodes.

This ability to accurately place individual, aligned nanotubes at ahigh density enables the fabrication of a large number of nanotubetransistors on a single chip. Using the placement method, we fabri-cated thousands of transistors with a channel length (spacingbetween source and drain contacts) of 100 nm. As estimated fromSEM images of the channel regions, the average number of nano-tubes per channel was dependent on the trench dimensionsand the concentration of nanotubes in the deposition solution; nar-rower trenches and more diluted nanotube solutions resulted ina larger fraction of single-nanotube transistors (up to �78%;Supplementary Fig. S3). Direct numerical simulation of the measureddistributions of nanotubes per channel suggests that the probabilityof a nanotube from solution adhering in an empty trench is

roughly three times higher than that of adhering in an occupiedtrench (Supplementary Fig. S4). This propensity to form single-nanotube trenches is an important advantage of this approach.

Figure 3a presents images of the channel regions of an array ofnanotube transistors with a device pitch of 300 nm—an order ofmagnitude smaller than previous reports (�5 mm)9. Each transistorcontained one trench of width 100, 150 or 200 nm and length 1 mm.Because the nanotube transistors were designed and fabricated usinga conventional semiconductor fabrication facility, characterizationof the devices was compatible with high-volume electrical character-ization tools, enabling rapid testing of thousands of devices. Plots ofdrain current (ID) versus gate voltage (VG) from a subset of deviceson a chip (�300 devices) are shown in Fig. 3b. The curves providevaluable insight into the variation that exists in the nanotube tran-sistors, in addition to the population of devices that contained ametallic nanotube. A device yield of .90% was obtained with150 nm and 200 nm trench widths; as the trench width decreases,the yield of semiconducting devices increases, which is attributedto the yield of single-nanotube devices increasing (SupplementaryFig. S5). The highest device yield was achieved after optimizingthe surface-cleaning step that takes place before deposition of theNMPI monolayer; in other words, the density of NMPI, and thusnanotube density, is dependent on the surface cleanliness.

P++ SiHfO2

O NH

I−N+

H3C

O

Coulombicbonding

N+

O NH

H3CS

O

O

NaI

O

O−

NMPI

a b

c

SiO2

Carbon nanotubes on HfO2d

SiO2SiO2

SiO2

Nanotubeson HfO2

SDS

Carbon nanotube

SO O

O− Na+

SiO2

Figure 1 | Selective placement of carbon nanotubes by an ion-exchange process. a, Schematic of nanotube placement on the surface monolayer, which is

selectively coated on the HfO2 regions. The iodine ion in the end group of the NMPI monolayer is exchanged by the negatively charged SDS surfactant

wrapping the nanotubes; Naþ in SDS and I2 in NMPI are dissolved into solution as a sodium iodide. The thickness of SiO2 is 10 nm and the width of the

HfO2 trenches varies from 70 nm to 200 nm. The Pþþ Si layer is a highly doped p-type Si substrate. b, SEM image of nanotubes deposited on an open HfO2

area, showing extremely high density and excellent selectivity (scale bar, 2 mm). c,d, SEM image (c) and AFM (phase) image (d) of the nanotubes selectively

deposited on an array of 200-nm-wide HfO2 trenches. Good density and selectivity are maintained on these narrower trenches. Scale bars are 500 nm.

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For fast assessment of the key device parameters from a largenumber of devices, the measured characteristics for each transistorwere modelled by fitting the measured ID–VG curves to a parametricfunction (see Methods). Representative curve fits are shown inFig. 3c. Figure 3d shows the distributions of the threshold voltage(VT) and inverse subthreshold slope (SS) extracted from 7,066 semi-conducting devices. These devices were selected from about 12,000connected nanotube devices by excluding devices that did notexhibit current levels expected for the transistor dimensions, andso on (such devices typically contained a metallic nanotube oran extremely short contacted length, leading to high contact resist-ance and low current5). In this analysis, VT was defined as thegate voltage corresponding to a drain current of 3 nA. Theaverage on-state drain current (Ion), measured at VG¼VT 2 1.5 Vand VDS¼20.5 V, was 1.33 mA. These results show that the per-formance of devices fabricated using the chemical assembly is com-parable to that produced by the deposition of nanotubes fromsolution that did not undergo the same chemical treatments23–25.Annealing the wafer after nanotube deposition to remove theNMPI monolayer is crucial to maintaining this good electrical per-formance (Supplementary Fig. S6).

Before this study, device metrics for nanotube transistors, such asIon, VT, SS and the purity of semiconducting devices, were typicallyevaluated from, at most, a few hundred devices23–27. However, torealistically consider carbon-nanotube transistors for a technology,

the distribution in performance across tens of thousands ofdevices must be statistically analysed and optimized. One keyexample comprises the accurate measurement of the fraction of met-allic nanotubes in a solution. Metallic nanotubes lead to transistor‘shorts’, and must be largely eliminated. A competitive carbon-nanotube logic technology requires an extremely high purity ofsemiconducting devices, with a metallic fraction less than at least1 × 1024. Measuring this level of purity in solution has notproven possible, leaving large-scale device fabrication and testingas the only viable method. Our new ion-exchange placementapproach provides a platform for such testing to be realized.The capability of measuring the device parameter distributionsfrom a large number of nanotube transistors will also be criticalin developing robust wafer-scale processes for carbon-nanotubeintegrated circuits.

In summary, we have demonstrated a new ion-exchange surfacechemistry approach for the placement of individual carbon nano-tubes with a density of 1 × 109 cm22. The method combines excel-lent selectivity with nanotube alignment at a high density to enablethe formation of single-nanotube devices. The compatibility of thisapproach with existing semiconductor technology was shown byfabricating tens of thousands of nanotube transistors within a con-ventional fabrication facility. Electrical testing shows that the per-formance of nanotube devices is not significantly degraded by thedeposition chemistry. This new placement technique is readily

a

b

W = 200 nm W = 70 nm W = 100 nm

c

Trench density = 109 cm−2

SiO2 Carbon nanotubes on HfO2

90

60

30

0

θ (d

eg)

−30

−60

−90

90

60

30

0

θ (d

eg)

−30

−60

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θ (d

eg)

−30

−60

−900 200

Tube length (nm)400 0 200

Tube length (nm)400 0 200

Tube length (nm)400

1 µm

10 nmW

θ

Figure 2 | High density of individually positioned carbon nanotubes. a, Plots of angular alignment of individual nanotubes versus length of the nanotube for

trenches of three different widths (W¼ 200 nm, 100 nm, 70 nm). Inset: schematic showing how the angular alignment u is defined (08 is perfect alignment

in a trench). By reducing the trench width to 70 nm, the angular variation was reduced from+758 to less than+308. b, SEM image of nanotubes selectively

placed and well-aligned in an array of 70-nm-wide HfO2 trenches with a 200 nm pitch (scale bar, 400 nm). c, SEM image of nanotubes selectively placed in

an array of short and narrow trenches with a 200 nm pitch in the x direction and 500 nm pitch in the y direction, corresponding to a density of 109

sites cm22 (scale bar, 400 nm). This demonstrates precise placement in two dimensions (rather than just one dimension with the long trenches in b). As

determined from more than 350 trench images, �90% of the trenches contain at least one nanotube.

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implemented, involving common chemicals and processes, andprovides a platform for future nanotube transistor experimentalstudies. Furthermore, these results show that nanotube placementvia chemical self-assembly is a promising approach for developinga viable carbon-nanotube logic technology compatible with existingsemiconductor fabrication.

MethodsSynthesis of NMPI molecules. The surface monolayer was formed from NMPImolecules, and was synthesized in two steps from the commercially availablemethyl isonicotinate. Methyl isonicotinate was converted to its correspondinghydroxamic acid, 4-(N-hydroxycarboxamido)pyridine, using a previously describedprocedure in ref. 28. Methyl iodide (10 g) was added to a solution of 4-(N-hydroxycarboxamido)pyridine (5.14 g, 0.03 mol) in 200 ml of methanol, and themixture was stirred at room temperature for 3 days. The precipitate was filteredand washed with methanol and dried. Crystallization from 9:1 ethanol–waterafforded the analytically pure pyridinium compound NMPI as light yellowcrystals (7.35 g, 84%). 1H NMR (DMSO-d6), d; 4.38 (s, 3H), 8.3 (d, j¼ 6 Hz, 2H),9.1 (broad d, j¼ 6Hz, 2H).

Purification of single-walled carbon nanotubes. A 1 g ml21 solution of carbonnanotubes (Hanhwa Nanotech) in 1% aqueous SDS (Sigma Aldrich) was preparedvia horn sonication (99%, 1 s pulse, 20 min). The solution was then purified using astep-gradient ultracentrifugation process. For the purification, 6 ml of 1% SDS in45% iodixdinol (Sigma Aldrich) solution was prepared and layered below 6 ml of thenanotube solution in a 12 ml centrifuge tube. The layered solution was thencentrifuged for 15 h at 41,000 r.p.m. using a Beckman Coulter Optima L-100 XP

ultracentrifuge equipped with a swinging bucket-type rotor. The purified nanotubesolution sedimented at the interface of the two layers while the graphitic impuritiesand large bundles settled to the bottom of the centrifuge tube. The purified nanotubesolution was then removed via pipette and diluted 1:1 with 1% aqueous SDS solutionbefore loading on the column. It is important to note that this step-gradientcentrifugation step is only used to remove the graphitic impurities and concentratethe solution (very effective) and does not sort the nanotubes in any fashion. Achromatography step was then performed to isolate the semiconducting nanotubes.

Isolation and dialysis of semiconducting-enriched carbon-nanotube solution.The semiconducting nanotubes were separated from the purified nanotube solutionby means of column chromatography, which was modified from a previouslyreported method described in ref. 29. A column was prepared by loading a 25-mm-diameter glass chromatography column with a Sephacryl-200 slurry (SigmaAldrich). The column was flushed with 1% wt/vol SDS solution several times. Thenanotube solution was then added to the column and allowed to pass through thecolumn using a small positive nitrogen gas pressure. Once the solution was fullyinserted into the column, more 1% SDS solution was added and was continuallyadded until all of the nanotubes (now separated) passed through the column.Initially, a blue fraction (metallic) passed through, followed by a red band(semiconducting). Fractions of the solution were collected in small glass vials andcharacterized using a UV–vis–NIR absorption spectrometer (Perkin Elmer Lambda950). Excess SDS in the solution was removed via dialysis, with the concentratednanotube solution syringed into a dialysis cartridge and placed in 1 l of deionizedwater and changed daily for four days.

Fabrication of carbon-nanotube transistors. To assemble the carbon nanotubes,HfO2 trenches were fabricated by patterning SiO2 on HfO2-coated substrates. First,

−0.04 ± 0.44 V 265.2 ± 120.8 mV dec−1

d

VDS = −0.5 V

VDS = −0.5 V

c

a

Leads to pads

Transistor array

b

10−5 800

600

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Cou

nt

I D (A

)

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)

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800 1,000

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VG (V)

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−2 −1 0VG (V)

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1 2

10−6

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10−9

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10−8

10−10

10−12

10−11

7,066 devices 7,066 devices

Single tube

Double

Single

Single

SiO2

Pd300 nm

Nanotube channel

Metallic or bundled nanotubes

Figure 3 | Demonstration of high-density carbon nanotube transistors (CNTs). a, Optical (left) and SEM (right) images of nanotube transistor arrays with a

pitch of 300 nm. Source and drain contacts for the devices in the array are connected by metal leads and pads for electrical testing in a semi-automated

probe station. The achievable device density estimated from the device pitch and trench dimension is .1 × 108 transistors cm22. (Contrast and brightness in

the vicinity of nanotubes have been adjusted to make them more visible.) b, Subthreshold characteristics (log(ID)–VG curves) from a subset (310 devices) of

total devices on a chip. The yield of electrically connected devices is larger than 90% (evaluated from measurement of 3,312 devices). c, Four representative

ID–VG data (dots) from the large sets of devices measured in a semi-automated probe station and curves fitted using a parametric function (solid lines).

Device parameters (VT, Ion, SS) can be assessed from the fitted curves. Inset: plots in a linear scale. d, Distribution of threshold voltages (left) and inverse SS

(right) extracted from measurements of 7,066 semiconducting nanotube transistors on a single chip. The ability to analyse key performance metrics from such

a large number of devices provides valuable information regarding variability and yield and is a critical advance for a carbon-nanotube transistor technology.

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10 nm HfO2 was deposited on a highly doped p-type silicon substrate via chemicalvapour deposition (precursor, hafnium-tetra-tert-butoxide Hf(C4H9O)4; carrier gas,O2; working pressure/temperature, 0.3 torr/500 8C) and treated by a rapid thermalannealing at 700 8C in a N2 atmosphere. Trench patterns were defined by electron-beam lithography (in PMMA), deposition of 5 or 10 nm of SiO2 by electron-beamevaporation with a deposition rate of 0.2 nm s21, and liftoff in acetone. Note that therole of the evaporated SiO2 layer was to prohibit the deposition of nanotubes so as toachieve the demonstrated excellent selectivity, and the layer was not included in thegate dielectric of final devices. Before self-assembly of the NMPI monolayer, thesubstrate was cleaned by oxygen plasma at 300 mtorr for 5 min. The NMPImonolayer was then assembled on the patterned surface by placing the substrate in a3.5 mM solution of NMPI (3:1 ethanol/water) for 1 h. The surface was then rinsedwith ethanol. The substrate was then placed horizontally with its surface facingupwards in the dialysed nanotube solution for 1 h, without an agitation. Afternanotube deposition, the substrate was rinsed with flowing deionized water for 30 sand subsequently in a sonication bath with deionized water for 1 min. The substratewas then annealed at 450 8C under Ar/H2 for 5 min to drive off the monolayer andeliminate its effects on device performance. Source and drain electrodes(Ti/Pd/Au¼ 0.5/20/20 nm) were patterned on the nanotubes via electron-beamlithography with a channel length of 100 nm. The highly doped silicon substrate wasused as a backgate. In the deposition process, an effective cleaning process wascritical to achieve a high density of placed nanotubes. The majority of the electricalcharacterization for large device sets in this work was performed on wafers that hadbeen cleaned with a 700 8C anneal in oxygen before NMPI deposition. However, thisprocess only provided a device yield of �50%. A subsequent wafer that was subject tothe oxygen plasma cleaning step resulted in the �90% yield.

Fitting measured VG–ID curves. The measured data from large sets of devices wereautomatically analysed by fitting each measured curve to the expression

ID(VG) = Ioff + a ln(1 + z) + bz

1 + z

where z¼ exp[(VT–VG)/SS]. The five fitting parameters are VT, Ioff , SS, a and b. Ioffis the off-state drain current defined as ID(VTþ 1 V). This strictly empirical fittingfunction includes all the necessary features to allow a good fit and analysis: a smalloff-state current, a voltage threshold and an exponential rise near the threshold.

Received 10 July 2012; accepted 26 September 2012;published online 28 October 2012

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AcknowledgementsThe authors thank J. Bucchignano and G. Wright for their expert technical assistance withelectron-beam lithography, and Q. Cao for helpful discussions.

Author contributionsH.P., A.A., G.S.T. and S.H. developed the carbon nanotube placement method. H.P., S.H.and A.D.F. fabricated and characterized the nanotube transistors. J.B.H., J.T. and W.H.developed the model and software for rapid assessment of the large sets of measured data.All authors contributed to discussing the results and writing manuscript.

Additional informationSupplementary information is available in the online version of the paper. Reprints andpermission information is available online at http://www.nature.com/reprints. Correspondenceand requests for materials should be addressed to H.P. and A.A.

Competing financial interestsThe authors declare no competing financial interests.

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