High Average-Efficiency Power Amplifier Techniques

Jason Stauth, U.C. Berkeley Power Electronics Group

LVout

PA

Feedforward Adapt Signal/s

Lc

VDD Digital Sigma-

delta PWMDead time

controlNonlinear

Feedforward:f(t,v)

22 QI

I

Q

L

L

3-PhasePower train

Baseband Digital pre-distortion

S

Overview

• Application Space: Efficient RF Power Amplifiers

• PA Fundamentals, Polar/ET Architectures• Challenges with Polar/ET

• Research Directions• Direct Digital Modulation• Pulse-Density Modulation

Power Amplifier Fundamentals

VDD

RL

BiasVout

Rs

Vs

Source

InputNetwork

Output Network

RF-in

PowerAmplifier Antenna

RF-out

Q

I

Edge Constellation: 3pi/8, rotated 8-PSK

Linear Power Amplifier (PA)

RL

VoutImpedance Matching Network

Impedance Transformation

NetworkZin

Rs

VsGM

Zo

Active Device

Source Antenna

RL/N

Vout/NRs

VsGM

Active Device

Source Antenna

Rs Ro

•Active transconductance device

•Input matched to previous stage

•Output (antenna) impedancetransformed to increasepower gain

•Small-signal model close to common source amplifier

Nonlinear PA

• Active device operates as a switch

• Approx LTV System

• Voltage waveform constrained

(also consider current waveform)

RL

VoutOutput

Network

Zo

Active Device

Antenna

Rs

Vs

Source

Comparator

constrained unconstrained constrained

Gate Voltage

Dra

in V

olta

ge

• Class-F— Frequency Domain— Impedance Design

• Class-E— Time domain— Impulse Response

design-Class E/F ZVS Amplifiers, Kee et al., MTT ‘03

The Point…

• Nonlinear PAs can’t do amplitude modulation

• Linear PAs can do amplitude modulation, but are inefficient

2

2

2

1

dd

aA V

V

dd

aB V

V

4

dd

aS V

V

Average Efficiency

0%

1%

2%

3%

4%

5%

-60 -50 -40 -30 -20 -10 0dB(Pmax) - dB(Pout)

Eff

icie

ncy

0%

20%

40%

60%

80%

100%

Pro

bab

ilit

y

PDF Class A Class B Nonlinear*

LLsupplyL

LLL

supply

loadavg

dPPPPg

dPPPg

E

E

)()(

)(

LL

LL

LLL

dPP

PPg

dPPPg

)()(

)(

PA Class: Class A Class B Nonlinear PA

Average Efficiency:

0.78%* / 9.2%**

14.46% 18.21%

*constant bias current

**variable bias current

Polar and Envelope Tracking Transmitters

• Supply regulation synchronous with RF Envelope

Voltage Regulator

0%

1%

2%

3%

4%

-60 -50 -40 -30 -20 -10 0dB(Pmax) - dB(Pout)

Eff

icie

nc

y

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Pro

ba

bil

ity

Ideal Class-B PA Efficiency

0%

1%

2%

3%

4%

-60 -50 -40 -30 -20 -10 0dB(Pmax) - dB(Pout)

Effi

cien

cy

0%10%20%30%40%50%60%70%80%90%

Pro

babi

lity Ideal Dynamic

Supply PA

0%

1%

2%

3%

4%

-60 -50 -40 -30 -20 -10 0dB(Pmax) - dB(Pout)

Eff

icie

nc

y

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

Pro

ba

bil

ity

Realistic Dynamic SupplyPA Efficiency

%5.62avg-Raab et al. “High efficiency L-band Kahn-technique transmitter," MTT-S, 1998.

-Hanington, et al. "High-Efficiency Power Amplifier Using Dynamic Power-Supply Voltage for CDMA Applications," MTT, Aug. 1999.

Polar Architecture

0

0.2

0.4

0.6

0.8

1

0 2 4 6 8 10time

Am

plit

ud

e S

ign

al

-1.5

-1

-0.5

0

0.5

1

1.5

0 2 4 6 8 10

timeP

ha

se

Sig

na

l

PA

Regulator

PolarModulator

Env.Det.

A(t)

Φ(t)SRFLO

Limiter

I

Q

S

)(),(

)sin()cos(),(

wtjeFV

wtQwtIQIFV• Many (most?) implementations don’t use

an efficient supply modulator • efficiency gains from using nonlinear PA

Q

I

Envelope Tracking

• Linear (class-AB) PA

• Efficient supply modulator (linear reg doesn’t make sense)

Bas

eban

dG

ener

atio

n

RF

RF LOLinear

PA

V(t)

Env

elop

eM

appi

ng

Envelope Feedback

Operate at max PAE point

Challenges

• Bandwidth

• Peak-average power ratio

• Time alignment

• Distortion (AM-AM, AM-PM)

• PSRR

SystemBandwidth

(MHz)Peak-Average

Power Ratio (dB)Power Control

Range (dB)

GSM 0.20 0 30

EDGE 0.20 3.2 30

WCDMA 3.84 3.5–7 80

cdma2000 1.23 4–9 80802.11a/g 18.0 6–17 —

-15 -10 -5 0 5 10 15-20 20

-90

-80

-70

-60

-50

-40

-30

-20

-100

-10

freq, MHzdBm

(fs(

WLA

NA

[1],-

20M

,20M

,,,"K

aise

r"))

42.5 43.0 43.542.0 44.0

0.10.20.30.40.50.60.70.80.91.0

0.0

1.1

time, usec

mag

(WLA

NA

[1])

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5-2.0 2.0

-90

-80

-70

-60

-50

-40

-30

-20

-100

-10

freq, MHz

dBm

(fs(

CD

MA

2k[1

],-2M

,2M

,,,"K

aise

r"))

27 29 31 3325 35

0.2

0.3

0.4

0.1

0.5

time, usec

mag

(CD

MA

2k[1

])

0.1 0.2 0.3 0.4 0.50.0 0.6

50

100

150

200

0

250

indep(histogram(mag(CDMA2k[1]),250,0,.5))

hist

ogra

m(m

ag(C

DM

A2k

[1]),2

50,0

,.5)

0.1 0.2 0.3 0.4 0.5 0.6 0.70.0 0.8

50

100

150

200

0

250

indep(histogram(mag(WLANA[1]),250,0,.8))

hist

ogra

m(m

ag(W

LAN

A[1

]),2

50,0

,.8)

Project Directions

-

+C

VDD

Switching Regulator

Load

Linear Regulator

ILr ISr

ILoad

Vref

Feedback

S-

+

eControl/PWM

L

Bas

eban

dG

ener

atio

n

IF

RF

RF LOLinear

PA

V(t)

Env

elop

eM

appi

ng

Envelope Feedback

RF Pulse Train

Pulse-density modulation process

Mixer PA Filter

Wideband Switching Regulators

Hybrid Linear-Switching Regulators

Direct Nonlinear Modulation Transmitters

Wideband Switching Regulators

• Envelope Tracking Architecture• Wideband: 20MHz Envelope bandwidth• High switching frequency• High PSRR PA

Control&

PWM

Baseband

Baseband-Envelope

Map

EnvelopeDetect

AND/OR

PA RF-Out

Vdd

.

Filter

Switching Regulator

LO

RFIF

upconversion

EnvelopeReference

0%

1%

2%

3%

4%

-60 -50 -40 -30 -20 -10 0dB(Pmax) - dB(Pout)

Effic

ienc

y

0%

10%

20%

30%

40%

50%

60%

Prob

abili

ty

Probability density functionPA Efficiency

w/o dynamicsupplywith

dynamic supply

Challenge: Power Supply Rejection

• Supply noise can mix into the RF spectrum, degrading SNR, violating spectral masks (ACPR)

• New Concept: design for high PSRR

Voltage Regulator

RF AmplifierRF Input RF Output

Power Supply Noise

wo

wo

w

w

P(d

B)

P(d

B)

P(d

B)

-Stauth, Sanders, "Power supply rejection for RF amplifiers," (RFIC) Symposium, June 2006

Results: MTT Oct ‘07

• Supply-Signal mixing term:

423222111

1

222 KgmbKgmKyKgmo

gmdBPSRR

0

423222111111

222),(

K

KgmbKgmKyKgmoyjwjwA Sba

0

10

20

30

40

50

60

70

1.E+06 4.E+06 1.E+07 5.E+07 2.E+08 7.E+08 3.E+09 1.E+10Frequency (Hz)

PS

RR

(d

BV

)

gmo11gmo11+go2gmo11+go2+C2

go2*

gmo11*

C2*

Total PSRR value

PSRR=sideband in dBc for 1V (0dBv) supply noise tone

),(

)(2

011

010

SjwjwA

jwAdBPSRR

Hybrid Linear-Switching Regulators

Hybrid Regulator Paradigm

-

+C

VDD

Switching Regulator

Load

Linear Regulator

ILr ISr

ILoad

Vref

Feedback

S-

+

eControl/PWM

L

-

+

C

VDD

Switching RegulatorLoad

Linear Regulator

Vref RefControl/PWM

L

Series Hybrid Parallel (shunt) Hybrid

•Decouple bandwidth-efficiency (audio, AVS digital, PA supply)

•Fast linear block: (supply dynamic output voltage, attenuate switching regulator harmonics)

•Slow switching block: (efficient, low cost)

•Series hybrid drawbacks: low Vdd efficiency, headroom issues

Parallel Hybrid Operation

• Linear Stage: Voltage Follower(Class AB LDO)

• Switching Stage: Current source

• Traditional:

• Previous work: Optimize in the frequency domain

-

+C

VDD

Switching Regulator

Load

Linear Regulator

ILr ISr

ILoad

Vref

Feedback

S-

+

eControl/PWM

L

SwitchingFrequency

SwitchingReg. BW Linear Reg. BW

Dynamic Supply BW

-Yousefzadeh, et al. ISCAS ‘05, PESC 06.-F. Wang et al, MTT-S, June 2004.-P. Midya et al. PESC, ‘00.

LOADSR ii

This Work: Optimize in the Time Domain

• Fundamental: many signals may share same power spectrum• Phase of signals not represented can be critical for max efficiency in the

time domain• Consider strong nonlinearities in conversion from Cartesian to polar

representation

0 1 2 30

5

10

15

Sig

na

l A (

V)

0 1 2 30

5

10

15

Sig

na

l B (

V)

time (s)0 5 10 15 20 25

-100

-80

-60

-40

-20

0

20

frequency (Hz)

Po

we

r S

pe

ctru

m (

dB

/Hz)

PAPR=5.2 dB

PAPR=10.1 dB

Interesting Conclusions

00.10.20.30.40.50.60.70.80.9

1

0 0.1 0.2 0.3 0.4 0.5Modulation Amplitude, Normalized (V)

Effi

cie

ncy

Sin-AM isr=isr*

Sin-AM isr=idc

2-tone isr=isr*

2-tone isr=idc

•Traditional method with is suboptimal

•Optimum isr is a function of Vdd, and dynamics of the modulation signal

•Power savings potentially very large for high PAPR signals, high Vdd

00.10.20.30.40.50.60.70.80.9

1

0.0 5.0 10.0 15.0 20.0 25.0

Average Output Power (dBm)

Effi

cie

ncy

isr = idcisr = isr*

Sin-AM, 2-Tone: IS-95 CDMA:

LOADSR ii

Future Work

• Adaptive optimization

• Performance tuning

-

+

WeightedSum

Switching Regulator

Linear Regulator

ILr ISr

ILoadVref

SwitchingRegulator

Vdd1 Vdd2

ILr-supply ISr-supply

Adaptive Extremum Seeking

Look up table (LUT)

Average power level

Current Command, isr

To Load: PA

From baseband, or measured at

input or output of PA

CurrentScheduling

Digital Pulse-Density Modulation

This work:1-Bit Linear Transmitter

• PA at ‘max power’ or ‘off’• Inherent linearity• Improved efficiency in

power backoff…

RF Pulse Train

Pulse-density modulation process

Mixer PA Filter

Pulse Density Modulation Process

• AM process Extra harmonics• Tradeoff between oversampling ratio & Q

—Out of band spectrum—Efficiency

• Noise shaping: digital S• Conclusions

—No major efficiency advantage with Q<~5-10—Linearity may be the compelling factor— (almost) pure digital implementation!—Need to run PDM process *as fast as possible*

Pow

er s

pect

rum Filter profile

Carrier withDSB harmonics

PDM Process

S

S

G(z)-1

PDMquantizer

v(t) y(t)

S S z-1

PDMquantizer

v(t) y(t)•Sigma-delta

•Error feedback

Spectrum: •bandpass in nature•Amplitude modulation•Noise Shaping

PDM Process

0.4 0.6 0.8 1 1.2 1.4 1.6-5

0

5

10

15

Frequency (Hz)P

ower

/fre

quen

cy (

dB/H

z)

Power Spectral Density

0 2 4 6 8 10 120

0.5

1

Time-Domain Waveforms

0 2 4 6 8 10 120

0.5

1

•Modulate at fraction of carrier frequency out of band harmonics

0.4 0.6 0.8 1 1.2 1.4 1.6-5

0

5

10

15

Frequency (Hz)P

ower

/fre

quen

cy (

dB/H

z)

Power Spectral Density

0 2 4 6 8 10 120

0.5

1

Time-Domain Waveforms

0 2 4 6 8 10 120

0.5

1

PDM Process

•Modulate at fraction of carrier frequency out of band harmonics

0.4 0.6 0.8 1 1.2 1.4 1.6-5

0

5

10

15

Frequency (Hz)P

ower

/fre

quen

cy (

dB/H

z)

Power Spectral Density

0 2 4 6 8 10 120

0.5

1

Time-Domain Waveforms

0 2 4 6 8 10 120

0.5

1

PDM Process

•Modulate at fraction of carrier frequency out of band harmonics

Class-D PA

• Conventional timing, control• Series-Resonant Filter block out of band

harmonics• High impedance out of band reduce power

drawn from supply for ‘wasted’ energy

50ΩZ-xf, BPF

VDD

10-1

100

101

30

40

50

60

70

80

mag

(impe

danc

e) (

ohm

s) (

dB)

Impedance vs Frequency

frequency (Hz) (rad/sec)

Architecture

• Cartesian Representation

— Noise-Shaped PDM amplitude modulation

— Independent I-Q processing/upconversion

— Class-D PA

— Series resonant bandpass filter/transformer

PA

BasebandI

Q

Pulse-Density

modulator

50Ω

S

RFclk 0o

Upconversion

PAPulse-Density

modulator

Upconversion

RFclk 90o

This work

Q

I

Behavioral Verification

• Ideal Components, PDM process• Passive network Q~30• Vdd=1.0V (assume 90nm CMOS)

Class-D PA

I Pulse-Density

modulator

RFclk 0o

Upconversion

50ΩZ-xf, BPF

VDD

timin

g,

driv

ers

Ideal no losses in switches, passives

Carrier Fundamental Linearity

• Simulation, expt show good linearity vs pulse density

• IM3 comparable to good linear PA (range of -20dBc to -40dBc)

• Predistortion likely to improve linearity further

Output Voltage Amplitude vs Code

y = 7.27E-04x3 - 1.37E-02x2 + 3.61E-01x

0.000

0.500

1.000

1.500

2.000

2.500

3.000

0 2 4 6 8 10

ClassD PA, 90nm CMOS, Spectre Sim, Q~15 in passives

2-tone test

Conclusions

• Efficiency stays high in power backoff• Future analysis: comparison of series resonant to

parallel resonant output filters for class-D PAs

• High linearity, compelling argument for this architecture

Implementation

Class-D PA

I Pulse-Density

modulator

RFclk 0o

Upconversion

50ΩZ-xf, BPF

VDD

timin

g,

driv

ers

Two chips:•Modulator•Class D PA

Both 90nm CMOS,Low voltage (1.0V),Wirebond chip-on-board

Architecture

• Multiple stages: RF PDM and Baseband sigma-delta

• Tradeoff oversampling for power consumption• Still have 10-100x oversampling for most

standards (edge, Bluetooth, WCDMA, 802.11x)

I (10 bits)

1-bit PA

LO

S modulator (3rd order)

From baseband

CLK (100MHz)

Reg

iste

r

Reg

iste

r

Syncronization

1.95GHz

S Modulator(10à 4.25 bits)

Pulse-Density Modulator (4.25à 1 bit) PA

RF DAC (PDM)

PDM Process

S

S

G(z)-1

PDMquantizer

v(t) y(t)

0 10 20 30 40 50-90

-70

-50

-30

FREQUENCY (MHz)

PO

WE

R (

dB

m)

-1 -0.5 0 0.5 1-1

-0.5

0

0.5

1Pole-Zero Map

Real Axis

Imag

inar

y A

xis

1.9 1.925 1.95 1.975 2-80

-60

-40

-20

FREQUENCY (GHz)

PO

WE

R (

dB

m)

321 5.25.21)( zzzzG

PA Blocks

• Use 2.0V to drive for higher output power• Maximum Voxide=1.0V• No resonant switching: need accurate control of gate voltage• Recycle current used by high-side switches (excess goes to

digital processing block)

PA Drivers Output StageVHV=2.0 V

Vhalf=1.0 V

Delay, 60ps

Delay, 60ps

Vhalf

Vhalf

Level Shift Deadtime Control

Vin

Results

• Program I/Q waveforms into FPGA

• Downconvert/process signals with NI PXI box running labview

• Results show linear downconverted I/Q waveforms

1.2

-1.0

-750.0m

-500.0m

-250.0m

0.0

250.0m

500.0m

750.0m

1.0

Time (sec)250.0u0.0 25.0u 50.0u 75.0u 100.0u 125.0u 150.0u 175.0u 200.0u 225.0u

Plot 0AM Demodulated Signal

RF clk: 1.95GHz

Xylinx Virtex II FPGA

PDM Transmitter

Laptop

NI-PXIRF

(Labview)

Two-tone spectrum

• 10mV tones with 2MHz spacing at 1.95GHz carrier

• 20MHz of noise shaping is functional, noise peaks 50MHz from carrier at fs/2

• LO leakage tuned with signal offset

1.85 1.9 1.95 2 2.05-65

-60

-55

-50

-45

-40

-35

Frequency (GHz)

Po

we

r (d

Bm

)

802.11a, 64QAM OFDM Waveform

• 10mV tones with 2MHz spacing at 1.95GHz carrier

• 20MHz of noise shaping is functional, noise peaks 50MHz from carrier at fs/2

• LO leakage tuned with signal offset

1.85 1.9 1.95 2 2.05-60

-50

-40

-30

-20

-10

Frequency (GHz)

Pow

er (

dBm

)

WCDMA Spectrum

References

• [1] A. Jerng and C. G. Sodini, "A Wideband Delta-Sigma Digital-RF Modulator for High Data Rate Transmitters," IEEE Journal of Solid State Circuits, vol. 42, pp. 1710-1722, Aug. 2007.

• [2] A. Kavousian, D. K. Su, and B. A. Wooley, "A Digitally Modulated Polar CMOS PA with 20MHz Signal BW," IEEE International Solid State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 78-588, 2007.

• [3] S. M. Taleie, T. Copani, B. Bakkaloglu, and S. Kiaei, "A bandpass Delta-Sigma RF-DAC with embedded FIR reconstruction filter," IEEE International Solid State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 578-579, 2006.

• [4] R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and GSM/EDGE transmitter in 90nm CMOS," IEEE International Solid State Circuits Conference, vol. 1, pp. 316-600, Feb. 2005.

• [5] J. Lindeberg, J. Vanakka, J. Sommarek, and K. Halonen, "A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.12um CMOS," IEEE Journal of Solid State Circuits, vol. 40, pp. 1978-1982, Sept. 2005.

• [6] F. Wang, D. Kimball, D. Y. Lie, P. Asbeck, and L. E. Larson, "A Monolithic High-Efficiency 2.4GHz 20dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier," IEEE Journal of Solid State Circuits, vol. 42, pp. 1271-1281, June 2007.