HFSS Solver On Demand for Package and PCB · PDF fileHFSS Solver‐On‐Demand for Package and PCB Characterization Using

© 2011 ANSYS, Inc. September 6, 20111

HFSS Solver‐On‐Demand for Package and PCB Characterization Using Cadence

Greg Pitner


Problem Statement

• Usually SI engineers extract only the package or the pcb due to the trade‐offs between capacity and simulation time

• For high speed channels, it is important to combine the package and pcb to capture the transitions in 3D

• Merging multi‐layer package and pcb in 3D can be cumbersome


Agenda

• Introduce HFSS in Cadence – a HFSS Solver on Demand Technology

• Demonstrate ease of use of HFSS in Cadence for high speed I/O analysis using Xilinx Virtex6 package and pcb

• Process package and pcb models from Cadence environment

• Merge package on to pcb and extract the model by means of HFSS Solver on Demand

• Exhibit the macro modeling ability within Designer through Network Data Explorer

• Demonstrate the new IBIS AMI importer which streamlines usage of IBIS AMI driver/receiver models

• Evaluate high speed channel performance with IBIS AMI driver/receiver models through eye diagrams


HFSS in Cadence Enables More Robust 3D Investigation

• Today, we will show the advances that we have made in our Solver on Demand capabilities which enable

– The solving of larger 3D models to determine optimal performance – The ability to add and solve manufacturing variations to the 3D model

+ =


HFSS in Cadence – Automation and Ease of Use

• Select nets of interest– Signal, Power and Ground

• Draw extents to export selected portions of package or pcb

• Create ports on signal nets• Specify HFSS solution setup• Specify HFSS airbox extents


HFSS in Cadence Package ‐ Select Nets and Determine Extents


HFSS in CadencePackage ‐ Automatic Port Creation


HFSS in CadencePackage ‐ Airbox Extents and HFSS Solution Setup


Package Model in Designer

2D Layout ViewStackup Editor


HFSS in Cadence Board ‐ Select Signals and Draw Extents


HFSS in CadenceBoard ‐ HFSS Solve Settings


Board Model in Designer

2D Layout View Stackup Editor


Create PCB Ports in Designer

Select Trace Edges in Layout

Automatically creates coupled waveport


Merge Package on to PCB

Package layout is now a sub‐circuit of the board cutoutPackage stackup is

independent of the PCB

Package placement layer and position can be specified in the Footprint


Merged Package and PCB Cutouts

2D Layout View 3D Layout View


Enable Package Ports in Schematic

Port1:PCIE_RX2P_T2 Port1:PCIE_RX2N_T2Port1:PCIE_RX3P_T2 Port1:PCIE_RX3N_T2 Port9:PCIE_TX2P_T2Port9:PCIE_TX2N_T2

Port9:PCIE_TX3P_T2Port9:PCIE_TX3N_T2

MGTRXP0_BumpMGTTXP0_Bump

MGTRXN0_BumpMGTTXN0_Bump

MGTRXP1_BumpMGTTXP1_Bump

MGTRXN1_BumpMGTTXN1_Bump

Pkg Sub Circuit

PCB Ports

Port1:PCIE_RX2P_T2 Port1:PCIE_RX2N_T2_RX3P_T2 Port1:PCIE_RX3N_T2 Port9:PCIE_TX2P_T2Port9:PCIE_TX2N_T2Port9:Port9:PCIE_TX3N_T2

MGTRXP0_BumpMGTTXP0_BumpMGTRXN0_BumpMGTTXN0_BumpMGTRXP1_BumpMGTTXP1_BumpMGTRXN1_BumpMGTTXN1_Bump

MGTRXP0_Bump MGTTXP0_BumpMGTRXN0_Bump MGTTXN0_Bump

MGTRXP1_Bump MGTTXP1_BumpMGTRXN1_Bump MGTTXN1_Bump


Analyze Model from Designer (HFSS Solver‐on‐Demand)


Export to 3D HFSS Model from Designer


Differential Insertion and Return Loss Insertion Loss

Return Loss


Agenda – Part 1

• Introduce HFSS in Cadence – a HFSS Solver on Demand Technology

• Demonstrate ease of use of HFSS in Cadence for high speed I/O analysis using Xilinx Virtex6 package and pcb

• Process package and pcb models from Cadence environment

• Merge package on to pcb and extract the model by means of HFSS Solver on Demand

• Exhibit the macro modeling ability within Designer through Network Data Explorer

• Demonstrate the new IBIS AMI importer which streamlines usage of IBIS AMI driver/receiver models

• Evaluate high speed channel performance with IBIS AMI driver/receiver models through eye diagrams


Macro‐modeling Functionality

Circuit Simulation• Designer• Simplorer• Other• State‐space fitting

• Passivity enforcement• Passivity checker• S‐parameter visualization• S‐matrix reduction• Macro‐model generation

HFSS

SIwave

Q3D

Network Data Explorer

Designer

• State‐space• Simplorer• Spectre• HSPICE• PSPICE

Measured Data

New functionality for the SI market


Network Data Explorer


Network Data Explorer• The S‐Parameter data can be converted to

a macro model for use with circuit simulation in multiple formats:

Advanced features

New!

Use perturbation when s‐parameter model has many ports (>10)

Default (fast but memory intensive)


IBIS AMI

AMI stands for Algorithmic Modeling Interface

It allows users to specify their own transmitter and receiver models as C‐interface compiled libraries

• Designer supports Matlab as well as compiled DLLs• faster signal processing algorithms• intellectual property protection

Mainly used in convolution (fast) transient engines for channel simulation• Designed to be used with fixed time step data

Introduced in IBIS 5.0 specs• http://eda.org/pub/ibis/ver5.0/ver5_0.txt• IBIS stand for “I/O Buffer Information Specification”; high‐level buffer specification for circuit

modeling• In these specs the library is specified inside the IBIS wrapper and the interface is called IBIS‐

AMI• In fact, AMI concept is independent of IBIS


New AMI Import Process

Import from .ibs file or specific .ami file directly


New AMI Import Process

• Automatically fill out fields for .dll and .so models • Test button runs IBIS committee parser and reports pass/fail• Advanced option used to set up models with non‐standard behavior


Advanced Options Form (Optional)

Model parameter tree

Sample Parameters string

Test results details


Imported Component

AMI model parameters can be sweep able component parameters upon import

AM

IS

ource

ID=192

Tx Rx


Schematic and Setup for AMI Analysis

0

00

50

R6

50

R9

AMI

Source

ID=26

AMI

Probe

ID=32

Port1Port2Port3Port4Port5Port6Port7Port8

Port9Port10Port11Port12Port13Port14Port15Port16

50

R149

50

R150

50

R151

50

R152

50

R153

50

R154

50

R155

50

R156

50

R157

50

R158

50

R159

50

R160

1

2

Pkg on PCB model from HFSS Solver on Demand

15 inches long striplinedifferential pair from Designer library

Makes use of GPU card


Eye Opening Before Receiver


Eye Opening After Receiver DFE


Conclusions

• HFSS in Cadence enables SI engineers to setup and solve package and pcbmodels in 3D using HFSS

• Designer provides a complete framework to – Import ready to solve models from third party layout– Enables HFSS Solver on Demand to solve HFSS models– Check for passivity and causality to determine quality of S parameters and W

elements– Enforce passivity and causality on S parameters and W elements– Greatly simplify the reading and execution of AMI models for transmitter and

receivers through the new AMI importer– Validate channel performance with statistical eye diagrams and various eye

measurements

• HFSS in Cadence (a Solver on Demand feature) greatly enhances productivity of an SI engineer

Documents

HFSS Solver On Demand for Package and PCB · PDF fileHFSS Solver‐On‐Demand for Package and PCB Characterization Using