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UNIT I
BINARY SYSTEMS
1. DIGITAL SYSTEMS,BINARY NUMBERS & NUMBER BASE CONVERSION
A digital system can understand positional number system only where there are a few symbols called digits and these symbols represent different values depending on the position they occupy in the number.A value of each digit in a number can be determined using The digit The position of the digit in the number The base of the number system (where base is defined as the total number of digits available in the number system).The term digital refers to the fact that the signal is limited to only a few possible values. In general, digits signals are represented by only two possible voltages on a wire - 0 volts (which we called "binary 0", or just "0") and 5 volts (which we call "binary 1", or just "1"). We sometimes call these values "low" and "high", or "false" and "true".
Definition:
A digital system is an interconnection of digital modules and it is system that manipulates discrete elements of information that is represented internally in the binary form.
Characteristics of digital system:1. Digital systems manipulate elements of information2. Discrete elements are nothing but the digits such as 10 decimal digits ,26 letters of
alphbets 3. Digital systems use physical quantities called signals to represent discrete elements.4. In digital systems, the signals have two discrete values & therefore said to be binary.5. A signal in digital system represents one binary digit called a bit, the bit has value
either 0 or 1.6. Discrete elements of information are represented with group of bits called binary
codes.
Advantages of digital system:1. Dramatic cost reductions in digital devices have come about because of advances in
digital
integrated circuit technology.2. Equipment built with digital integrated circuits can perform at a speed of hundreds of
millions of operations per second.3. Digital systems can be made to operate with extreme reliability by using error
correcting codes.
Decimal Number System
The number system that we use in our day-to-day life is the decimal number system. Decimal number system has base 10 as it uses 10 digits from 0 to 9. In decimal number system, the successive positions to the left of the decimal point represent units, tens, hundreds, thousands and so on.Each position represents a specific power of the base (10). For example, the decimal number 1234 consists of the digit 4 in the units position, 3 in the tens position, 2 in the hundreds position, and 1 in the thousands position, and its value can be written as
(1×1000) + (2×100) + (3×10) + (4×l) (1×103) + (2×102) + (3×101) + (4×l00) = 1000 + 200 + 30 + 1 = 1234
Number System & Description
1 Binary Number System Base 2. Digits used: 0, 12 Octal Number System Base 8. Digits used: 0 to 73 Hexadecimal Number System Base 16. Digits used: 0 to 9, Letters used: A- F
Binary Number System
Characteristics Uses two digits, 0 and 1. Also called base 2 number system Each position in a binary number represents a 0 power of the base (2). Example: 20
Last position in a binary number represents an x power of the base (2). Example: 2x
where x represents the last position - 1.
ExampleBinary Number: 101012
Calculating Decimal Equivalent −Step Binary Number Decimal NumberStep 1 101012 ((1 × 24) + (0 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10
Step 2 101012 (16 + 0 + 4 + 0 + 1)10
Step 3 101012 2110
Note: 101012 is normally written as 10101.
Octal Number SystemCharacteristics Uses eight digits, 0,1,2,3,4,5,6,7. Also called base 8 number system Each position in an octal number represents a 0 power of the base (8). Example: 80
Last position in an octal number represents an x power of the base (8). Example: 8x
where x represents the last position - 1.
ExampleOctal Number − 125708
Calculating Decimal Equivalent Step Octal Number Decimal NumberStep 1 125708 ((1 × 84) + (2 × 83) + (5 × 82) + (7 × 81) + (0 × 80))10
Step 2 125708 (4096 + 1024 + 320 + 56 + 0)10
Step 3 125708 549610
Note: 125708 is normally written as 12570.
Hexadecimal Number SystemCharacteristics Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F. Letters represents numbers starting from 10. A = 10, B = 11, C = 12, D = 13, E = 14, F = 15. Also called base 16 number system.
Each position in a hexadecimal number represents a 0 power of the base (16). Example 160. Last position in a hexadecimal number represents an x power of the base (16). Example
16x where x represents the last position - 1.Example −Hexadecimal Number: 19FDE16
Calculating Decimal Equivalent −
StepBinary Number
Decimal Number
Step 1 19FDE16((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E × 160))10
Step 2 19FDE16((1 × 164) + (9 × 163) + (15 × 162) + (13 × 161) + (14 × 160))10
Step 3 19FDE16 (65536 + 36864 + 3840 + 208 + 14)10
Step 4 19FDE16 10646210
Note − 19FDE16 is normally written as 19FDE.
Number Base Conversions
There are many methods or techniques which can be used to convert numbers from one base to another. We'll demonstrate here the following −
Decimal to Other Base System
Other Base System to Decimal
Other Base System to Non-Decimal
Shortcut method − Binary to Octal
Shortcut method − Octal to Binary
Shortcut method − Binary to Hexadecimal
Shortcut method − Hexadecimal to Binary
Decimal to Other Base SystemTwo methods
. 1) For integer part using successive division method. 2) For fractional part using successive multiplication method.
Decimal to binaryExample −Decimal Number: 2910
Calculating Binary Equivalent −Step Operation Result RemainderStep 1 29 / 2 14 1Step 2 14 / 2 7 0Step 3 7 / 2 3 1Step 4 3 / 2 1 1Step 5 1 / 2 0 1
As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder becomes the Least Significant Digit (LSD) and the last remainder becomes the Most Significant Digit (MSD).
Decimal Number − 2910 = Binary Number − 111012.
Octal to decimal conversion:
Ex: Convert 4057.068 to octal
= 4x83+0x82+5x81+7x80+0x8-1+6x8-2
= 2048+0+40+7+0+0.093 = 2095.093710
Other Base System to Decimal System Steps
Step 1 − Determine the column (positional) value of each digit (this depends on the position of the digit and the base of the number system).
Step 2 − Multiply the obtained column values (in Step 1) by the digits in the corresponding columns.
Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in decimal.
Example Binary Number − 111012
Calculating Decimal Equivalent −
Step Binary Number Decimal NumberStep 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10
Step 2 111012 (16 + 8 + 4 + 0 + 1)10
Step 3 111012 2910
Binary Number − 111012 = Decimal Number − 2910
Hexadecimal to Decimal conversion:
Ex: 5C716 to decimal
(5x162)+(C x161)+ (7 x160) = 1280+192+7.= 14710
Other Base System to Non-Decimal System Steps
Step 1 − Convert the original number to a decimal number (base 10). Step 2 − Convert the decimal number so obtained to the new base number.ExampleOctal Number − 258
Calculating Binary Equivalent −Step 1 − Convert to Decimal
Step Octal Number Decimal NumberStep 1 258 ((2 × 81) + (5 × 80))10
Step 2 258 (16 + 5 )10
Step 3 258 2110
Octal Number − 258 = Decimal Number − 2110
Step 2 − Convert Decimal to BinaryStep Operation Result RemainderStep 1 21 / 2 10 1Step 2 10 / 2 5 0Step 3 5 / 2 2 1Step 4 2 / 2 1 0Step 5 1 / 2 0 1
Decimal Number − 2110 = Binary Number − 101012
Octal Number − 258 = Binary Number – 1010
Binary to Octal conversion:
Starting from the binary pt. make groups of 3 bits each, on either side of the binary pt, & replace each 3 bit binary group by the equivalent octal digit.
Convert 110101.1010102 to octal Group of 3
110 101. 101 010
6 5 . 5 2
Hexadecimal to binary:Replace each hex digit by its 4-bit binary group.Ex: 4BAC10 to binary
=01001011101011002Shortcut method - Binary to Octal
Steps
Step 1 − Divide the binary digits into groups of three (starting from the right). Step 2 − Convert each group of three binary digits to one octal digit.Example
Binary Number − 101012
Calculating Octal Equivalent −Step Binary Number Octal NumberStep 1 101012 010 101Step 2 101012 28 58
Step 3 101012 258
Binary Number − 101012 = Octal Number − 258
Shortcut method - Octal to Binary Steps
Step 1 − Convert each octal digit to a 3 digit binary number (the octal digits may be treated as decimal for this conversion).
Step 2 − Combine all the resulting binary groups (of 3 digits each) into a single binary number.
ExampleOctal Number − 258
Calculating Binary Equivalent –
Step Octal Number Binary NumberStep 1 258 210 510
Step 2 258 0102 1012
Step 3 258 0101012
Octal Number − 258 = Binary Number − 101012
=65.528
4 B A C0100 1011 1010 1100
Shortcut method - Binary to Hexadecimal Step 1 − Divide the binary digits into groups of four (starting from the right).
Step 2 − Convert each group of four binary digits to one hexadecimal symbol.
Example
Binary Number − 101012
Calculating hexadecimal Equivalent –
Step Binary Number Hexadecimal Number
Step 1 101012 0001 0101
Step 2 101012 110 510
Step 3 101012 1516
Binary Number − 101012 = Hexadecimal Number − 1516
Shortcut method - Hexadecimal to Binary Step 1 − Convert each hexadecimal digit to a 4 digit binary number (the hexadecimal
digits may be treated as decimal for this conversion).
Step 2 − Combine all the resulting binary groups (of 4 digits each) into a single
binary number.
Example: Hexadecimal Number − 1516
Calculating Binary Equivalent −
Step Hexadecimal Number Binary Number
Step 1 1516 110 510
Step 2 1516 00012 01012
Step 3 1516 000101012
Hexadecimal Number − 1516 = Binary Number − 101012
QUESTIONS:
1. Convert the decimal number 250.5 to base 2, base4, base7, base8 & base16.
2. Convert the binary 1110001.110 to decimal, octal, & hexadecimal.3. Convert the hexadecimal 2AC5.D to decimal, octal & binary.
4. Convert the octal 623.55 to decimal, binary & hexadecimal.5. List the first 16 numbers in base 12. Use the letters A and B to represent
two digits.6. Determine the base of the numbers in each case for the following
operations to be correct: (a) 14/2= 5, (b) 54/4 = 13, (c) 24 + 17 = 40, d) (211)x=(152)8.
7. Find the 16's complement of B2FA. 8. What is the largest binary number that can be expressed with 14 bits?
What are the equivalent decimal and hexadecimal numbers?
2. COMPLEMENTS & SIGNED BINARY NUMBERS
Complements
Complements are used in the digital computers in order to simplify the subtraction
operation and for the logical manipulations. For each radix-r system (radix r represents
base of number system) there are two types of complements.
S.N
.Complement Description
1 Radix ComplementThe radix complement is referred to as the r's
complement
2 Diminished Radix ComplementThe diminished radix complement is referred to
as the (r-1)'s complement
Binary system complementsAs the binary system has base r = 2. So the two types of complements for the binary
system are 2's complement and 1's complement.
1's complement
The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This
is called as taking complement or 1's complement. Example of 1's Complement is as
follows.
2's complement
The 2's complement of binary number is obtained by adding 1 to the Least Significant Bit
(LSB) of 1's complement of the number.
2's complement = 1's complement + 1
Example of 2's Complement is as follows.
Binary arithmetic is essential part of all the digital computers and many other digital system. 9’s & 10’s Complements:
It is the Subtraction of decimal no.s can be accomplished by the 9‘s & 10‘s compliment methods similar to the 1‘s & 2‘s compliment methods of binary . the 9‘s compliment of a decimal no. is obtained by subtracting each digit of that decimal no. from 9. The 10‘s compliment of a decimal no is obtained by adding a 1 to its 9‘s compliment.
Example: 9‘s compliment of 3465 and 782.54 is 9999 999.99
-3465 -782.54---------- -----------6534 217.45
10‘s complement of 4069 is 9999
- 4069---------- 5930
+1---------- 5931-----------
SIGNED BINARY NUMBERS:
There are three ways of representing signed binary numbers.
1. signed-magnitude representation
2. signed 1’s complement representation
3. signed 2’s complement representation
1. signed-magnitude representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and remaining bits represents magnitude.
2. signed 1’s complement representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and the magnitude represents in1’s complement form.
3. signed 2’s complement representation: In this representation the most significant bit indicates the sign, if it is 0 that represents +ve number & if it is 1 that represents –ve number and the magnitude represents in2’s complement form.
UNSIGNED BINARY NUMBERS
Binary Addition and Binary SubtractionIt is a key for binary subtraction, multiplication, division. There are four rules of binary addition.
In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in the given column and a carry of 1 over to the next column.
Example − Addition
Subtraction and Borrow, these two words will be used very frequently for the binary subtraction. There are four rules of binary subtraction.
Example − Subtraction
Binary subtraction A − B can be executed by Adding A with two’s complement of B, provided we use two’s complementation for representation − ve numbers
Example: Find 129 − 128
0000 0000 1000 0001 [= +129 d ] 1111 1111 1000 0000 [= − 128 d ] -------------------------------------------0000 0000 0000 0001 [= + 1 d ]
Example Find + 16392 − (16392)
A= +16392 0100 0000 0000 1000 −B= −16392 1011 1111 1111 1000 --------------------------------------------------A + ( − B) 0000 0000 0000 0000
Example: Find +1020 − ( − 1017) 1111 1100 0000 0111 [ − 1017 d ]
0000 0011 1111 1001 [ − ( − 1017) d ] [+1017d] 0000 0011 1111 1100 [= +1020 d ] 0000 0111 1111 0101 [= +2037 d ]
Example: Find − 1017 − ( − 1020)1111 1100 0000 0111 [ − 1017 d ] 0000 0011 1111 1100 [ − ( − 1020) d ] --------------------------------------------------0000 0000 0000 0011 [= +3 d ]
Binary MultiplicationBinary multiplication is similar to decimal multiplication. It is simpler than decimal
multiplication because only 0s and 1s are involved. There are four rules of binary multiplication.
Example − Multiplication
Binary DivisionBinary division is similar to decimal division. It is called as the long division procedure.
Example − Division
QUESTION
1. Obtain the 1’s complement and 2’s complement of the following binary numbersi) 101010001 ii) 00001001 iii) 1000111110
2. Obtain the 9’s complement and 10’s complement of the following numbersi) 13579 ii) 90090 iii) 00000
3. Perform the subtraction with the following decimal numbers using 10’s complementAnd 9’s complement. a) 5250-321 b) 753-864 c) 3570-2100
4. Find the 16's complement of B2FA.5. Convert decimal + 46 and + 29 to binary. using the signed-2' complement
representation and enough digits to accommodate the numbers. Then perform the binary equivalent of(+ 29) + (-49 ), ( - 29) + (+49) . and ( - 29) + ( - 49) . Convert the answers back In decimal and verify that they are correct.
4. BINARY CODES & BINARY STORAGE & REGISTERS
Binary codes
In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the number, letter or word is being encoded. The group of symbols is called as a code. The digital data is represented, stored and transmitted as group of binary bits. This group is also called as binary code. The binary code is represented by the number as well as alphanumeric letter.
Advantages of Binary Code
Following is the list of advantages that binary code offers.
Binary codes are suitable for the computer applications.
Binary codes are suitable for the digital communications.
Binary codes make the analysis and designing of digital circuits if we use the binary codes.
Since only 0 & 1 are being used, implementation becomes easy.
Classification of binary codes
The codes are broadly categorized into following four categories.
Weighted Codes Non-Weighted Codes Binary Coded Decimal Code Alphanumeric Codes Error Detecting Codes Error Correcting Codes
Weighted CodesWeighted binary codes are those binary codes which obey the positional weight
principle. Each position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits.
Non-Weighted Codes
In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are Excess-3 code and Gray code.
Excess-3 codeThe Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in 8421. The excess-3 codes are obtained as follows −
Example
Excess-3 Addition:Add the xs-3 no.s by adding the 4 bit groups in each column starting from the
LSD. If there is no carry starting from the addition of any of the 4-bit groups , subtract 0011 from the sum term of those groups ( because when 2 decimal digits are
added in xs-3 & there is no carry , result in xs-6). If there is a carry out, add 0011 to the sum term of those groups( because when there is a carry, the invalid states are skipped and the result is normal binary).
Excess -3 (XS-3) Subtraction:Subtract the xs-3 no.s by subtracting each 4 bit group of the subtrahend from the corresponding 4 bit group of the minuend starting form the LSD .if there is no borrow from the next 4-bit group add 0011 to the difference term of such groups (because when decimal digits are subtracted in xs-3 & there is no borrow , result is normal binary). I f there is a borrow , subtract 0011 from the differenceterm(b coz taking a borrow is equivalent to adding six invalid states , result is in xs-6)
Gray CodeIt is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation.
Application of Gray code Gray code is popularly used in the shaft position encoders. A shaft position encoder produces a code word which represents the angular position
of the shaft.
Binary to Gray conversion:
N bit binary no is represented by Bn Bn-1 ------- B1
Gray code equivalent is by Gn Gn-1 ------- G1
Bn,, Gn are the MSB‘s then the gray code bits are obtained from the binary code as
Gn=Bn Gn-1=Bn Bn-1 Gn-2=Bn- 1 Bn-2 ----------- G1=B2 B1
EX-OR symbol
Procedure: ex-or the bits of the binary no with those of the binary no shifted one position to the right . The LSB of the shifted no. is discarded & the MSB of the gray code no.is the same as the MSB of the original binary no.
Gray to Binary Conversion:If an n bit gray no. is represented by Gn Gn-1 ------- G1Its binary equivalent by Bn Bn-1 ------- B1 then the binary bits are obtained from gray bits as
Bn= Gn Bn-1=Bn Gn-1 Bn-2= Bn-1 Gn-2 ------- G1= B2 G1
To convert no. in any system into given no. first convert it into binary & then binary to gray. To convert gray no into binary no & convert binary no into require no system.
Ex: 10110010(gray) = 110111002= DC16=3348=22010
EX:1101 Gray: 1 1 0 1
Binary: 1 0 0 1
Binary Coded Decimal (BCD) codeIn this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we can
represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.
Advantages of BCD Codes It is very similar to decimal system. We need to remember binary equivalent of decimal numbers 0 to 9 only.
Disadvantages of BCD Codes
The addition and subtraction of BCD have different rules. The BCD arithmetic is little more complicated. BCD needs more number of bits than binary to represent the decimal number. So
BCD is less efficient than binary.
8421 BCD code (Natural BCD code):Each decimal digit 0 through 9 is coded by a 4 bit binary no. called natural binary codes. Because of the 8,4,2,1 weights attached to it. It is a weighted code & also sequential . it is useful for mathematical operations. The advantage of this code is its case of conversion to & from decimal. It is less efficient than the pure binary, it require more bits.Ex: 14 1110 in binary But as 0001 0100 in BCD code.The disadvantage of the BCD code is that, arithmetic operations are more complex than they are in pure binary. There are 6 illegal combinations 1010, 1011, 1100,1101,1110,1111 in these codes; they are not part of the 8421 BCD code system. The disadvantage of 8421 code is, the rules of binary addition 8421 no, but only to the individual 4 bit groups.BCD Addition:It is individually adding the corresponding digits of the decimal no,s expressed in 4 bit binary groups starting from the LSD . If there is no carry & the sum term is not an illegal code , no correction is needed .If there is a carry out of one group to the next group or if the sum term is an illegal code then 610(0100) is added to the sum term of that group & the resulting carry is added to the next group.
Ex: Perform decimal additions in 8421 code (a)25+13
In BCD 25= 0010 0101In BCD +13 =+ 0001 0011
38 0011 1000No carry, no illegal code .This is the corrected sum (b). 679.6 + 536.8
679.6 = 0110 0111 1001 .0110 in BCD+536.8 = +0101 0011 0010 .1000 in BCD _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1216.4 1011 1010 0110 . 1110 illegal codes+0110 + 0011 +0110 . + 0110 add 0110 to each
(1)0001 (1)0000 (1)0101 . (1)0100 propagate carry/
+1/
+1/
+1/
+1
0001 0010 0001 0110 . 0100 1 2 1 6 . 4
BCD Subtraction:Performed by subtracting the digits of each 4 bit group of the subtrahend the digits from the corresponding 4- bit group of the minuend in binary starting from the LSD . if there is no borrow from the next group , then 610(0110)is subtracted from the difference term of this group.
(a)38-15
In BCD 38= 0011 1000In BCD -15 = -0001 0101
23 0010 0011No borrow, so correct difference.
Alphanumeric codes
A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not enough for communication between two computers because there we need many more symbols for communication. These symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols.
The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information. An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e. total 36 items. The following three alphanumeric codes are very commonly used for the data representation.
American Standard Code for Information Interchange (ASCII). Extended Binary Coded Decimal Interchange Code (EBCDIC). Five bit Bardot Code.
ASCII code table
ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more commonly used worldwide while EBCDIC is used primarily in large IBM computers.
Error Codes
There are binary code techniques available to detect and correct data during data transmission.
ERROR DETECTING CODES:
When binary data is transmitted & processed, it is susceptible to noise that can alter or distort its contents. The 1‘s may get changed to 0‘s & 1‘s .because digital systems must be accurate to the digit, error can pose a problem. Several schemes have been devised to detect the occurrence of a single bit error in a binary word, so that whenever such an error occurs the concerned binary word can be corrected & retransmitted.
Parity: The simplest techniques for detecting errors is that of adding an extra bit known as parity bit to each word being transmitted. Two types of parity: Odd parity, even parity for odd parity, the parity bit is set to a ‗0‘or a ‗1‘a t the transmitter such that the total no. of 1 bit in the word including the parity bit is an odd no.For even parity, the parity bit is set to a ‗0‘or a ‗1‘at the transmitter such that the parity bit is an even no.
Decimal 8421 code Odd parity Even parity0 0000 1 01 0001 0 12 0010 0 13 0011 1 04 0100 0 15 0100 1 06 0110 1 07 0111 0 18 1000 0 19 1001 1 0
When the digit data is received. a parity checking circuit generates an error signal if the total no of 1‘s is even in an odd parity system or odd in an even parity system. This parity check can always detect a single bit error but cannot detect 2 or more errors with in the same word. Odd parity is used more often than even parity does not detect the situation. Where all 0‘s are created by a short ckt or some other fault condition.
Ex: Even parity scheme(a) 10101010 ( b) 11110110 (c) 10111001
Ans:(a) No. of 1‘s in the word is even is 4 so there is no error(b) No. of 1‘s in the word is even is 6 so there is no error(c) No. of 1‘s in the word is odd is 5 so there is error
Ex: odd parity(a)10110111 (b) 10011010 (c)11101010
Ans:(a) No. of 1‘s in the word is even is 6 so word has error(b) No. of 1‘s in the word is even is 4 so word has error
(c) No. of 1‘s in the word is odd is 5 so there is no error
Error –Correcting Codes:A code is said to be an error –correcting code, if the code word can always be deduced from an erroneous word. For a code to be a single bit error correcting code, the minimum distance of that code must be three. The minimum distance of that code is the smallest no. of bits by which any two code words must differ. A code with minimum distance of 3 can‘t only correct single bit errors but also detect (can‘t correct) two bit errors, The key to error correction is that it must be possible to detect & locate erroneous that it must be possible to detect & locate erroneous digits. If the location of an error has been determined. Then by complementing the erroneous digit, the message can be corrected , error correcting , code is the Hamming code , In this , to each group of m information or message or data bits, K parity
checking bits denoted by P1,P2,----------pk located at positions 2 k-1 from left are added to form an (m+k) bit code word.
To correct the error, k parity checks are performed on selected digits of each code word, & the position of the error bit is located by forming an error word, & the error bit is then complemented. The k bit error word is generated by putting a 0
or a 1 in the 2 k-1th position depending upon whether the check for parity involving the parity bit Pk is satisfied or not.Error positions & their corresponding values :
7-bit Hamming code:
To transmit four data bits, 3 parity bits located at positions 20 21&22 from left are added to make a 7 bit code word which is then transmitted.
The word format
P1 P2 D3 P4 D5 D6 D7
D—Data bits P-Parity bits
Ex: Encode the data bits 1101 into the 7 bit even parity Hamming Code The bit pattern is
P1 P2 D3 P4 D5 D6 D71 1 0 1
Bits 1,3,5,7 (P1 111) must have even parity, so P1 =1 Bits 2, 3, 6, 7 (P2 101) must have even parity, so P2=0 Bits 4,5,6,7 (P4 101)must have even parity, so P4=0
The final code is 1010101
15-bit Hamming Code: It transmit 11 data bits, 4 parity bits located 20 21 22 23
Word format is
P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12 D13 D14 D15
12-Bit Hamming Code: It transmit 8 data bits, 4 parity bits located at position 20 21 22 23 Word format is
P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12
Binary storage & Registers
A register is a memory device that can be used to store more than one bit of information.
A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register.
Common refers to the property that the control signals apply to all flip-flops in the same way A register is a generalization of a flip-flop. Where a flip- flop stores one bit, a register stores several bits The main operations on a register are the same as for any storage devices, namelyLoad or Store: Put new data into the register
Read: Retrieve the data stored in the register (usually without changing the stored data
QUESTIONS
1.Convert the following to binary and then to gray code.
(a) (1111)12 (b) (BC54)16 (c) (237)8 (d) (164)10
2. The following is a string of ASCII characters whose bit patterns have been converted into hexadecimal for compactness: 7J F4 E5 76 E5 fA EF 62 73. Of the eight bus in each pair of digits the leftmost is a parity bit. The remaining bits are the ASCII code.(a) Convert the string to bit form and decode the ASCII.
(b) Determine the parity used : odd or even ?
3. The state of a 12·bit register is 1000 100 1011 1.What is its content if it represents
(a) three decimal digits in BCD?
(b) three decimal digits in the excess-3 code ?
(c) three decimal digit in the 84-2-1 code ?
(d) a binary number?
4. What bit must be complemented to change an ASCII letter from capital to lowercase and vice-versa?
BOOLEAN ALGEBRA & LOGIC GATES5. BASIC DEFINITIONS, AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA, BASIC PROPERTIES OF BOOLEAN ALGEBRA
Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical Algebra. Boolean algebra was invented by George Boole in 1854.
Rule in Boolean Algebra Following are the important rules used in Boolean algebra.
Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.
Complement of a variable is represented by an overbar (-). Thus, complement of variable B is represented as . Thus if B = 0 then = 1 and B = 1 then = 0.
ORing of the variables is represented by a plus (+) sign between them. For example ORing of A, B, C is represented as A + B + C.
Logical ANDing of the two or more variable is represented by writing a dot between them such as A.B.C. Sometime the dot may be omitted like ABC.
Boolean Laws There are six types of Boolean Laws.
Commutative law Any binary operation which satisfies the following expression is referred to as commutative operation.
Commutative law states that changing the sequence of the variables does not have any effect on the output of a logic circuit.
Associative law This law states that the order in which the logic operations are performed is irrelevant as their effect is the same.
Distributive lawDistributive law states the following condition.
AND lawThese laws use the AND operation. Therefore they are called as AND laws.
OR law These laws use the OR operation. Therefore they are called as OR laws.
INVERSION lawThis law uses the NOT operation. The inversion law states that double inversion of variable results in the original variable itself.
AXIOMS & Laws of Boolean Algebra:Axioms or Postulates are a set of logical expressions i.e, without proof. & also we can build a set of useful theorems. Each axiom can be interpreted as the outcome of an operation performed by a logic gate.
AND OR NOT0.0=0 0+0=0 1=00.1=0 0+1=1 0=11.0=0 1+0=11.1=1 1+1=1
Simplification Using Algebraic FunctionsIn this approach, one Boolean expression is minimized into an equivalent expression by applying Boolean identities.Problem 1Minimize the following Boolean expression using Boolean identities −
F(A,B,C)=A′B+BC′+BC+AB′C′F(A,B,C)=A′B+BC′+BC+AB′C′SolutionGiven, F(A,B,C)=A′B+BC′+BC+AB′C′ F(A,B,C)=A′B+(BC′+BC′)+BC+AB′C′ [By idempotent law, BC’ = BC’ + BC’]F(A,B,C)=A′B+(BC′+BC)+(BC′+AB′C′)
F(A,B,C)=A′B+B(C′+C)+C′(B+AB′) [By distributive laws]F(A,B,C)=A′B+B.1+C′(B+A) [ (C' + C) = 1 and absorption law (B + AB')= (B + A)]F(A,B,C)=A′B+B+C′(B+A) [ B.1 = B ]F(A,B,C)=B(A′+1)+C′(B+A)F(A,B,C)=B.1+C′(B+A) [ (A' + 1) = 1 ]F(A,B,C)=B+C′(B+A) [ As, B.1 = B ]F(A,B,C)=B+BC′+AC′F(A,B,C)=B(1+C′)+AC′F(A,B,C)=B.1+AC′ [As, (1 + C') = 1]F(A,B,C)=B+AC′ [As, B.1 = B]
F(A,B,C)=B+AC′ is the minimized form.
Problem 2Minimize the following Boolean expression using Boolean identities −
F(A,B,C)=(A+B)(B+C)F(A,B,C)=(A+B)(B+C)SolutionGiven, F(A,B,C)=(A+B)(A+C)F(A,B,C)=A.A+A.C+B.A+B.C [Applying distributive Rule]F(A,B,C)=A+A.C+B.A+B.C [Applying Idempotent Law]F(A,B,C)=A(1+C)+B.A+B.C [Applying distributive Law]F(A,B,C)=A+B.A+B.C [Applying dominance Law]F(A,B,C) = (A+1).A+B.C [Applying distributive Law]F(A,B,C)=1.A+B.C [Applying dominance Law]F(A,B,C)=A+B.CSo, F(A,B,C)=A+BC is the minimized form.
QUESTIONS1. Simplify the following Bo Simplify the following Boolean expressions to minimum
no. of literals.i. ABC+A’B+ABC’ii. (BC’+A’D)(AB’+CD’)
2. Obtain the Dual of the following Boolean expressions.i. AB+A(B+C)+B’(B+D)ii. A’B+A’BC’+A’BCD+A’BC’D’Eiii. ABEF+ABE’F’+A’B’EF
3. Simplify the following Boolean expression:
(i) F = (A+B)(A’+C)(B+C). (ii) F = A+B+C’+D (E+F)
4. Simplify the following expression Y = (A + B) (A + C’) (B' + C’)
5. BOOLEAN FUNCTIONS, CANONICAL AND STANDARD FORMS
Boolean functions & their representation:
A function of n Boolean variables denoted by f(x1,x2,x3------xn) is another variable denoted by & takes one of the two possible values 0 & 1.The various way of represent a given function is1. Sum of Product (SOP) form: It is called the Disjunctive Normal Form (DNF) Ex: f(A,B,C)=(A B+B C)2. Product of Sums (POS) form: It is called the Conjunctive Normal Form (CNF). Ex: f(A,B,C)=( A+ B)(B+C)3. Truth Table form:The function is specified by listing all possible combinations of values assumed by the variables & the corresponding values of the function.
Example:
# A B C F0 0 0 0 01 0 0 1 12 0 1 0 03 0 1 1 14 1 0 0 15 1 0 1 06 1 1 0 17 1 1 1 1
Table 1 – Arbitrary function defined via Truth Table
A "product" in Boolean algebra is a logical AND operation while a "sum" is a logical OR operation.
Minterm
A "minterm" is a Boolean expression that is true for the minimum number of combinations of inputs.Because we want to minimize the coverage, we want to use the Boolean operation that is the most restrictive, which is the AND operation. Since the AND is true only if ALL of the inputs are True, we can craft an expression that is True for only a single combination of inputs by including each input in the product. If the input is uncomplemented, then we require that it be True, while if it is complemented, then we require it to be False. The minterm expression for each combination of inputs is therefore Keep in mind that each minterm is True only for the specific combination of inputs with which it is associated and is False for all others.
A B C minterm
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 2 - Table of Minterms
In order to be a minterm, the product must cover exactly one of the possible combination of inputs. To do this, each input must be present in either uncomplemented or complemented form. Consider the system of three inputs in the table above. We can combine the last two minterms, namely ABC'+ABC, into a single product, namely AB. Using this "simplifies" the expression and it is still in SOP form, but it is not a minterm.
If we have an expression that is in SOP form but is not in standard form and we need it to be, then we can simply expand each product by ANDing it with products that are constructed by ORing one of the missing inputs and its complement. Thus, we can expand AB back to minterm form as follows:
Maxterm
A "maxterm" is a Boolean expression that is True for the maximum number of combinations of inputs. Because we want to maximize the coverage, we want to use the Boolean operation that is the most permissive, which is the OR operation. While the OR is True if ANY of its inputs is True, for our purposes it is more convenient to recognize that the OR is False only if ALL of its inputs are False; thus, we can craft an expression that is False for only a single combination of inputs by including each input in the sum. If the input is uncomplemented, then we require that it be False, while if it is complemented, then we require it to be True. The maxterm expression for each combination of inputs is therefore Keep in mind that each maxterm is False only for the specific combination of inputs with which it is associated and is True for all others.
# A B C maxterm
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3 - Table of Maxterms
In order to be a maxterm, the sum must cover all but exactly one of the possible combination of inputs. To do this, each input must be present in either uncomplemented
or complemented form. Consider the system of three inputs in the table above. We can combine the last two maxterms, namely (A'+B'+C)(A'+B'+C'), into a single sum, namely (A'+B'). Using this "simplifies" the expression and it is still in POS form, but it is not a maxterm.
If we have an expression that is in POS form but is not in standard form and we need it to be, then we can simply expand each sum by ORing it with terms that are constructed by ANDing one of the missing inputs and its complement. Thus, we can expand (A'+B') back to maxterm form as follows:
The above equation may look odd but that is because while we are used to multiplication being distributable over addition (and thus AND being distributable over OR looks natural), we are used to addition not being distributable over multiplication. However, OR is distributable over AND, hence
In the above relation,
Relationship between Labels, Minterms, and Maxterms
Consider the minterm and maxterm for a particular row. Since the minterm is True ONLY when that input combination is asserted while the maxterm is False ONLY when that combination is asserted, it is clear that each minterm is the logical inverse of the corresponding maxterm (and vice versa, of course).
Standard SOP (Sum of Products)
As mentioned in the introduction, the SOP form takes on the appearance of being a sum of several terms, each of which is the product of several factors.To craft the SOP form of a Boolean logic function, we merely need to OR together the minterms associated with each combination of inputs for which the overall output should be True.By looking at
Table 1 we see that we need to sum the minterms associated with rows {1,3,4,6,7}. This is often represented simply as
Standard POS (Product of Sums)
As mentioned in the introduction, the POS form takes on the appearance of being a product of several factors, each of which is the sum of several terms.To craft the POS form of a Boolean logic function, we merely need to AND together the maxterms associated with each combination of inputs for which the overall output should be False. By looking at Table 1 we see that we need to take the product of the maxterms associated with rows {0',2',5'}. This is often represented simply as
6. LOGIC GATES, OTHER LOGIC OPERATIONS, INTEGRATED
CIRCUITS
LOGIC GATES Logic gates are the basic building blocks of any digital system. It is an electronic
circuit having one or more than one input and only one output. The relationship between the input and the output is based on certain logic. Based on this, logic gates are named as AND gate, OR gate, NOT gate etc.
AND GateA circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
OR GateA circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
NOT GateNOT gate is also known as Inverter. It has one input A and one output Y.
Logic diagram
Truth Table
NAND GateA NOT-AND operation is known as NAND operation. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
NOR GateA NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
XOR GateXOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or sometime as X-OR gate. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
XNOR GateXNOR gate is a special type of gate. It can be used in the half adder, full adder and subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has n input (n >= 2) and one output.
Logic diagram
Truth Table
Boolean Expression & Logic Diagrams:
Boolean expressions can be realized as hardware using logic gates. Conversely, hardware can be translated into Boolean expressions for the analysis of existing circuits.
1. Converting Boolean Expressions to Logic:
To convert, start with the output & work towards the input.
Assume the expression (AB)’+A+(B +C)’ is to be realized using AOI logic. Start with this expression. (AB)‘ is the output of an inverter whose inputs is AB and (B+C)‘ must be the output of an inverter whose input is B+C. so, those two inverters are as Since it is three terms, it must be the output of a three-input OR gates. So, draw an OR gate with three inputs as
Now AB must be output of a two-input AND gate whose inputs are A and B . And B+C must be the output of a two-input OR gate whose inputs are B and C. so, an AND gate and an OR gate are as
2. Converting Logic to Boolean Expressions:
To convert logic to algebra, start with the input signals and develop the terms of the Boolean expression until the output is reached.
Integrated circuits
An integrated circuit is one in which circuit components such as transistors, diodes, resistors, capacitors etc. are automatically part of a small semiconductor chip.
An integrated circuit consists of a number of circuit components (e.g. transistors, diodes, resistors etc.) and their inter connections in a single small package to per- form a complete electronic function. These components are formed and connected within a small chip of semi- conductor material. The following points are about integrated
circuits :
Advantages: Integrated circuits possess the following advantages over discrete circuits : Increased reliability due to lesser number of connections. Extremely small size due to the fabrication of various circuit elements Lesser weight and space requirement due to miniaturized circuit. Low power requirements. Greater ability to operate at extreme values of temperature. Low cost because of simultaneous production of hundreds of alike circuits on a small semi- conductor wafer.The circuit lay out is greatly simplified because integrated circuits are constrained to use minimum number of external connections.Disadvantages: The disadvantages of integrated circuits are :
If any component in an IC goes out of order, the whole IC has to be replaced by the new one.
In an IC, it is neither convenient nor economical to fabricate capacitances exceeding 30 pF.
It is not possible to fabricate inductors and transformers on the surface of semiconductor chip.
It is not possible to produce high power ICs (greater than 10 W). There is a lack of flexibility in an IC i.e., it is generally not possible to modify the
Parameters within which an integrated circuit will operate.QUESTIONS:
1. Implement Boolean functions F=xy+xy’+y’z using basic gates
2. Convert the following to the other canonical form
F(x,y,z)=∑(1,3,7)
3. Obtain the truth table of the function F= xy+xy’+y’z
4. Obtain the truth table of the following Boolean function and express the function as sum of minterms and product of maxterms F = (A+B) (B+C).
5. Convert the given expression in canonical SOP form Y = AC + AB + BC.6. Given two eight-bit strings A = 10110001 and B = 10101100, evaluate the eight-
bit result after the following logical operations: (a ) AND. (b) OR. (C)XOR. (d)NOT A, (e) NOT B .
7. Express the following function as a sum of minterms and as a product of maxterms:F(A ,B.C. D) = B'D + A'D + BD
UNIT II
GATE LEVEL MINIMIZATION
1.THE MAP METHOD, FOUR VARIABLE K-MAP, FIVE-VARIABLE K-MAP
Introduction to Karnaugh Maps
1. The Karnaugh map (or K-map) is a visual way of detecting redundancy in theSOP.
2. The K-map can be easily used for circuits with 2, 3, or 4 inputs.
3. It consists of an array of cells, each representing a possible combination of inputs.
4. The cells are arranged to that each cell’s input combination differs from adjacent cells by only a single bit.
5. This is called Gray code ordering – it ensures that physical neighbors are the array and are logical neighbors as well. (In other words, neighboring bit patterns are nearly the same, differing by only 1 bit).
Consider the following arrangements of cells:
2-input 3-input
a’@ b’ a’@ b a’@ b’@ c’ a’@ b’@ c a’@ b @ c a’@ b @ c’
00 01 000 001 011 010
a @ b’ a @ b a @ b’@ c’ a @ b’@ c a @ b @ c a @ b @ c’
10 11 100 101 111 110
4-input
a’@b’@c’@d’ a’@b’@c’@d a’@b’@c@d a’@b’@c@d’
0000 0001 0011 0010
a’@b@c’@d’ a’@b@c’@d a’@b@c@d a’@b@c@d’
0100 0101 0111 0110
a@b@c’@d’ a@b@c’@d a@b@c@d a@b@c@d’
1100 1101 1111 1110
a@b’@c’@d’ a@b’@c’@d a@b’@c@d a@b’@c@d’
1000 1001 1011 1010
The cells are arranged as above, but we write them empty, like this:
Note that the numbers are not in binary order, but are arranged so that only a single bit changes between neighbors.This one-bit change applies at the edges, too. So cells in the same row on the left and right edges of the array also only differ by one bit.
Note: The value of a particular cell is found by combining the numbers at the edges of the row and column.
Also, in general, it is easier to order the inputs to a K-map so that they can be read like a binary number. (Show example.)
So, we have this grid. What do we do with it?
• We put 1's in all the cells that represent minterms in the SOP . (In other words, we find the 1's in the truth table output, and put 1's in the cells corresponding to the same inputs.)
Let’s do this in relation to the 2-input multiplexer example:
S A B Y
0 0 0 0
0 10 0
1 00 1
1 10 1
0 01 0
0 11 1
1 01 0
1 1 1 1
If there are two neighboring 1's in the grid, it means that the input bit change between the two cells has no effect on the output, and thus there is redundancy. This leads to a basic strategy.
Basic Strategy:
Group adjacent 1's together in square or rectangular groups of 2, 4, 8, or 16, such that the total number of groups and isolated 1's is minimized, while using as large groups as possible. Groups may overlap, so that a particular cell may be included in more than one group.
(Recall that adjacency wrap s around edges of grid.)
Applying this to the multiplexer example:
So, considering the best option above (i), notice the following:
B changes but the output doesn’t, so B is redundant in this group (See comment 1, below).
A changes but the output doesn’t, so A is redundant in this group (See comment 2, below).
(1.)
(2.)
So, we write out Boolean expressions for each group, leaving out the redundant elements. That is, for each group, we write out the inputs that don’t change.The multiplexer example, with two groups, gives us two terms, Y = S@B + S’@Awhich is the same as what we achieved through using Boolean algebra to reduce the circuit.So, we can summarize this process into a basic set of rules:
Rules for K-Maps
1. Each cell with a 1 must be included in at least one group.
2. Try to form the largest possible groups.
3. Try to end up with as few groups as possible.
4. Groups may be in sizes that are powers of 2: 2 0 = 1, 21 = 2, 22 = 4, 23 = 8, 24 = 16, ...
5. Groups may be square or rectangular only (including wrap-around at the grid edges). No diagonals or zig-zags can be used to form a group.
6. The larger a group is, the more redundant inputs there are:
i. A group of 1 has no redundant inputs.
ii. A group of 2 has 1 redundant input.
iii. A group of 4 has 2 redundant inputs.
iv. A group of 8 has 3 redundant inputs.
v. A group of 16 has 4 redundant inputs.
The following simple examples illustrate rule 6 above.
Examples
2-input Example
A B Y
0 0 1
10 1
01 1
11 0
Direct from truth table: Y = A’B’ + A’B + AB’
3-input Example
A B C Y
0 0 0 0
0 10 0
1 00 1
1 10 1
0 01 1
0 11 0
1 01 1
1 11 1
Direct from truth table: Y = A’BC’ + A’BC + AB’C’ + ABC’ + ABC
4-input Example
AB C DY
0 0 0 01
0 0 10 0
0 1 00 1
0 1 10 0
1 0 00 0
1 0 10 1
1 1 00 0
1 1 10 1
0 0 01 1
0 0 11 0
0 1 01 1
0 1 11 0
1 0 01 0
1 0 11 1
1 1 01 1
1 1 11 1
use a K-map to reduce the following 4-input circuit.
A B C D Y
0 0 0 0 1
0 0 10 0
0 1 00 1
0 1 10 0
1 0 00 1
1 0 10 1
1 1 00 1
1 1 10 1
0 0 01 1
0 0 11 0
0 1 01 1
0 1 11 0
1 0 01 1
1 0 11 1
1 1 01 1
1 1 11 1
Using K-Maps
So, we have seen how K-maps can help us minimize logic.How do we apply this to a circuit which has multiple outputs?We simply use multiple K -maps, and treat them as separate circuits that just happen to have the same inputs.
A B C X Y
0 0 0 1 0
0 1 10 0
1 0 00 1
1 1 10 1
0 0 01 0
0 1 11 0
1 0 01 1
1 1 11 0
Now, what if there are cases w here our output doesn’t matter?
• In other words, what if there are input combinations for which we don’t care what the output is?
You might wonder when such a case might occur. So, consider a seven-segment display (like in many alarm clocks, or the classroom wall clock).
On this seven-segment display, we only wish to display the numbers 0 to 9.
• To represent the numbers 0 to 9, we need 4 bits: 0000 represents zero, 1001 represents nine, and the other digits are similarly represented.
• But 4 bits can actually represent values from 0 to 15!
• So, when input bit values are from 10 to 15, we don’t care what the output is. (That is, we would never expect the input to the circuit to have those values, so we don’t care what the circuit does if it does happen).
This concept of not caring allows us to minimize the logic further.
So, a circuit to control a seven-segment display would have 4 inputs (the binary number representation of the decimal number to be displayed) and 7 outputs (control signals to each of the 7 segments that tell them to light up or turn off).
Consider the topmost segment, labeled ‘a’.
• assume that a value of 1 activates the segment, and a value of 0 turns it off / leaves it unlit
• the top segment will be lit for values 0 , 2, 3, 5, 6, 7, 8, 9
• we don’t care what it does if the values input happen to be in the range of 10 to 15
In both the truth tab le and K-map, we represent a “don’t care” with an X . We draw them on the K-map grid along with the 1's.
Then, when forming groups on the K-map, we can treat the “don’t cares” (the X cells) as 1's. This may often allow us to make larger groups, and thus reduce the logic more.
So, we can include “don’t cares” in groups, but we never have groups of just don’t cares. Basically, we can treat them as 1's or 0's, whichever is most convenient.
Truth table for output a of seven-segment display.
A B C D a
0 0 0 0 1
0 0 10 0
0 1 00 1
0 1 10 1
1 0 00 0
1 0 10 1
1 1 00 1
1 1 10 1
0 0 01 1
0 0 11 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Thus, using “don’t care” outputs can sometimes allow us to further minimize logic, but only in
cases where we really don’t care. You should look to utilize “don’t cares” if the design
specification allows it, but unfortunately that won’t always be the case.
Five variable k-map:
Five variable k-map can have 25 =32 possible combinations of input variable as
A’B’C’D’E’, A’B’C’D’E,--------ABCDE with minterms m0, m1-----m31 respectively in SOP &
A’+B’+C’+D’+E’, A’+B’+C’+D’+E,---------- A+B +C +D +E with maxterms M0,M1, -----------
M31 respectively in POS form. It has 25=32 squares or cells of the k-map are divided into 2 blocks
of 16 squares each. The left block represents minterms from m0 to m15 in which A is a 0, and the
right block represents minterms from m16 to m31 in which A is 1.The 5-variable k-map may
contain 2-squares, 4-squares , 8-squares , 16-squares or 32-squares involving these two blocks.
Squares are also considered adjacent in these two blocks, if when superimposing one block on top
of another, the squares coincide with one another.
Grouping s is
Ex: F=Σm(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31) is SOPPOS is F=πM(2,3,7,8,9,10,11,12,16,17,18,19,20,21,23,26,27)
The real minimal expression is the minimal of the SOP and POS forms.The reduction is done as
1. There is no isolated 1s2. M12 can go only with m13. Form a 2-square which is read as A‘BCD‘
3. M0 can go with m2,m16 and m18 . so form a 4-square which is read as B‘C‘E‘
4. M20,m21,m17 and m16 form a 4-square which is read as AB‘D‘
5. M2,m3,m18,m19,m10,m11,m26 and m27 form an 8-square which is read as C‘d
6. Write all the product terms in SOP form. So the minimal expression is
Fmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D(16 inputs)
In the POS k-map ,the reduction is done as:1. There are no isolated 0s
3.4.M85. M286. M307. Sum terms in POS form. So the minimal expression in POS is Fmin= A‘BcD‘+B‘C‘E‘+AB‘D‘+C‘D
Don’t care combinations: For certain input combinations, the value of the output is unspecified
either because the input combinations are invalid or because the precise value of the output is of no
consequence. The combinations for which the value of experiments are not specified are called
don‘t care combinations are invalid or because the precise value of the output is of no
consequence. The combinations for which the value of expressions is not specified are called don‘t
care combinations or Optional Combinations, such expressions stand incompletely specified. The
output is a don‘t care for these invalid combinations.
Ex:In XS-3 code system, the binary states 0000, 0001, 0010,1101,1110,1111 are unspecified. &
never occur called don‘t cares.
A standard SOP expression with don‘t cares can be converted into a standard POS form by keeping
the don‘t cares as they are & writing the missing minterms of the SOP form as the maxterms of the
POS form vice versa.
Don‘t cares denoted by ‗X‘ or ‗φ‘
Ex: f=Σm(1,5,6,12,13,14)+d(2,4)
Or f=π M(0,3,7,9,10,11,15).πd(2,4)
SOP minimal form fmin= BC’+B’D +A’C’D
POS minimal form fmin=(B+D)(A’ +B)(C’ +D’)
Questions
1. What is a karnaugh map? State the limitations of karnaugh map.
2. Minimize the following Boolean function using k-map and realize using NAND Gates
F(A, B, C, D)= Σm(0, 2, 4, 6, 8, 10, 12, 14).
3. Minimize the following Boolean function using k-map and realize F(A, B, C, D)= Σm(0,
2, 7,6, 8, 11, 15, 14).
4. Minimize the following Boolean function using k-map and realize using NAND Gates
(A, B, C, D,E)= Σm(0, 2, 4, 6, 9,11,13,15,17,21,25,27,29,31).
5. Minimize the following Boolean function using k-map and realize using NAND Gates
F(A, B, C)= Σm(0, 2, 4, 6, 1,5,3)
2.Nand and Nor Implementation
The implementation of a logic expression such that each one of the inputs has to pass through only two gates to reach the output is called Two-level implementation. Both SOP , POS forms result in two-level logic Two level implementation can be with AND, OR gates or only NAND or with only NOR gates Boolean expression with only NAND gates requires that the function be in SOP form.Function F= AB+CD(A) AND-OR logic(B) NAND-NAND logic F=AB+CD= AB+CD =AB .CD
AND-OR Logic NAND LogicTwo –level implementation using AND-OR and NAND logic The implementation of the form:F=XY‘+X‘Y+Z using AND-OR logic and NAND- NAND logic is
Two –level implementation using AND-OR and NAND logic
The implementation of Boolean expressions with only NOR gates requires that the function be in the form of POS form.Implementation of the function (A+B)(C‘+D‘)
Two –level implementation using OR-AND and NOR logic
Two –level implementation using OR-AND and NOR logic
TWO LEVEL IMPLEMENTATION, EX-OR FUNCTION
Two level implementation:
The types of gates most often found in IC‘s are NAND and NORSome NAND or NOR gates allow the possibility of wire connection between the outputs of two gates to provide a specific logic function called Wired Logic.The logic function implemented by the circuit
Is calledan AND-OR Invert function.
Similarly NOR outputs of ECL gates can be tied together to form Wired NOR function. The logic function implemented by this circuit is
Is called OR-AND INVERT Function.EX: Open Collector TTL NAND gates, when tied together perform the wired AND logic is called AOI
=( AB) .(CD )=AB +CDSimilarly NOR outputs of ECL can tied together to perform a wired NOR function. F=(A +B )+(C + D) =[(A +B ) ( C+D ) ]Non Degenerate forms:Considering 4 types of gates AND, OR, NAND , NOR & assign one type of gate for the first level & one type of gate for the second level. Find 16 possible combinations of two level form. Eight of these are degenerate forms. Because they generate to a single operation. i.e, AND gate in first level & AND gate in second The output is nearly the AND function of all input variables.The other non degenerate forms produce an implementation in SOP or POS are AND-OR OR-ANDNAND-NAND NOR-NORNOR-OR NAND-NANDOR-NAND AND-NORThe two forms are dual of each other.AND-OR & OR-AND forms are the basic two-level forms. NAND-NAND, NOR_NORAOI Implementation:The two forms Nandi-And and And-Nor perform AOI function.Inversion isand-Nor form resembles the and-Or form done by the bubble in the output of the NOR gate.Its function is F= AB+CD +E
Two-level implementation in AND-NOR and NAND-AND formOAI Implementation:The twoforms OR-NAND and NOR-NOR perform OAI function.OR-NAND form OR-AND form except inversion done by bubble in NAND gate. Function F=[(A +B ) ( C+ D) E]
Summary:
The Exclusive OR (X-OR) gate:It has 2 inputs& only 1 output. It assumes output as 1 when input is not equal called anti-
coincidence gate or inequality detector.
0
Logic Symbol
Proof: Truth Table
The high outputs are generated only when odd number of high inputs is present. This is why x-or function also known as odd function.
The X-OR gate using AND-OR-NOT gates:
A B0 0 00 1 11 0 11 1 0
X-OR gate as an Inverter:By connecting one of two input terminals to logic 1 & feeding the sequence to be
inverted to other terminal
Logic Symbol TTL IC 746 has 4 x-OR gateCMOS IC 74C8C has 4 X-OR gates.X-OR gate using NAND gates only:
X-OR gate using NOR gates only:
QUESTIONS
1. What is two level logic? State its advantages and disadvantages?
2. Implement OR gate using only two input NAND gates
3. Implement the following Boolean equation using only NAND gates Y=AB+CDE+F 3.
4. Simplify the following Boolean expressions using K-map and implement them using
NAND gates F(W,X,Y,Z)= XZ+W’XY’+WXY+W’YZ+WY’Z
5. Implement the following Boolean function using NOR gates
Y=(AB’+A’B)(C+D’ )
4 .QUINE-MCCLUSKEY METHOD
Quine- Mccluskey Method:
It also known as Tabular method. It is more systematic method of minimizing expressions of even larger number of variables. It is suitable for hand computation as well as computation by machines i.e., programmable. . The procedure is based on repeated application of the combining theorem.PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from which a minimal sum may be selected.Consider expressionΣm(0,1,4,5)= A’B’C’+A’B’ C+AB’C’ +AB’CFirst, second terms & third, fourth terms can be combinedA’B( C+C’ )+ AB(C+C’ )= A’B +ABReduced toB( A’+A )=BThe same result can be obtained by combining m0& m4 & m1&m5 in first step & resulting terms in the second step .Procedure: Decimal Representation Don‘t cares PI chart EPI Dominating Rows & Columns Determination of Minimal expressions in comples cases. Branching Method:
EX:
QUESTIONS1. Simplify the Boolean function by using tabulation method
F(a,b,c,d)=Σm(0,1,2,5,6,7,8,9,10,14)
2. Simplify the following Boolean function using Tabulation method
Y(A,B,C,D) = Σ(1,3,5,8,9,11,15)
UNIT III
COMBINATIONAL LOGIC CIRCUITS:
Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits are following −
The output of combinational circuit at any instant of time, depends only on the levels present at input terminals.
The combinational circuit do not use any memory. The previous state of input does not have any effect on the present state of the circuit.
A combinational circuit can have an n number of inputs and m number of outputs.
Block diagram
We're going to elaborate few important combinational circuits as follows.
Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is designed to add two single bit binary number A and B. It is the basic building block for addition of two single bit numbers. This circuit has two outputs carry and sum.
Block diagram
Truth Table
Circuit Diagram
Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.
Block diagram
Truth Table
Circuit Diagram
Half-Subtractors
Half-subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
Truth Table
Circuit Diagram
Full-Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the borrow output.
Truth Table
Circuit Diagram
N-Bit Parallel Adder
The Full Adder is capable of adding only two single digit binary number along with a carry input. But in practical we need to add binary numbers which are much longer than just one bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. It uses a number of full adders in cascade. The carry output of the previous full adder is connected to carry input of the next full adder.
4-Bit Parallel AdderIn the block diagram, A0 and B0 represent the LSB of the four bit words A and B. Hence Full
Adder-0 is the lowest stage. Hence its Cin has been permanently made 0. The rest of the
connections are exactly same as those of n-bit parallel adder is shown in fig. The four bit parallel adder is a very common logic circuit.
Block diagram
N-Bit Parallel SubtractorThe subtraction can be carried out by taking the 1's or 2's complement of the number to be
subtracted. For example we can perform the subtraction (A-B) by adding either 1's or 2's complement of B to A. That means we can use a binary adder to perform the binary subtraction.
4 Bit Parallel Subtractor
The number to be subtracted (B) is first passed through inverters to obtain its 1's complement. The 4-bit adder then adds A and 2's complement of B to produce the subtraction. S3 S2 S1 S0
represents the result of binary subtraction (A-B) and carry output Cout represents the polarity of the result. If A > B then Cout = 0 and the result of binary form (A-B) then C out = 1 and the result is in the 2's complement form.
Block diagram
Carry Look Ahead Adder
In ripple carry adders, the carry propagation time is the major speed limiting factor.
Most other arithmetic operations, e.g. multiplication and division are implemented using several add/subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations. Accordingly, reducing the carry propagation delay of adders is of great importance. Different logic design approaches have been employed to overcome the carry propagation problem. One widely used approach employs the principle of carry look-ahead solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based on the fact that a carry signal will be generated in two cases: (1) when both bits Ai and Bi are 1, or (2) when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1. To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers A and B.
The Figure shows the full adder circuit used to add the operand bits in the ith column; namely Ai & Bi and the carry bit coming from the previous column (Ci ).
In this circuit, the 2 internal signals Pi and Gi are given by:
The output sum and carry can be defined as :
Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi =1, regardless of the input carry (Ci). Pi is known as the carry propagate signal since whenever Pi =1, the input carry is propagated to the output carry, i.e., Ci+1. = Ci (note that whenever Pi =1, Gi =0). Computing the values of Pi and Gi only depend on the input operand bits (Ai & Bi) as clear from the Figure and equations. Thus, these signals settle to their steady-state value after the propagation through their respective gates. Computed values of all the Pi’s are valid one XOR-gate delay after the operands A and B are made valid. Computed values of all the Gi’s are valid one AND-gate delay after the operands A and B are made valid. The Boolean expression of the carry outputs of various stages can be written as follows: C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
In general, the ith carry output is expressed in the form Ci = Fi (P’s, G’s , C0). In other words, each carry signal is expressed as a direct SOP function of C0 rather than its preceding carry signal. Since the Boolean expression for each output carry is expressed in SOP form, it can be implemented in two-level circuits. The 2-level implementation of the carry signals has a propagation delay of 2 gates, i.e., 2τ. The 4-bit carry look-ahead (CLA) adder consists of 3 levels of logic:
First level: Generates all the P & G signals. Four sets of P & G logic (each consists of an XOR gate and an AND gate). Output signals of this level (P’s & G’s) will be valid after 1τ. Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-level implementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) as defined by the above expressions. Output signals of this level (C1, C2, C3, and C4) will be valid after 3τ. Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi ⊕ Ci). Output signals of this level (S0, S1, S2, and S3) will be valid after 4τ.
Thus, the 4 Sum signals (S0, S1, S2 & S3) will all be valid after a total delay of 4τ compared to a delay of (2n+1)τ for Ripple Carry adders. For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9τ.
The disadvantage of the CLA adders is that the carry expressions (and hence logic) become quite complex for more than 4 bits.
Thus, CLA adders are usually implemented as 4-bit modules that are used to build larger size adders.
BCD Adder
If two BCD digits are added then their sum result will not always be in BCD. Consider the two given examples.
In the first example, result is in BCD while in the second example it is not in BCD. Four bits are needed to represent all BCD digits (0 – 9). But with four bits we can represent up to 16 values (0000 through 1111). The extra six values (1010 through 1111) are not valid BCD digits. Whenever the sum result is > 9, it will not be in BCD and will require correction to get a valid BCD result.
Correction is done through the addition of 6 to the result to skip the six invalid values as shown in the truth table by yellow color.Consider the given examples of non-BCD sum result and its correction.
A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum BCD digit and a carry out bit. The maximum sum result of a BCD input adder can be 19. As maximum number in BCD is 9 and may be there will be a carry from previous stage also, so 9 + 9 + 1 = 19 The following truth table shows all the possible sum results when two BCD digits are added.
The logic circuit that checks the necessary BCD correction can be derived by detecting the condition where the resulting binary sum is 01010 through 10011 (decimal 10 through 19). It can be done by considering the shown truth table, in which the function F is true when the digit is not a valid BCD digit. It can be simplified using a 5-variable K-map. But detecting values 1010 through 1111 (decimal 10 through 15) can also be done by using a 4-variable K-map as shown in the figure.
Values greater than 1111, i.e., from 10000 through 10011 (decimal 16 through 19) can be detected by the carry out (CO) which equals 1 only for these output values. So, F = CO = 1 for these values. Hence, F is true when CO is true OR when (Z3 Z2 + Z3 Z1) is true. Thus, the correction step (adding 0110) is performed if the following function equals 1:
F = CO + Z3 Z2 + Z3 Z1
The circuit of the BCD adder will be as shown in the figure.
The two BCD digits, together with the input carry, are first added in the top 4-bit binary adder to produce the binary sum. The bottom 4-bit binary adder is used to add the correction factor to the binary result of the top binary adder. Note: 1. When the Output carry is equal to zero, the correction factor equals zero. 2. When the Output carry is equal to one, the correction factor is 0110.
The output carry generated from the bottom binary adder is ignored, since it supplies information already available at the output-carry terminal. A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from one stage must be connected to the input carry of the next higher-order stage.
Questions .
1.What is half subtractor? Draw the block diagram.
2.Define half adder? Draw the block diagram.
3.Design the full subtractor using half subtractor.
4. Design the full adder using half adders.
5. Draw the basic structure of combinational logic circuit
6. What is half subtractor? Draw the block diagram.
7. Define half adder? Draw the block diagram.
8. Design the full subtractor using half subtractor.
9. Design the full adder using half adders.
10. Design a 4-bit parallel adder using full adders.
11. Sketch 4-bit adder cum subtract using full adders
Binary Multiplier
Multiplication of binary numbers is performed in the same way as with decimal numbers. The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. The result of each such multiplication forms a partial product. Successive partial products are shifted one bit to the left. The product is obtained by adding these shifted partial products. Consider an example of multiplication of two numbers, say A and B (2 bits each), C = A x B. The first partial product is formed by multiplying the B1B0 by A0. The multiplication of two bits such as A0 and B0 produces a 1 if both bits are 1; otherwise it produces a 0 like an AND operation. So the partial products can be implemented with AND gates.The second partial product is formed by multiplying the B1B0 by A1 and is shifted one position to the left.
The two partial products are added with two half adders (HA). Usually there are more bits in the partial products, and then it will be necessary to use Full Adders.
The least significant bit of the product does not have to go through an adder, since it is formed by the output of the first AND gate as shown in the Figure. A binary multiplier with more bits can be constructed in a similar manner. Consider another example of multiplying two numbers, say A (3-bit number) and B (4-bit number). Each bit of A (the multiplier) is ANDed with each bit of B (the multicand) as shown in the Figure.
The binary output in each level of AND gates is added in parallel with the partial product of the previous level to form a new partial product. The last level produces the final product.
Since J = 3 and K = 4, 12 (J x K) AND gates and two 4-bit ((J - 1) K-bit) adders are needed to produce a product of seven (J + K) bits. Its circuit is shown in the Figure. Note that 0 is applied at the most significant bit of augend of first 4-bit adder because the least significant bit of the product does not have to go through an adder
Digital Comparator
Another common and very useful combinational logic circuit is that of the Digital Comparator circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals present at their input terminals and produce an output depending upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to compare them and determine whether the value of input A is greater than, smaller than or equal to the value at input B etc. The digital comparator accomplishes this using several logic gates that operate on the principles of Boolean Algebra. There are two main types of Digital Comparator available and these are.
1. Identity Comparator – an Identity Comparator is a digital comparator that has only one output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has three output terminals, one each for equality, A = B greater than, A > B and less than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the following three output conditions when compared to each other.
Which means: A is greater than B, A is equal to B, and A is less than B
This is useful if we want to compare two variables and want to produce an output when any of the above three conditions are achieved. For example, produce an output from a counter when a certain count number is reached. Consider the simple 1-bit comparator below.
1-bit Digital Comparator Circuit
Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Digital Comparator Truth Table
Inputs OutputsB A A > B A = B A < B0 0 0 1 00 1 1 0 01 0 0 0 11 1 0 1 0
You may notice two distinct features about the comparator from the above truth table. Firstly, the circuit does not distinguish between either two “0” or two “1”‘s as an output A = B is produced
when they are both equal, either A = B = “0” or A = B = “1”. Secondly, the output condition for A = B resembles that of a commonly available logic gate, the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-bits giving: Q = A ⊕ B
Digital comparators actually use Exclusive-NOR gates within their design for comparing their respective pairs of bits. When we are comparing two binary or BCD values or variables against each other, we are comparing the “magnitude” of these values, a logic “0” against a logic “1” which is where the term Magnitude Comparator comes from.
As well as comparing individual bits, we can design larger bit comparators by cascading together n of these and produce a n-bit comparator just as we did for the n-bit adder in the previous tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD words to produce an output if one word is larger, equal to or less than the other.
A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words (“nibbles”) are compared to each other to produce the relevant output with one word connected to inputs A and the other to be compared against connected to input B as shown below.
4-bit Magnitude Comparator
Decoder
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.
Block diagram
Examples of Decoders are following.
Code converters BCD to seven segment decoders Nixie tube decoders Relay actuator
2 to 4 Line Decoder
The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each output is 1 for only a specific combination of inputs.
Block diagram
Truth Table
Logic Circuit
in this topic we will try to discuss about Combinational Logic Implementation full adder circuit with a decoder and two OR Gates.
To do this at first we need to review the truth table of Full Adder circuit.
Inputs a b c
Outputs C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Truth table of Full Adder Circuit
From the truth table we have been found that S(a,b,c)=sum(1,2,4,7).,C(a,b,c)=sum(3,5,6,7)
As there are three inputs and eight min-terms, so have to use 3 to 8 line decorder. The generates the eight min-terms for a, b, c.
The OR Gate for output S forms the sum of min-terms 1, 2, 4 and 7. The OR Gate output C forms the sum of min-terms 3, 5, 6 and 7.
Circuit Diagram
A function with a long list of min-terms requires an OR Gate with a large number of inputs. A function F having a list of K min-terms can be expressed in its complemented form F’ with 2^n-K min-terms. If the number of min-terms in a function is greater than 2^n/2, then F’ can be expressed with fewer min-terms than required for F. In such a case, it is suitable to use a NOR Gate to sum the min-terms of F’. The output of the NOR Gate will generate the normal output F.
The decoder method can be used to implement any combinational circuit. It is necessary to implementing with comparing to all other possible implementations to determine the solution.
Encoder
Encoder is a combinational circuit which is designed to perform the inverse operation of the decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into an m bit another digital word.
Block diagram
Examples of Encoders are following.
Priority encoders Decimal to BCD encoder Octal to binary encoder Hexadecimal to binary encoder
Priority Encoder
This is a special type of encoder. Priority is given to the input lines. If two or more input line are 1 at the same time, then the input line with highest priority will be considered. There are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has the highest priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other inputs.
Block diagram
Truth Table
Logic Circuit
Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the selected inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y. E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal that means it will perform the required operation when it is low.
Block diagram
Multiplexers come in multiple variations
2 : 1 multiplexer4 : 1 multiplexer16 : 1 multiplexer32 : 1 multiplexer
Block Diagram
Truth Table
Demultiplexers
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. It has only one input, n outputs, m select input. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. A de-multiplexer is equivalent to a single pole multiple way switch as shown in fig.
Demultiplexers come in multiple variations.
1 : 2 demultiplexer 1 : 4 demultiplexer 1 : 16 demultiplexer 1 : 32 demultiplexer
Block diagram
Truth Table
Questions 1. Design & implement BCD to Excess-3 code converter.2. Explain carry look ahead adder circuit with the help of logic diagram.3. Construct a BCD adder-subtractor circuit.4. Implement 4-bit magnitude comparator and write down its design procedure.5. Design & implement full adder using decoder.6. Implement the following Boolean function using 8:1 multiplexer. F(A,B,C,D) = A’BD’+ACD+B’CD+A’C’D.7. What is encoder? Design octal to binary encoder. 1. Draw the basic structure of combinational logic circuit
8.Implement 2-bit by 2-bit multiplier with half adders.9. Design a 4-bit parallel adder using full adders.10. Realize a 2-bit comparator using gates.11. Draw the block diagram of 3x8 decoder with enable.12. How decoder can be converted into a demultiplexer.13. What is an encoder?14. What is priority encoder? Mention its operation.15. What is multiplexer? Draw the block diagram of 4x1 MUX.16. What are the functional differences between serial & parallel adder?17. What is demultiplexer?18. Draw 4-bit by 4-bit multiplier.19. Sketch 4x16 decoder with two 3x8 decoders.20. Draw 32:1 mux using two 16:1 mux and one 2:1 mux.21. Sketch quadruple 2-to-1-line multiplexer.
