Heterogeneous Integration of III-V Active Devices on a Silicon-on-Insulator Photonic Platform

http://photonics.intec.ugent.bePhotonics Research Group

Heterogeneous Integration of III-V Active Devices on a Silicon-on-Insulator Photonic Platform

G. Roelkens, J. Brouckaert, J. Van Campenhout, D. Van Thourhout, R. Baets

Photonics Research Group – Ghent University/IMECSint-Pietersnieuwstraat 41,

B-9000 Ghent – Belgiume-mail: [email protected]

© intec 2007 - Photonics Research Group - http://photonics.intec.ugent.be

Outline

• Introduction

• Die-to-wafer bonding for hetero-integration

• Heterogeneously integrated laser diodes

• Heterogeneously integrated photodetectors

• Conclusions and outlook


IntroductionWhy combine silicon with III-V?

silicon

fall back on CMOS technology

high index contrast

no emission nor amplification, yet

III-V

superb emission, amplification and detection

full active-passive integration is complex and expensive, still

III-V on silicon

combine the best of two worlds

price: bonding technology does it work?

can it turn into a manufacturing technology?


IntroductionThere are several ways to integrate III-V on SOI

Flip-chip integration of opto-electronic components

most rugged technology

testing of opto-electronic components in advance

slow sequential process (alignment accuracy)

low density of integration

Hetero-epitaxial growth of III-V on silicon

collective process, high density of integration

mismatch in lattice constant, CTE, polar/non-polar

contamination and temperature budget

Bonding of III-V epitaxial layers

sequential but fast integration process

high density of integration, collective processing

high quality epitaxial III-V layers


Outline

• Introduction






III-V/Silicon photonics

Bonding of III-V epitaxial layers Molecular die-to-wafer bonding

Based on van der Waals attraction between wafer surfaces

Adhesive die-to-wafer bonding Uses an adhesive layer as a glue to stick both surfaces

Wafer-scaleprocessing

of III-V devices

III-V die bonding(unprocessed) InP substrate removal

SOI Waveguide wafer


III-V/Silicon photonicsBonding of III-V epitaxial layers

Molecular die-to-wafer bonding Based on van der Waals attraction between wafer surfaces

Requires “atomic contact” between both surfaces

- very sensitive to particles

- very sensitive to roughness

- very sensitive to contamination of surfaces

Adhesive die-to-wafer bonding Uses an adhesive layer as a glue to stick both surfaces

Requirements are more relaxed compared to Molecular

- glue compensates for particles (some)

- glue compensates for roughness (all)

- glue allows (some) contamination of surfaces

While established technology for SOI, III-Vs often do not While established technology for SOI, III-Vs often do not meet the requirements for molecular bondingmeet the requirements for molecular bonding


Bonding TechnologyRequirements for the adhesive for bonding

Optically transparent High thermal stability (post-bonding thermal budget) Low curing temperature (low thermal stress) No outgassing upon curing (void formation) Resistant to all kinds of chemicals

Si

CH3

CH3

Si

CH3

CH3

O

1,3-divinyl-1,1,3,3-tetramethyldisiloxane-bisbenzocyclobutene

400C400C

250C250C

<0.1dB/cm<0.1dB/cm

OKOK

HCl,HHCl,H22SOSO44,H,H22OO22,…,…

DVS-BCB satisfies these requirements


Bonding TechnologyOverview of the bonding process

Die/wafer cleaning most critical step in processing SOI wafer: standard clean – 1 (H2SO4:H2O2:H2O @70C)

Lifts off particles from surface and prevents redeposition

InP/InGaAsP: removal of sacrificial InP/InGaAs layer pair

Si-substrate

SiO2

SiDVS-BCB DVS-BCB DVS-BCB

DVS-BCB coating

Wafer cleaning

Solvent evap + prepolymerization

Die attachment

DVS-BCB

DVS-BCB curing (pressurized)


Bonding TechnologyOverview of the bonding process

After bondingAfter thinning

Cross-section

Optical SOI waferOptical SOI wafer

Thinning:

- mechanical grinding

- wet etching till etch stop layer reached (HCl)


Bonding Technology

200nm

Cross-sectional image of III-V/Silicon substrate

InP-InGaAsP epitaxial layer stack

DVS-BCB

SiO2

Si

Si Si WGDVS-BCB

SiO2

InP/InGaAsP epitaxial layer stack

200nm


Towards integrated devicesLaser diodes and photodetectors have to be fabricated in bonded III-V layer and coupled to SOI circuit below

What architecture is used for the laser diode / photodetector?

How is light efficiently coupled between III-V and SOI layer?

Performance degradation of bonded active devices?

Silicon substrate

Oxide buffer layerSilicon waveguide layer

InP/InGaAsP layer stack


Outline

• Introduction


• Heterogeneously integrated laser diodes Fabry-Perot lasers

Microring lasers




Integrated Devices: laser diode Integrated laser diodes

Fabry-Perot laser cavity by etching InP/InGaAsP laser facets

Inverted adiabatic taper coupling approach

Laser beam



Fabry-Perot laser cavity by etching InP/InGaAsP laser facets

Inverted adiabatic taper coupling approach



Only pulsed operation due to high thermal resistivity DVS-BCB Integration of a heat sink to improve heat dissipation Continuous wave operation achieved this way


Integrated Devices: laser diodeIntegrated laser diodes

Microlasers

Si substrate

SiO2Si waveguide

bottom contact

InP

top contact

Si substrate

SiO2Si waveguide

bottom contact

InP

top contact

SiO2/BCBSiO2/BCB

0.01

0.1

1

10

100

1000

0 2 4 6 8 10

Exponentieel(h0)Exponentieel(h50)Exponentieel(h100)

ts = 0nmts = 50nmts = 100nm

microdisk diameter D [m]

be

nd

loss

[/c

m]

Simulation results“Fundamental Whispering Gallery Modes”

TE-pol

Meep FDTD


CW Microdisk Laser integrated with SOI wire

Si substrate

SiO2Si waveguide

top contactbottom contact

active layer

tunnel junction

Si substrate

SiO2Si waveguide

top contactbottom contact

active layer

tunnel junction

7.5-m devices exhibit continuous-wave lasingThreshold current Ith = 0.6mA, voltage Vth = 1.5-1.7V,

up to 7W CW, 100 W pulsed (coupled into SOI wire)J. Van Campenhout et al (Ghent University-IMEC, INL, CEA-LETI),

OFC 2007 and Optics Express, p.6744-6749 (2007)


Integrated Devices: laser diodeIntegrated laser diodes

Microlasers (7.5um devices)

-90

-80

-70

-60

-50

-40

-30

1540 1560 1580 1600 1620 1640wavelength [nm]

inte

nsi

ty [

au, l

og

]

I990u

0

1

2

3

4

5

6

7

8

0 0.5 1 1.5 2current [mA]

ou

tpu

t p

ow

er

[W

]

0

0.5

1

1.5

2

2.5

vo

lta

ge

[V

]

Threshold current Ith = 0.6mA, voltage Vth = 1.5-1.7V

slope efficiency = 15W/mA, up to 7W

(Pulsed regime: up to 100W peak power)

Thermal roll-over can be shifted to higher drive current levels through the incorporation of an integrated heat sink

as for the Fabry-Perot laser diodes


SOI waveguide

SOI Optical Interconnect

layer

Electrical Interconnect

layer

Silicon transistor

layer

microdetectormicrolaserIII-V material

On-Chip Optical Interconnect“Adding a compact and efficient optical link to a silicon chip, by heterogeneous integration”

→ European research programme PICMOS (Photonic Interconnect Layer on CMOS by Waferscale Integration,

FP6-2002-IST-1-002131)


Outline

• Introduction

• DVS-BCB die-to-wafer bonding for hetero-integration


• Heterogeneously integrated photodetectors p-i-n

MSM



Integrated Devices: detectorsIntegrated photodetectors

Side-coupled p-i-n photodetector Identical structure as bonded Fabry-Perot laser diode

Relatively good responsivity (0.23A/W)

Large number of processing steps – compatible with laser



Vertical incidence p-i-n photodetector Coupling using a diffraction grating

Low experimental responsivity (0.02A/W) but due to design

Smaller number of processing steps – more compact design

DVS- BCB layerOxide buffer layer



Evanescently coupled MSM detector Small number of processing steps

High experimental responsivity (1.0A/W)

Compact devices

Epitaxial layer structure not compatible with laser epitaxy


Integrated Devices: detectors

2 coplanar Schottky contacts

InAlGaAs Graded schottky contact layer

InGaAs absorption layer

40μm

Integrated photodetectors Evanescently coupled MSM detector

Directional coupling between detector waveguide and SOI waveguide (3μm)

Ti/Au contact

contact window

SOI waveguide


Integrated Devices: detectors

25μm long detector

R = 1A/W (1550nm), IQE = 80% (5V bias)

Idark = 3nA (5V bias)

25μm long detector

Wide spectral range (limited by bandgap wavelength of InGaAs @ 1.65μm)

0

10

20

30

40

50

60

70

80

90

100

1480 1500 1520 1540 1560 1580 1600 1620 1640 1660

Wavelength (nm)

No

rma

lize

d q

ua

ntu

m e

ffic

ien

cy

(-)

.

Integrated photodetectors Evanescently coupled MSM detector


Outline

• Introduction

• DVS-BCB die-to-wafer bonding for hetero-integration





Conclusions and outlookHeterogeneous III-V/Silicon PICs hold the promise to combine best of both worlds, resulting in complex active/passive integrated optical circuits.

Bonding technology is an enabling technology to achieve this. Adhesive die-to-wafer bonding is a robust technology compatible with modest surface quality of III-V surfaces

Proof-of-principle components have been demonstrated, illustrating the benefits of this technology. The design and characterization of more complex integrated circuits is on the way.


Acknowledgements• PICMOS consortium, in particular CEA-LETI, TRACIT and INL Lyon for co-developing the InP/Si microlaser

• IMEC CMOS pilot line for fabricating the SOI photonic circuits

• ePIXnet Silicon Photonics Platform (IMEC+LETI) for organizing MPW runs on a a cost-sharing basis (www.siliconphotonics.eu)

Documents

Heterogeneous Integration of III-V Active Devices on a Silicon-on-Insulator Photonic Platform