Henk Gooijen - PA8PDPVincent Slyngstad - vrs version 1.0 - August 12th, 2004

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Generic Switch & Lights console

The “Real Console” manual

Preface

Parts listing for the Core Board

Parts listing for the I/O Board

Building the “Real Console”1. Assembly of the Core Board2. Assembly of the I/O Board

Configuration of the “Real Console”1. Jumper settings on the Core Board2. Jumper settings on the I/O Board

Introduction to the “Real Console”1. Operating modes of the Real Console

! Stand-Alone mode! Console mode! Debug Monitor mode

2. Brief hardware description3. Brief firmware description4. An example: “The implementation of the PDP-11/40 console”5. How to implement the required modifications to SIMH

AppendicesA. Command summary of the monitor CORESYS-09B. Protocol description of the Real ConsoleC. Detailed hardware description

1. Schematic diagram Core board! Memory map

2. Schematic diagram I/O board3. Connection between Core and I/O Board4. Connections I/O Board and external hardware

D. I/O Board load calculationsE. Firmware descriptionF. Detailed electrical diagrams

Sources

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P R E F A C E

Hello!

Thank you for your interest in our Real Console project! Hopefully this document will notbore the more sophisticated readers.

First, a disclaimer. You bought these cards from us, other hobbyists interested in PDP-11s.You did not buy them from a major corporation who stands behind them with deep pockets.We have done some limited testing of the hardware in connection with the serial port of a PC.However, if some combination of our slip-ups and your slip-ups damages you or your PC, theproject’s hardware or a vintage front panel connected to the hardware, we will be truly sorry,but that’s it. There is, as the lawyers say, “No warranty of any kind, expressed or implied,not even an implied warranty of merchantability or fitness for a particular purpose.”Suing us would be especially rude and pointless, since we provided these items for cost andwithout charging for our labour, then warned you of the danger.

That said, they didn’t fry our PC’s .

The Real Console is provided as bare boards, with or without a parts kit.This means you will be assembling them yourself. We have tried to make this a project thatwe thought was reasonably easy for people who actually own and maintain vintage hardware.The main motivation for this project was, in fact, the idea to have a PDP-11 with the fancy“blinkenlight” console on your desk, using a simple PC.

So, here is what we expect. You have some passing exposure to TTL logic, you can readresistor colour code, and you can solder. This means that you know to use relatively finelypitched rosin core solder and a low wattage soldering iron, and that you can reliably make aclean solder joint while heating the components for no more than a few seconds.If any of this is new to you or sounds challenging, get help.

Basically, the silk-screen on the board labels the component openings with the componentthat goes there. Pay attention to the orientation of the parts; do not install them backwards.Pin 1 of the integrated circuits has a dot and/or a rectangular notch near it, which goes towardthe notch pictured in the silk-screen. Likewise the oscillator (metal can with four leads) has adot and a sharp corner that goes to the “1” on the silk-screen. The resistors and capacitors cango in either way. We like to place them so that it is easy to read their markings. Make surethat you install the electrolytic (polarised) capacitors, one on each board, with the correctpolarity.

Be careful of solder bridges. It may even be possible to short the supplies, if solder is appliedwhere it doesn’t belong. I did specify a solder mask in an effort to help you.

You will have to decide whether to socket all the ICs or only the CPU, PIA, ACIA, RAM andthe EPROM(s).

Vince & Henk .

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Parts listing for the Core Board

• Integrated Circuits and sockets

Component Quantity SocketMC6809E 1 40 p *MC6821 1 40 p *MC6850 1 24 p *i27128 or i27256 1 28 p *TC5565 or 6264 1 28 p *74LS245 2 20 p74LS139 1 16 p74LS138 1 16 p74LS132 1 14 p74LS73 1 14 pNE556 or LM556 1 14 pMAX232A or SP232A 1 16 p

* Socket supplied in the kit.

• Resistors and Capacitors

Resistors qty Capacitors qty3300 Ω (3k3) 710000 Ω (10k) 3 220 pF 1100 kΩ 2 0,1 µF (=100 nF) 7270 Ω 1 100 nF (bypass C’s) 1410k (10-turn trim pot) 1 22 µF / 10 V. (electrolytic) 1

• Miscellaneous

part description qtyCore Board 1LED, 3 mm 14 MHz crystal oscillator 120-pin header connector 1 – 2 rows / 10 pins each2-pin header 3 (1 a,b,c)

DE-9 female connector 1 (2 a)

3-pin header 2 (2 a,b) – 1 row / 3 pins5-pin header 1 – 1 row / 5 pinsjumper 3

Note 1). a - If PIA pin CB1 is not used, one 2-pin header is not needed.b - One is only needed if the external Debug Monitor start-up is required.c - One is only needed if the external Reset button must be connected.

Note 2). a - Only needed if the RS-232 connector is used. This 3-pin header is only used if the DE-9 connector is not used. Likewise, if the DE-9 is used, the 3-pin header is not used. Both are supplied in the kit.b - The other 3-pin header selects the active half if the 27256 boot EPROM is used. This 3-pin header is always needed (including the jumper), even when a 27128 EPROM is installed.

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Parts listing for the I/O Board

• Integrated Circuits and sockets

Component Quantity Socket74LS373 (1) 3 (full configuration: 8) 20 p74LS374 (1) 5 (full configuration: 8) 20 p74LS138 (3) 3 (single board: 2) 16 p

• Resistors and Capacitors

Resistors qty Capacitors qty- - 100 nF (bypass C) 19

100 µF / 10V. (electrolytic) 1

• Miscellaneous

part description qtyI/O Board 116-pin header connector (1) 5 (full config: 8) -- 2 rows / 8 pins each18-pin header connector (2) 1 – 2 rows / 9 pins eachjumper (2) 120-pin header connector (3) 1 – 2 rows / 10 pins each

Note (1): the component count is for the PDP-11/40 console implementation.Note (2): if you have a single I/O Board, or have the I/O Boards at fixed port numbers,

you can solder a jumper at the correct position instead of the 18-pin header with the jumper. This header is not included in the kit.

Note (3): if the system is expanded with more I/O Boards, the flat cable does not endat the 20-pin header of the 1st I/O Board, but continues to the next I/O Board.In a ‘multi’-I/O board configuration, every IO Board must have the 3rd

74LS138 installed and the jumper uniquely configured for the I/O Boardsequence number.

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Building the “Real Console”

1. Assembly of the Core Board

Needed tool, besides a fine low-wattage soldering iron is a multimeter.Take your time to solder the components on the Core Board. Better spend a few more minutes nowworking accurately, than searching for that little solder excess that cause a short circuit.Soldering the components in order from smallest height to higher has the advantage that the boardlays stable on your desk while soldering. Therefore the following soldering order is proposed.

1. Solder all resistors except the trim pot.Make sure that the resistors with the different values are in their correct position.Check the electrical diagram and follow the traces on the Core Board if you have any doubt.Use the Ohm range of the multimeter if you are not sure interpreting the colour codes.

2. Solder the IC sockets that are supplied in the kit. Notice the orientation of the sockets.If you prefer to use sockets for all IC’s you can solder these sockets too, but do not solder thetwo sockets for the 74LS245’s yet. It is a little easier to solder the CORE_IO header beforethe two sockets for the 74LS245’s are soldered.

3. Solder the trim pot.4. Solder the headers JP1, JP4, CORE-IO, and EP-1.5. Solder the two sockets for the 74LS245’s, if you want to use sockets for them. See step 2.6. Solder the bypass capacitors.

! This is how your Core Board will look after these six steps (with sockets for all IC’s).Take a break and admire the work so far!

Note: this is the prototype Core Board with the components bought in The Netherlands.Your components can look different. I used sockets for all IC’s to allow measurement checks,as this is the prototype. I also already installed the jumper on the EP-1 header.

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© First checks and adjustment that you can do.

1. Connect the +5 V power supply to JP4 of the Core Board. Notice the correct polarity, the(-) of the power supply goes to the pin of JP4 close to the CORE-IO header pin #1. At thisstage the Core Board does not have any components that are polarity sensitive, but betterstart correct now, or detect the error connecting the power supply now!Connect the (-) connector of the multimeter to the GND (-) of the power supply.Set the multimeter to a DC Voltage setting higher than 5V (for example 20V).Use the (+) connection of the multimeter to check that the +5 V. is present on all the ICpins that must be connected to +5 V. See the electrical diagram, or use the table below.

IC number - type pin number(s) IC number - type pin number(s)17 MC6809 7, 2, 3, 4, 40 24 MC6821 20, 22, 24, 1821 MC6850 12, 8, 10, 22 6264A 2823 i27128 28, 1 29 i27256 28, 118 74LS132 14 19 74LS138 1628 74LS139 16 27 LM556 14, 4, 1025 74LS245 20 26 74LS245 2020 MAX232 16 2 74LS73 4, 2, 6

2. Preliminary adjustment of the baudrate of the serial port.Switch off the power supply, and disconnect the power supply.Disconnect the (-) of the multimeter from the power supply.Set the multimeter range to “Ohm”, measuring range higher than 20kΩ (20,000 Ohm).Connect one lead of the multimeter to pin #2 of IC27 (LM556 / NE556) and connect theother lead of the multimeter to pin #1 of IC27.Adjust the trim pot R11 until the multimeter reads approximately 14000 Ω.

7. Solder the LED. Notice the correct polarity!The cathode is near the IC #18, 74LS132. The anode is near the resistor. If you are not sureabout the cathode and anode pin, use a power supply and a series resistor to limit the current.The pin that connects to the (+) of the power supply is the anode when the LED is on.

8. Solder the electrolytic polarised capacitor. Notice the correct polarity!9. Solder all other capacitors.10. Solder the IC’s on the Core Board for which you do not use an IC socket.

Do not solder the two 74LS245’s (yet) if you are not using sockets for these two IC’s.• Take care that you install the IC’s in the correct orientation!

The choice is up to you to use IC sockets for all IC’s or for just a few.The kit only supplies sockets for the most important IC’s.

11. Solder the Crystal Oscillator. Notice the location of pin #1. The dot on the metal casingindicates pin #1, the corner of the casing at pin #1 is sharp, the 3 other corners are round.

12. Solder the DE-9 serial port connector or the RS-232 header, depending on which you will useto connect the Core Board to the COM port or terminal.

13. Put all the IC’s in the sockets, except the two 74LS245’s.The reason the 74LS245’s are not put in place is that you can check the flat cable connectionbetween the Core Board / I/O board connection.Install the EPROM in position IC23. Leave IC29 (at the corner of the Core Board) empty.• Take care that you put the IC’s in the correct orientation!

14. Connect a jumper at the position “HI/27128” on the header EP-1 near the EPROM IC23.15. Admire again your work , and do a visual inspection with a bright light.

The Core Board is finished.# Are all IC’s installed with pin 1 at the correct side?# Have the LED and the polarised capacitor the correct orientation?# No small droplets of solder near the soldering joints?

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The protoype board, final result. -- I have put a red dot (paint) next to the (+) pin of JP4…!

16. Connect a momentary switch (contacts normally open) to JP1, RESET.17. Make sure the +5V power supply is turned off.

Connect the +5 V. power supply to JP4. *** Notice the correct polarity! ***Turn on the power supply, and press the RESET button for a short moment.

© Check: the LED must blink at a rate of one time per second.

18. Connect a serial cable to the RS-232 COM-port of your PC (or terminal) and connect the otherend to the DE-9 connector or the RS-232 header next to the DE-9 connector.Make sure the COM port parameters or the terminal has the following settings:♦ Baudrate 9600 Baud, 8 data bits, no parity, Xon/Xoff disabled, no hardware handshake.

19. Press the RESET button.The monitor identification message should appear if the baudrate is OKAdjust the trim pot R11 a little if the text output is garbage. The frequency at the pin #5 ofIC27 must be 153.6 kHz (if you have a frequency counter).When you do not see any text at all on the terminal, try the reversal of the TxD and RxD pin.When you use the RS-232 header it is easily corrected by just turning the connector 180°.

20. Turn off the power supply.Congratulations! You have a working Core Board on your desk.

2. Assembly of the I/O Board

The I/O board only contains the octal latches soldered directly on the board, bypass capacitors andone electrolytic polarised capacitor. If you want to put the octal latches in sockets you must buythe sockets, as these are not included in the kit. The proposed soldering order is as follows.1. Solder the CORE-IO header.

2. Decide how you will arrange the position of the Core Board and the I/O board and make theflat cable that connects the two boards. Connect the Core and I/O Board with the flat cableand apply the +5V power to the Core Board through JP4. *** Notice the correct polarity! ***

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© Check. Connect the (-) connector of the multimeter to the pin #10 of any octal latch. Set the multimeter to a DC Voltage setting higher than 5V (for example 20V). Connect the (+) connection of the multimeter to pin #20 of any octal latch. The meter must indicate a positive 5 V. In that case you know that the flat cable is OK.

3. Turn the power supply off, and disconnect the flat cable from the I/O Board.

4. Solder the 3 decoder IC’s, or in a single I/O Board configuration, solder only the decoder IC9and IC10 saving a little power consumption. Notice the orientation of the sockets or the IC’s.

5. Solder all the latches or only the input and output latches that you need for your application.If you choose the use IC sockets, solder the sockets.Whatever your choice: Notice the orientation of the sockets or the IC’s.

6. Solder the bypass capacitors.

7. Solder the electrolytic polarised capacitor. Notice the correct polarity!

8. Solder the header JP1 (if needed, you can also solder a jumper wire if this is a one-timeconfiguration connection, see the “Configuration” chapter).Solder the header JP2, and the headers for the input and output ports.

9. Install the IC’s if you used sockets.

• Take care that you put the IC’s in the correct orientation!

This is how your I/O Board will look after these steps.Again, take a break and admire your work!

Note: this is the prototype I/O Board with the components bought in The Netherlands.Your components can look different. I used sockets for all IC’s to allow measurement checks, asthis is the prototype.

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Configuration of the “Real Console”

1. Jumper settings on the Core Board

The Core Board has the following jumpers / connectors.

JP4 CORE-IO JP3 DEBUG 27128/27256 RS-232 EPROM/RAM JP1

(Component side view)

JP1 External RESET push-button.Normally Open button to reset the Real Console externally.

DEBUG External Real Console / Debug Monitor start-up. Normally Open button.After power-up or reset the Real Console starts its application; when during reset orpower-up the button contacts are closed, the Debug Monitor is started.

JP3 PIA 6821 CB1 input pin.The CB1 pin has a pull-up resistor of 3300 Ω. The other pin is connected to GND.The CB1 pin is available for another application on the Real Console.

JP4 +5 V / GND power supply connector(optional, as there is also a power connector on the I/O Board)Make sure you connect the power supply correctly …!!

RS-232 Serial port connection (parallel to COM connector)If the Real Console is built inside a box you can use the RS-232 connector insteadof the 9-pin connector.NOTE: if you use the RS-232 connector you can simply swap to null-modem orstraight connection by connecting the 3-pin connector the other way around.

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27128 /27256

Boot EPROM type selection / “bank” selection.If the IC23 is a 27128 you must connect the 2 pins at the text “HI/27128”. If IC23 isa 27256 (cheaper) you have the option of selecting the upper or the lower half of theEPROM. In the “HI/27128” position the upper half (E000-FFFF) is active, and inthe “LO/27256” position the lower half is active (C000-DFFF).Remark: the selected half must contain the boot code.

! Jumper on Pin #1 - #2 (“LO”)– EPROM type = 276256 (lower 16k byte visible)

! Jumper on pin #2 - #3 (“HI”)– EPROM type = 27128 or– EPROM type = 27256 (upper 16k byte visible)

EPROM /RAM

Device selection of IC29, either 27256 EPROM or 62256 RAM.2 jumpers on pins #1-#2 and #3-#4 is for EPROM, #2-#3 and #4-#5 is for RAM.

! Jumpers on #1 - #2 and #3 - #4IC29 = 27256 EPROM

! Jumpers on #2 - #3 and #4 - #5IC29 = 62256 RAM

Note: 2 jumpers used !

CORE-IO Interface connection between the Core and the I/O board.

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2. Jumper settings on the I/O Board

The I/O Board has the following jumpers / connectors.

OUT1-2 / OUT7-8 CORE-IO JP1 JP2 IN1-2 / IN7-8

(Component side view)

OUT1-2OUT3-4OUT5-6OUT7-8

Output port connectors. OUT 1 / 3 / 5 / 7 OUT 2 / 4 / 6 / 8 bit 7 = pin 7 bit 3 = pin 8 bit 7 = pin 15 bit 3 = pin 16 bit 6 = pin 5 bit 2 = pin 6 bit 6 = pin 13 bit 2 = pin 14 bit 5 = pin 3 bit 1 = pin 4 bit 5 = pin 11 bit 1 = pin 12 bit 4 = pin 1 bit 0 = pin 2 bit 4 = pin 9 bit 0 = pin 10

IN1-2IN3-4IN5-6IN7-8

Input port connectors. IN 1 / 3 / 5 / 7 IN 2 / 4 / 6 / 8 bit 7 = pin 7 bit 3 = pin 8 bit 7 = pin 15 bit 3 = pin 16 bit 6 = pin 5 bit 2 = pin 6 bit 6 = pin 13 bit 2 = pin 14 bit 5 = pin 3 bit 1 = pin 4 bit 5 = pin 11 bit 1 = pin 12 bit 4 = pin 1 bit 0 = pin 2 bit 4 = pin 9 bit 0 = pin 10

JP2 +5 V / GND power supply connectorMake sure you connect the power supply correctly …!!

CORE-IO Interface connection between the Core and the I/O board.

JP1 Device Selection (optional header).This 18-pin header or jumper selects the I/O Board number if more than one I/OBoard is connected or selects the I/O Board in a single I/O Board configuration.

jumper between pins I/O Board 17 - 18 single -- IC19 (74LS138) can be omitted 15 - 16 #1 13 - 14 #2 11 - 12 #3 9 - 10 #4 7 - 8 #5 5 - 6 #6 3 - 4 #7 1 - 2 #8

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Introduction to the “Real Console”

The idea for this project started in 2002. I had collected a few PDP-11’s, but did not want to turn themon too often. However, I wanted to ‘play’ with the Operating System, wanted to learn more, and wasthinking of writing programs on a PDP-11 to run on a PDP-11. With SIMH or Ersatz-11 all this is alsopossible on a PC or any other computer for which SIMH can be compiled or Linux can run.While I was working on a PC, I missed the nostalgic feeling and the appearance of a full console withall the switches, momentary switches and lights. Such a console is called a “blinkenlight” console.Ersatz-11 enables you to connect 16 LED’s to the parallel port of a PC, but I wanted to whole thing.So, the idea developed to build my own blinkenlight console and connect that to the PC somehow.Since the demo version of Ersatz-11 does not offer the control of a parallel port, only the serial ports, itwas decided that whatever I would build must connect to the PC via the serial port.As my development was intended for the PDP-11 console you will see that specific computer modelfrom DIGITAL throughout this manual, but it could easily have been PDP-8, or in fact every othercomputer with a blinkenlight console that is supported by SIMH.

I decided that the blinkenlight console (called “Real Console”) must have the following properties.

# Built with simple, easy available components, no PAL’s, etc. except the programmed EPROM.# PC-compatible RS-232 serial interface

(full duplex, 9600 Baud, 8 data bits, no parity, 2 stop bits [8N2] , no CTS/RTS or DSR/DTR)# Software adaptation in SIMH allows control from and of the Real Console (bi-directional).# Supports three operating modes.# Stand Alone mode# Console mode# Debug Monitor mode# In “PDP-11” console mode, every "blinkenlight" console of the PDP-11 family can be selected,

PDP-11/05, PDP-11/10, PDP-11/20, PDP-11/35, PDP-11/40, PDP-11/45, PDP-11/55, PDP-11/70.However, the initial design is specifically for the PDP-11/35 (OEM) also known as PDP-11/40.It is also possible to connect a PDP-11/34 or PDP-11/60 style console, the one with a calculator stylekeypad and a 6 digit 7-segment read-out. Basically you can control many more with this design.

1. Operating modes of the Real Console

• Stand-Alone modeAfter power-up, the µP console interface initialises into "Stand-Alone mode".The Stand-Alone mode has the following properties.1. The 16 DATA LED’s show a 'walking' light pattern. Several patterns can be started.2. The ADDRESS/DATA switches are “echoed” to the ADDRESS LED’s.

The function switch and the momentary switches are “echoed” to the FUNCTION /STATUS LED’s.

3. The serial interface does not transmit any data.4. The serial interface listens to any data, but all data is ignored except the following:

! Query command(two versions: a single response and a repeated response at 1 second intervals)

! Define momentary switch Mask! Clear momentary switch Indicators

(two versions: Clear All and Clear Specified momentary switch)! Start PDP-11/xx Console Mode

5. The diagnostic LED on the 6809 µP board blinks at 1 Hz.

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• Console modeWhen the µP console interface receives the "Start Console mode" message, it will wait for asecond message byte that tells what console model must be emulated. This message byte mustfollow directly after the "Start Console mode" message.After the "Start Console mode" message is received completely, the diagnostic LED on CoreBoard blinks at 1 Hz and all LED’s on the 'real' console are turned off.If the second byte is not a valid model type code, the console reverts to the Stand-Alone mode.After a valid model type code is received, the serial interface listens for any message type.Illegal messages are discarded. The implemented message types are the following.

! "Command" messages! "Information" messages! "Data Request" messages

The serial interface transmits only messages when requested to do so. However, a DataRequest message exists that directs the µP board to transmit all switch information.

• Debug Monitor modeThe Debug Monitor mode can be activated by keeping the DIAG button pressed while the µPis reset, by the RESET button or by cycling the DC power supply.In the Debug Monitor mode, the serial port is used to communicate with a (VT220) terminalor any other terminal emulation program like HyperTerminal. A simple monitor starts andcommands can be entered via the terminal.The Debug Monitor mode uses the serial interface to connect to a terminal, and the diagnosticLED on the Core Board blinks at 2 Hz.

2. Brief hardware descriptionThe design is based on the Motorola MC6809 µP. This choice is purely based on my knowledge ofthe Motorola CPU family and the expertise in assembly programming them. The main componentsof this single board processor design (called the Core Board) are the following.! Motorola MC6809 processor, clocked at 1 MHz! Motorola MC6850 ACIA and MAX232A for the serial communications port (RS232)! Motorola MC6821 PIA to interface to input ports and output ports, the I/O Board! EPROM 27128 (16k bytes firmware space, 8k actually used)! EPROM 27256 (optional, to hold other user application programs)! 6264 8k RAM! Standard 74LS TTL logic! on-board diagnostic LED! NE556 dual timer for the serial port (baudrate) and timer interrupt generation

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The databus of the processor connects to all the system components, the RAM, ACIA, PIA and the2 EPROM’s. The addressbus of the processor connects to these system components too, and someaddress lines are used in the decode logic to decode the system components at a specific locationin the memory space (see the appendix for the details). The decode logic also has a circuit togenerate a power-up reset signal or a reset signal from a push-button.A modem handshake pin on the ACIA is used to read the state of a push-button immediately afterreset. This push-button called “DEBUG” determines which software starts after reset. Default theReal Console application is started, but if the push-button is pressed during reset the debugmonitor software is started.The output ports of the PIA are buffered with 74LS245 bi-directional buffers and make theinterface between the Core Board and the I/O Board. The I/O_CNTRL connection is alwaysconfigured as outputs; the I/O_DATA connection is switched from input to output if necessary.The Default State for the I/O_DATA connection is input direction (to the Core Board).

The I/O Board connects through a 20-wire flat cable to the buffered outputs of the Core Board, theI/O_DATA and the I/OCTRL ports. Each I/O Board has eight 8-bit input ports (74LS373), andeight 8-bit output ports (74LS374). The output ports can drive LED’s directly (with an externalresistor). The 74LS138 OUTport SEL strobes the data on the I/O_DATA port to the selectedoutput latch. The 74LS138 INport SEL reads the data to the I/O_DATA port from the selectedinput latch. The latches are selected with 3 bits from the I/O_CTRL port. A 4th bit that comes fromthe jumper JP, functions as an I/O-card enable. The I/O-card enable is generated through 3 bitsfrom the I/O_CTRL port that are decoded to 8 enable signals by the 74LS138*.The most significant bit of the I/O_CTRL port acts as an enable signal for the 74LS138* or, if thesystem has only one I/O Board, acts as the enable signal for the 2 74LS138 port SEL devices.So, one jumper (JP) on the I/O Board determines if only one I/O board is used, or more (up to 8!).In the latter case the jumper defines the I/O Board number.

3. Brief firmware descriptionThis section describes the Real Console application only. See the “Sources” at the end for areference to the debug monitor CORESYS-09.The Real Console main program is a loop. The software in the loop listens to the serial port. Whena command is recognised the command is immediately executed. Examples of these commands aresending data to a specified output latch, and information about the switches and momentary

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switches connected to the input ports. Since the output latches are read-only, the softwaremaintains a shadow register of all the output ports. That way it is possible to update just one bitwithout affecting the other bits.The other part of the Real Console software is an interrupt service routine that is executedapproximately 50 times per second. The interrupt routine takes care of the following actions:1. Flash the diagnostic LED on the Core Board at 1 Hz interval2. Read the position of the switches and de-bounce the switch contacts3. Read the position of the momentary switches and remember that it has been activated (even if

the momentary switch is released again)The interrupt routine stores the processed data of the switches and momentary switches in an array.The application does not need to take care of the scanning and de-bouncing process.Note. The array has room for all 8 input ports. If you connect more I/O Boards, you must adjustthe source code accordingly, and make a new EPROM.

4. An example: “The implementation of the PDP-11/40 console”This chapter gives an explanation of the PDP-11/40 console that is implemented in the firmware.The firmware provides for generic interface functions, but if you understand 6809 assembler, youcan write your own dedicated console application. Using the generic function interfaces you cannot combine output bits of different data types, for example in the PDP-11/40 console theADDRESS LED’s A16 and A17 and the function/status LED’s (RUN, PROC, etc.). Combiningthese output bits could save one output port (and latch), but it requires a modification in the RealConsole firmware, or a change to handle the combination in SIMH (see next chapter).

First, divide the LED’s of your console in logical groups. Do the same for the switches. Connectthe LED’s and switches in the same binary order as their ‘value’ indicates (modulo 8). Connect thestatus/function switches and momentary switches to the remaining bits.Looking at the PDP-11/35 (OEM version of the 11/40) console we see the following components.

! DATA LED’s DATA_0 through DATA_15! ADDRESS LED’s ADRS_0 through ADRS_17! STATUS LED’s RUN, BUS, USER, PROC, CONSOLE, VIRTUAL! SWITCH REGISTER SW_0 through SW_17! FUNCTION switch ENABLE/HALT! FUNCTION momentary switches LOAD ADRS, EXAM, CONT, START, DEP

Make a list, and group similar LED’s or switches together.See the following table as an example for the PDP-11/35 console.

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Console component Output portInput port

Bit assignment

DATA LED’s! DATA_15 through DATA_8

! DATA-7 through DATA_0

OUT-0

OUT-1

Highest DATA LED connects to highest bit.DATA_15 $ bit #7DATA_8 $ bit #0DATA_7 $ bit #7DATA_0 $ bit #0

ADDRESS LED’s! ADRS_15 through ADRS_8

! ADRS-7 through ADRS_0

! ADRS_17 and ADRS_16

OUT-2

OUT-3

OUT-4(see Note 1)

Highest ADRS LED to highest bit.ADRS_15 $ bit #7ADRS_8 $ bit #0ADRS_7 $ bit #7ADRS_0 $ bit #0ADRS_17 $ bit #1ADRS_16 $ bit #0

STATUS LED’sRUNBUSUSERPROCCONSOLEVIRTUAL

OUT-5(see Note 1) Bit #2

Bit #3Bit #4Bit #5Bit #6Bit #7

SWITCH REGISTERSW_15 through SW_8

SW_7 through SW_0

SW_17 and SW-16

IN-0

IN-1

IN-2(see Note 2)

Highest Switch connects to highest bit.SW_15 $ bit #7SW_8 $ bit #0SW_7 $ bit #7SW_0 $ bit #0SW_17 $ bit #1SW_16 $ bit #0

FUNCTION switchENABLE/HALT

IN-3(see Note 2) Bit #7

FUNCTION momentary switchesLOAD ADRSEXAMCONTSTARTDEP

IN-3(see Note 2) Bit #6

Bit #5Bit #4Bit #3Bit #2

After the console components have been assigned to the output and input ports and the bits in eachport, the set-up of the Real Console only needs one more item. The firmware must know on whichinput ports and which bit positions there are momentary switches connected. This is needed for thespecial processing that is required for the momentary switches.The needed interface routines are the following.

DEFINE_MSWITCH (Input_port-#, bitmask)SEND_DATA (Output_port-#, Output_data)Input_data = READ_SWITCH (Input_port-#)

The “DEFINE_MSWITCH” interface is called once for every input port that has momentaryswitches connected.The call for the example of the PDP-11/40 would be:

DEFINE_MSWITCH (IN_3, 0b01111100)

The “SEND_DATA” and “READ_SWITCH” are called by the controlling application, SIMH. Theintelligence and the functional implementation (behaviour) are defined in SIMH.

17

Note 1. OUT-4 and OUT-5 are combined exactly 8 bits. With a change in the firmware you canmake this combination and still keep the functional difference intact. The change is neededotherwise writing the ADRS_17 and ADRS_16 would clear the other 6 status LED’s.

Note 2. IN-2 and IN-3 could be combined just as described in Note 1.

For the PDP-11/40 console in the firmware I have written a set of commands that operate at onelevel higher. There is an “ADDRESS” interface routine for example that accepts a 3-byte address.How this 3-byte information is displayed on the LED’s and at which ports is completely hiddeninside the firmware. Likewise, there is such an interface for “DATA” and for “FUNC_STS”.

SIMH reads all the switches and momentary switches periodically and acts appropriately on thebits set. As told, the activated momentary switch is “remembered” in the Real Console application.After SIMH has processed the activated momentary switch its flag must be reset, with thefollowing interface routine:

CLEAR_MSWITCH (IN_3, <bitmask>)

The <bitmask> must have a logic “1” at the position that corresponds with the momentary switchposition in the input port. You can clear just one momentary switch or all momentary switches onthe specified input port with one call.

5. How to implement the required modifications to SIMHSIMH must do two actions:1. Read the switches and momentary switches of the Real console periodically to provide a

“real-time” response to the user,2. Update the ADDRESS, DATA, and STATUS LED’s as a response to a user action on the

Real Console, or as an indication of the running simulation in SIMH.

Special events in SIMH must also update the LED’s. Examples of special events are the HALTexception, and single step execution of the simulated software.The LED’s on the Real Console are not updated in “real-time” because that would create anenormous overhead, as all this information must be transmitted over the serial link. In the SIMHsoftware at the appropriate locations the call to a routine is made that counts the number of callsmade to it. When the count reaches a defined threshold or a “force-update” flag is set, the messageis sent to the Real Console. The message contains information for all the LED’s or for just onegroup. The threshold can be defined when the presence of the Real Console is told to SIMH.The changes applied to the files of SIMH can be downloaded from my web site, see “Sources”.

18

Appendix A: Debug monitor – <CORESYS-09>

The Real Console has a simple monitor that can be started by keeping the DIAG button on the µPboard pressed while the µP is reset by the RESET button or cycling the DC power.When the DIAG button is pressed during reset, the Real Console will start in the Debug Mode and, if aterminal is connected to the serial port, the monitor identifies itself by the * prompt.The following table list the commands recognised by the debug monitor.

CORESYS-09 debug monitor commandsREG Display all processor registersCONT Continue from current PC, resume from breakpointEXEC <addr> Execute program from address <addr>MEMORY <range> [opt] Display memory <range>

“opt” not used: address and data (e.g. 2A68=7E 2A69=E3 … etc)“opt” = DATA: only data (e.g. 7E E3 … etc)“opt” = USED: display ‘.’ if byte is zero, ‘+’ if byte is not zero

SET <range> <value> Set memory <range> to <value> (value is max 8 bytes listSET <register> <value> Set CPU <register> to <value>

<register> == [ .CC | .A | .B | .AB | .IX | .IY | .IU | .PC | .SP ]TEST <range> Test memory <range>BREAK ? Display breakpoint addressBREAK <addr> Remove current breakpoint, set new breakpoint at address <addr>BREAK Remove breakpointCOPY <range> <addr> Copy memory <range> <destination address>IBASE ? Show current input number base systemIBASE <base> Set input number base to <base>DBASE ? Show current display (output) number base systemDBASE <base> Set display (output) number base to <base>DUMP <range Dump memory <range> in S1-S9 Motorola recordsLOAD Read Motorola S1-S9 records into memorySEARCH <range> <data> Search memory <range> for <data> (data list max is 6 bytes)CLI Clear IRQ maskCLF Clear FIRQ maskSEI Set IRQ maskSEF Set FIRQ maskIRQ <addr> Set IRQ vector to <addr>FIRQ <addr> Set FIRQ vector to <addr>NMI <addr> Set NMI vector to <addr>RSRVD <addr> Set RSRVD vector to <addr>SWI <addr> Set SWI vector to <addr>SWI2 <addr> Set SWI2 vector to <addr>SWI3 <addr> Set SWI3 vector to <addr>DISAS <range> Disassemble memory <range> to 6809 mnemonicsBASIC Simple 16-bit signed integer BASIC interpreter$! “Dollar-Bang” $ start Real Console Mode -- “debug” flag set

<range> specification <base> specification

ADDRESS1:ADDRESS2 $ from address1 to address2 HEX $ number base system set to hexADDRESS1!COUNT $ from address1 ‘count’ bytes DEC $ number base system set to decimalADDRESS1 $ single address1 OCT $ number base system set to octal

BIN $ number base system set to binary

19

Appendix B: Protocol description

You can start the Stand-Alone mode with the “Dollar-Bang” command of the debug monitor.However, if you start the Real Console through the “$!” command, the software sets a “debug” flag,while starting immediately the Real Console, from power-up or reset, this “debug” flag is cleared.This “debug” flag defines the way the Real Console commands are expected.

The console commands can be in ASCII (“debug” enabled) or in binary format (“debug” disabled).The ASCII format is implemented to facilitate manual testing of all hardware, including a PDP-11/xxconsole. When “debug” is enabled the Real Console application responds with messages and shows aprompt to enter (test) commands. In normal operation the binary format is used because it is a littlemore efficient in the transmitted amount of data.Note: the commands are as shown in the table. The commands do not contain spaces and are not terminated by a Carriage Return!

Real Console commands -- Stand-Alone mode , “debug” not active

p<number> Start console # <number> modeThe ASCII numeric digit (0…8) defines the console to be emulated.• The command “p0” (zero) does not define any momentary switch

mask, but enables to go from Stand-Alone to [user-defined] Consolemode.

Real Console commands -- Stand-Alone mode , “debug” active

t<port><data> Define momentary switch (toggle) mask.The bits that are set in <data> define that at that input pin of the <port> amomentary switch is connected instead of a normal 2-position switch.<port> is one ASCII number (0 … max)<data> is 2-digit ASCII hexadecimal (00 … FF).

Note. The current implementation allows for one I/O Board (#0).

p<number> Start console # <number> modeThe ASCII numeric digit (0…8) defines the console to be emulated.• The command “p0” (zero) does not define any momentary switch

mask, but enables to go from Stand-Alone to [user-defined] Consolemode.

I Clear all active momentary switch indicators.A momentary switch that is once pressed caused a flag bit to be set in thesoftware. As long as the flag bit for this momentary switch is not cleared,pressing that momentary switch has no effect. The “i” command clears allthese indicators.

In the Stand-Alone mode the “DATA” LED’s show a repeated pattern. The pattern is selected at start-up through the switches [2-1-0] of the Switch Register.The position of the switches of the Switch Register is displayed on the “ADDRESS” LED’s.The position of the momentary switches is displayed on the LED’s that show the status (e.g. “USER”,“PROC”, etc).The LED is only on as long as the momentary switch is pressed. However, after the “t” command, oncea momentary switch is pressed the LED remains on until the “i” command is given.

20

Real Console commands -- Console mode

s Start Stand-Alone mode (small letter “s”)

p<number> Start console # <number> modeThe ASCII numeric digit (0…8) defines the console to be emulated.• The command “p0” (zero) does not define any momentary switch

mask, but enables to go from Stand-Alone to [user-defined] Consolemode.

D<data> Output <data> to the output port 1 and output port 2.By default these 2 output ports are connected to the “DATA” LED’s.• “debug” mode enabled

<data> is 4-digit , 4 bytes ASCII hexadecimal (0000 … FFFF)• “debug” mode disabled

<data> is 4-digit , 2 bytes binary value (0000 … FFFF)

A<data> Output <data> to the output port 3, 4 and output port 5.By default these 3 output ports are connected to the “ADDRESS” LED’s.• “debug” mode enabled

<data> is 5-digit , 5 bytes ASCII hexadecimal (00000 … 3FFFF)• “debug” mode disabled

<data> is 5-digit , 3 bytes binary value (0000 … 3FFFF)

Note. The address range is a specific implementation for the PDP-11/40console. Simple changes in the firmware will allow for a 22-bit range.

B<address><data> A combination for the “D” and the “A” command.The command is only for “debug” mode disabled. The first 3 bytes arefor the ADDRESS LED’s, and the last 2 bytes are for the DATA LED’s.

F<data> Output <data> to the output port 5.By default this output port are connected to the “FUNCTION” LED’s.• “debug” mode enabled

<data> is 2-digit , 2 bytes ASCII hexadecimal (00 … FF)• “debug” mode disabled

<data> is 2-digit , 1 byte binary value (00 … FF)

Note. The “Function/Status” LED’s are connected to the same port thatconnects to the “Address” LED’s, A17-A16. The implementation takescare that writing to output port 5 only affects the specific bits.

l<port><data> Output <data> to the output port <port>. Command is a small letter “el”.• “debug” mode enabled

<port> is 1-digit, 1 byte ASCII number<data> is 2-digit , 2 bytes ASCII hexadecimal (00 … FF)

• “debug” mode disabled<port> is 1-digit, 1 byte hexadecimal number<data> is 2-digit , 1 byte binary value (00 … FF)

t<port><data> Define momentary switch (toggle) mask.The bits that are set in <data> define that at that input pin of the <port> amomentary switch is connected instead of a normal 2-position switch.• “debug” mode enabled

<port> is 1-digit, 1 byte ASCII number<data> is 2-digit , 2 bytes ASCII hexadecimal (00 … FF)

• “debug” mode disabled<port> is 1-digit, 1 byte hexadecimal number<data> is 2-digit , 1 byte binary value (00 … FF)

Note. The current implementation allows for one I/O Board (#0).

c<port><data> Clear active momentary switch indicator(s).A momentary switch that is once pressed caused a flag bit to be set in thesoftware. As long as the flag bit for this momentary switch is not cleared,pressing that momentary switch has no effect.

21

The “c” command clears the indicator bits that are in the set positions ofthe data for in the specified port.<port> and <data> are as specified in the “t” command.

i Clear all active momentary switch indicators.A momentary switch that is once pressed caused a flag bit to be set in thesoftware. As long as the flag bit for this momentary switch is not cleared,pressing that momentary switch has no effect. The “i” command clears allthese indicators, even when the momentary switches are defined atseveral input ports.

Commands that generate a response to the senderH Request the current position of the “HALT/ENABLE” switch.

$ The firmware will send a one-character answer.• “H” - the switch is in the “HALT” position.• “E” - the switch is in the “ENABLE” position.

Whenever the position of this switch is changed, the firmware will sendthe switch position (H or E) unsolicited to the simulator.

Note. This command is implemented to enable the simulator to requestthe position of this switch, otherwise its position would be unknown untilits position is changed at least once.

Q “Query”. Request the switch data from all switches and momentaryswitches (all input ports effectively).$ The firmware will send one byte for every defined input port. As “query” (see below), but the switch data is transmitted only once.

q

<ESC>

“Query”. Request the switch data from all switches and momentaryswitches (all input ports effectively).$ The firmware will send one byte for every defined input port.$ The input port data is transmitted every second again.• Abort the periodic transmission by entering the “Esc” character.

22

Appendix C: Detailed hardware description

1. The Core BoardMost of the Core Board design is straightforward. The data bus is connected to the EPROM(s),the RAM, and the peripheral devices ACIA and PIA. The address bus is connected to thesedevices as well for the appropriate address lines to access the information in these devices.The address selection logic is explained here.

The address lines A15 and A14 generate the active low signals EP and EP1\ via the IC28A.EP is active when A15=0 and A14=0, EP1\ is active when A15=1 and A14=1.The EP and EP1\ signal go the second decoder, IC28B, and generates the active low signals0123\, CDEF\, and 4-B\ when the E\ signal from the output of IC18C according this table.

EP EP1\ 0123\ CDEF\ 4-B\ remark

0 0 1 1 1 input state not possible

1 0 0 1 1

0 1 1 0 1

1 1 1 1 0

23

You can say that the output 0123\ is active when an address is given from the CPU that lies in therange $0000 - $3FFF. The output CDEF\ is active in the address range $C000 - $FFFF, and theoutput 4-B\ is active in the range between them, that is $4000 - $BFFF.

The signal 0123\ goes to the CS1\ and the OE\ pin of the 6264, and address line A13 connects toCS2 of the 6264. The signal CDEF\ goes to the CE\ and OE\ pin of the first EPROM, the 27128or 27256. For the 27128 PGM, pin 27 must be connected to +5V, for the 27256 pin 27 is A14. Ifthe 27256 is used you can connect pin 27 either to +5V or to GND thus selecting the upper or thelower half of the 27256. Remember that the active half of the EPROM must contain the reset andinterrupt vectors and some start-up software!

The 4-B\ signal goes to the CE\ and OE\ pin of the optional EPROM, the 27256. However weapplied a trick to correct the addressing for this 32k EPROM. The 4-B\ signal is generated fromthe address lines A15 and A14 via IC28A and IC28B.

A15 A14 EP EP1\ 0123\ CDEF\ 4-B\

0 0 0 1 0 1 1

0 1 1 1 1 1 0

1 0 1 1 1 1 0

1 1 1 0 1 0 1

Address lines A15/A14 and the output signals of IC28A/B.

From the table you can see that the 4-B\ signal is active when 0123\ and CDEF\ are not active.Suppose we connected the optional 27256 EPROM with its address pins to the correspondingaddress pins of the 6809. That would mean that A14 of the EPROM is connected to A14 of theCPU. That would map the EPROM as follows in the address space.

A15 A14 A13 A12 A11-A8 A7-A4 A3-A0 Selected 27256 address space

0 0 * * **** **** **** Not selected, 4-B\ inactive

0 1 01

01

00001111

00001111

00001111

$4000 - $7FFFUPPER 16k selected

1 0 01

01

00001111

00001111

00001111

$0000 - $3FFFLOWER 16k selected

1 1 * * **** **** **** Not selected, 4-B\ inactive

(*) is a “don’t care” value, can be logic 0 or logic 1.

Without a change this scheme would mean that you must store the data in the optional EPROMkeeping in mind that the upper and lower halves are swapped in the memory map! This is notacceptable of course. But when we take a closer look at the table we see that when the EPROM isselected A14 and A15 are each other complement. So to correct the swapped condition of the 2halves of the EPROM the address line A15 of the 6809 is connected to the A14 pin of the 27256.

The outputs of the 1-of-8 decoder, IC19, can only be active when the signal 0123\ is active. Withthe select inputs A, B, and C connected to the address lines A4, A5 and A6 each output is activein one block of 16 bytes. Because of A7 the 16-bytes must be in the lower half of a 256 bytesgroup. A13 is used to limit the active state of the outputs to the address range below $1000.

The IO-E\ output enables the access to the 6821 PIA, and the IO-F\ output enables the access tothe 6850, ACIA. The other outputs of IC19 are not used, see the remark below the Memory Map.

24

Memory map

ADDRESS RANGE DESCRIPTION$0000 - $00DF Range not used, but decoded. See remark.$00E0 - $00EF 6821 PIA registers, every 4 bytes repeated$00F0 - $00FF 6850 ACIA registers, every 2 bytes repeated$0100 - $1FFF not used, not decoded$2000 - $3FFF 8k byte RAM, lower 512 bytes ($2000-$2200) used by Monitor and

Real Console applications$4000 - $BFFF 32k bytes --optional-- 27256 EPROM or 62256 RAM$C000 - $FFFF 16k bytes 27128 EPROM, holds boot code and applications.

The jumper enables the use of a 27256 EPROM, but only 16k bytes ofthe 32k bytes space in the EPROM is “visible”. The jumper defineswhich half of the EPROM is active, and mapped to $C000 - $FFFF.

Remark:The address range of $0080 to $00DF is decoded on the Core Board in blocks of 16 bytes.These decoded signal are not used which means that there are 6 ‘trigger’ signals available.These signals are not wired to a connector.The ‘trigger’ signal is active when an instruction references any address in the 16-byte boundary,for example $0080 - $008F. Normally the triggers are logic “1”.A read instruction at address $0080 will cause a logic “0” for approximately 1 - 2 µs.

2. The I/O BoardThe I/O board has 8 octal latches that are used as 8 output ports, and 8 octal latches that are used as8 input ports. The output port latches are 74LS374’s that have an edge-triggered sensitive clockpin. The input port latches are 74LS373’s that are set in transparent state (ENC=”1”) so that theoutput pins always reflect the state of the input pins where the switches and momentary switchesare connected.

The input pins of the output latches and the output pins of the input latches are all connected to theI/O DATA port (see the figure). The input pins do no harm, but it is obvious that when data mustbe written no output of the input ports may be active. When an input port must be read only thatinput port may be active. This is accomplished by controlling the OC\ pins (3-state control).

25

Eight signals (IN00 through IN07) control the input ports and eight signals load the data to theoutput ports (OUT00 through OUT07).The signals IN00 through IN07 and OUT00 through OUT07 are generated from the signals of theI/O_CTRL port with the following decoders.

The 3-to-8 decoders IC9 and IC10 select one of the INxx and OUTxx signals with the I/O_CTRLbit 2, bit 1, and bit 0. I/O_CTRL bit 6 selects which decoder is active, thus defining if bits 2-1-0are used for a read or a write action.I/O_CTRL bit 7 acts as a general “enable” for the I/O Board. If the system has only one I/O Boarda jumper must be installed on the pins #17 - #18 of JP1.If the system contains more than one I/O Board the 3-to-8 decoders IC19 uses the I/O_CTRL bit 5,bit 4, and bit 3 to enable one I/O Board of the system. I/O_CTRL bit 7 acts as the enable for IC19.The jumper is removed from the pins #17 - #18 and installed on another position on JP1, definingthe I/O Board number in the system.

bit 7 bit 6 bit 5 - 4 - 3 bit 2 -1 - 0 INport active OUTport active

1 * * * * * * * none none

0 0 0 0 0 000 - 111 I/O #0 : IN00 - IN07 none

0 1 0 0 0 000 - 111 none I/O #0 : OUT00 - OUT07

0 0 0 0 1 000 - 111 I/O #1 : IN00 - IN07 none

0 1 0 0 1 000 - 111 none I/O #1 : OUT00 - OUT07

0 = = = = === - === =============== ==================

0 0 1 1 1 000 - 111 I/O #7 : IN00 - IN07 none

0 1 0 0 0 000 - 111 none I/O #7 : OUT00 - OUT07

(*) is a “don’t care” value, can be logic 0 or logic 1.

26

3. Connection between Core and I/O Board

The connection between the Core and the I/O Board is a single 20-wire flat cable.If the system consists of more than one I/O Board the flat cable is continued from the first I/OBoard to the next I/O Board. The jumper on the I/O Board defines the I/O Board number.

Note how the flat cable must be connected to the sockets that connect to the CORE-IO headers onthe Core Board and the I/O Board. Pin #1 of both sockets must be at the same side.See the (side view) illustration below.

4. Connection I/O Board and external hardware

The pins of the outputs are directly connected to the 74LS374 octal latches. This means that youcan connect logic to it and even drive a LED from each output pin through a current-limiting seriesresistor. Note that TTL logic is bad in sourcing current to GND (just a few mA). These octallatches can sink current up to 24 mA, so a LED from the +5V to the output pin with a resistor of270Ω or 330Ω works great.The pins of the inputs are directly connected to the 74LS373 octal latches. To connect a switch youmust connect a pull-up resistor (say 10kΩ) from the input pin to +5V and from that input pin toone connection of the switch. The other connection of the switch goes directly to GND.

27

Appendix D: I/O Board load calculations

This appendix shows you how to calculate the maximum number of I/O Boards you can connect to theCore Board. The number of I/O Boards depends on the amount of latches on the I/O boards.For the load calculation it is assumed that each I/O Board is fully configured, that means eight 8-bitinput latches and eight 8-bit output latches.First the information from the TTL handbooks is summarised.

74 LS 245 ( on Core Board )

logic “0” 24 mAOUTPUT- drive I/O bus Data- drive I/O bus Control logic “1” 3 mA

logic “0” 0,2 mAINPUT- read I/O bus Data

logic “1” 20 µA

74 LS 374 ( on I/O Board -- drive outputs)

logic “0” 24 mAOUTPUT- drive LED’s, etc.

logic “1” 2,6 mA

logic “0” 0,4 mAINPUT- connected to I/O bus Data (always on I/O bus as “input” logic “1” 20 µA

74 LS 373 ( on I/O Board -- read inputs)

logic “0” 24 mAOUTPUT- drive I/O bus Data (read switches)

logic “1” 2,6 mA

logic “0” 20 µAOUTPUT- tri-state connected to I/O bus Data (logic level on bus by other device) logic “1” 20 µA

28

I/O bus Data Path - condition #1 : 74LS245 drives the I/O bus (output action)

Condition 1 (output action)

The 74LS245 outputs drive the I/O data bus on every I/O board. Each I/O Board has eight 74LS374inputs, and eight 74LS373 outputs in tri-state. Thus the load seen by the 74LS245 output is as follows.

74LS245 output 74LS374 74LS373 (tri-state) total load for 74LS245drive logic “0” 8 * 0,4 mA 8 * 20 µA 3,36 mAdrive logic “1” 8 * 20 µA 8 * 20 µA 320 µA

The output capability of the 74LS245 is for logic “0” 24 mA, and for logic “1” 3 mA (TTL handbook).Maximum number of I/O boards for 74LS245 when considered as output driving the I/O bus:

• for logic “0” : 24 mA / 3,36 mA = 7• for logic “1” : 3 mA / 320 µA = 9

Safe maximum = 7 I/O Boards (for above described condition)

I/O bus Data Path - condition #2 : 74LS373 drives the I/O bus (input action)

Condition 2 (input action)

LED’s

switchestogglestri-state

74LS245

( Core )

I/O bus Data

74LS373

( I / O )

inputs

74LS374

( I / O )

outputs

74LS245

( Core )

I/O bus Data

74LS373

( I / O )

inputs

LED’s

switchestoggles

74LS374

( I / O )

outputs

29

The 74LS373 outputs drive the I/O bus on every I/O Board and the inputs of the 74LS245 on the CoreBoard. The I/O Board with the active 74LS373 has seven 74LS373 outputs in tri-state and eight74LS374 inputs. All other I/O Boards have eight 74LS373 outputs in tri-state and eight 74LS374inputs. Thus the load seen by the active 74LS373 output is as follows.

logic “0” logic “1”Core Board 74LS245 (input) 0,2 mA 20 µA

74LS373 (output, tri-state) 7 * 20 µA 7 * 20 µAI/O Board (active)74LS374 (input) 8 * 0,4 mA 8 * 20 µA74LS373 (output, tri-state) N * 8 * 20 µA N * 8 * 20 µAI/O Boards (not active)

N boards in system 74LS374 (input) N *8 * 0,4 mA N * 8 * 20 µA

In formula, the active output of the 74LS373 on the selected I/O Board ‘sees’ the following load.

• drive logic “0” : 3,54 mA + N * 3,36 mA• drive logic “1” : 320 µA + N * 320 µA

[ where N is number of extra I/O Boards ]

The output capability of the 74LS373 is for logic “0” 24 mA, for logic “1” 2,6 mA (TTL handbook).Maximum number of I/O boards for 74LS373 when considered as output driving the I/O bus:

• for logic “0” : ( 24 mA - 3,54 mA ) / 3,36 mA = 6• for logic “1” : ( 2,6 mA - 320 µA ) / 320 µA = 7

Safe maximum = 6 I/O Boards (for above described condition)

I/O bus Control Path - 74LS245 drives the I/O Control bus 74LS138's (I/O chip decoders)

I/O bus Control

The 74LS245 outputs drive the I/O control bus on every I/O board.The bits 0, 1, and 2 are connected to the, B, and C select inputs of two 74LS138’s. The bits 3, 4, and 5are connected to the A, B, and C select inputs of one 74LS138. Bits 6 and 7 are connected to the G\input of two 74LS138’s. Thus the load seen by the 74LS245 output is as follows. * Note. Bit 7 is connected to only one G\ input in a single I/O Board system, not relevant for calculations.

Since all the inputs of the 74LS138 have the same load values, the worst case load condition is chosen:the 74LS245 drives two inputs of the 74LS138's per I/O Board.Specification of input currents for the 74LS138 (TTL handbook):

74 LS 138 A or B or C input G\ or G input total load for 74LS245 outputslogic “0” 20 µA 20 µA 320 µAlogic “1” 0,36 mA 0,36 mA 3,36 mA

[ 3 - 4 - 5 - 6 - 7 ]

[ 0 - 1 - 2 - 6 - 7 ]

74LS245

( Core )

I/O bus Control

74LS138

( I / O )

inputs

74LS138

( I / O )

outputs

I/O latch on I/O Board

I/O Board selection

30

The output capability of the 74LS245 is for logic “0” 24 mA, and for logic “1” 3 mA (TTL handbook).Maximum number of I/O boards for 74LS245 when considered as output driving the I/O Control bus:

• for logic “0” : 24 mA / 40 µA = 600• for logic “1” : 3 mA / 40 µA = 75

Conclusions for the maximum allowed I/O board configuration.

1) The 74LS245 that drives the I/O control bus is no limiting factor.2) The 74LS245 that drives the I/O data bus limits the maximum I/O board configuration.

- to drive a logic “0” :: max 7 I/O Boards- to drive a logic “1” :: max 9 I/O Boards

3) The 74LS373 that drives the I/O data bus also limits the maximum I/O board configuration.- to drive a logic level “0” :: max 6 I/O boards- to drive a logic level “1” :: max 7 I/O boards

Thus, in a maximum configuration (every I/O Board has 8 output latches and 8 input latches)the maximum I/O Board count is 6. If not all input latches are required on the installed I/OBoards, the calculations can be done (with the presented information), to see if a 7th I/O Board wouldbe within specification limits.The theoretical maximum of 8 addressable I/O Boards can not be achieved if the I/O Boards are allequipped with the maximum (8) input and output latches.

31

Appendix E: Firmware description

The following table gives the entry points and the description of subroutines in the monitor for use inapplication software. The addresses have a JMP instruction to the actual subroutines. The subroutinesreturn to the caller through the RTS instruction.

address label descriptionC000 inhex input one hex character and echo to output (if valid hex)

call : -return : cc = 0 : [A] = hex value cc = 1 : entry is CR or not hex no registers changed, except [A]

C003 in2hb input two hex characters in one byte and echo to output (if valid hex)

call : -return : cc = 0 : [A] = hex value cc = 1 : entry is CR or not hex no registers changed, except [A]

C006 incho input one char, reject control characters, and echo to output

call : -return : [A] = character ($20 - $7F) no registers changed, except [A]

C009 inch input one char, reject control characters, no echo to output

call : -return : [A] = character ($20 - $7F) no registers changed, except [A]

C00C ino input one char, no echo to output

call : -return : [A] = character ($00 - $FF) no registers changed, except [A]

C00F inchnb input one char, non-blocking, converted to uppercase

call : -return : cc = 0 : no entry available cc = 1 : [A] = uppercase character no registers changed, except [A]

C012 getbe output space, input begin and end address (begin < end)

call : -return : cc = 0 : hex entry begin & end address valid [X] = begin address // [Y] = end address cc = 1 : cv = 0 : entry terminated by CR cv = 1 : end address < begin address [A], [X] and [Y] destroyed

C015 sbaddr output space, input hex (2-byte) address

call : -return : cc = 0 : [X] = address cc = 1 : entry is CR or not hex [A] and [X] destroyed

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C018 baddr input hex (2-byte) address

call : -return : cc = 0 : [X] = address cc = 1 : entry is CR or not hex [A] and [X] destroyed

C01B outhl output one hex character, left half-byte (msb)

call : [A] = hex bytereturn : [A] most significant 4 bits printed as hex char [A] destroyed

C01E outhr output one hex character, right half-byte (lsb)

call : [A] = hex bytereturn : [A] least significant 4 bits printed as hex char [A] destroyed

C021 outb2 output one byte as two hex characters

call : [A] = hex bytereturn : [A] printed as two hex characters [A] destroyed

C024 outch output character

call : [A] = characterreturn : [A] printed no registers destroyed

C027 out2ch output two characters

call : [A] = first character [B] = second characterreturn : [A] printed followed by [B] printed [A] destroyed

C02A pdata print string

call : [X] = pointer to string, ended with EOT ($04)return : string printed [A] destroyed // [X] points to EOT byte

C02D newlin output new line

call : -return : carriage return (CR) line feed (LF) printed no registers destroyed

C030 outabt output one character, repeated

call : [A] = character to print [B] = number of times to print [A] ($00 = 256 times)return : [A] printed [B] times [B] = $00

C033 out2h output 2 hex characters from byte via pointer

call : [X] = points to byte to printreturn : byte printed as 2 hex [A] destroyed // [X] incremented by 1

C036 out2hs output 2 hex characters from byte via pointer, followed by one space

call : [X] = points to byte to print

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return : byte printed as 2 hex followed by a space [A] destroyed // [X] incremented by 1

C039 out4hs output 4 hex characters from word via pointer, followed by one space

call : [X] = points to word to printreturn : word printed as 4 hex followed by a space [A] destroyed // [X] incremented by 2

C03C outs output one space

call : -return : one space printed [A] destroyed

Remark: “cc” - condition code register C flag “cv” - condition code register V flag

Tiny BASIC

The firmware EPROM has plenty of room left, so a small 2k bytes BASIC interpreter is added.The code was found in the USEnet group comp.sys.m6809.The interpreter is started from the command prompt by entering “BASIC”. The interpreter works withsigned 16-bit integer, so the value range is +/- 32k. All commands must be entered in uppercasecharacters (use ‘CAPS LOCK’). The following commands are available:

NEW RUN LIST ? BYE STOP ENDREM LET IF GOTO GOSUB RETURN INPUTPRINT POKE PEEK USR MEM

When you enter a (small) BASIC program you must enter a line number followed by the statement.The BASIC code is not tokenized and is stored in memory in the following format.

! 2 bytes - hexadecimal line number! n bytes - the statement in ASCII! 1 byte - End-Of-Line indicator ($04)! 1 byte - End-Of-Text indicator ($FF) after the last line

When the command “BYE” is entered, the buffer start / end address and stack limit / top address isshown. You can use the buffer addresses to save your program with the DUMP command of themonitor. When you want to run that program again, use the LOAD command of the monitor to read theprogram into memory. Then start the BASIC interpreter.The interpreter will ask if you want to do a Cold start, or Warm start. If you choose “W” the 4 valuesthat were displayed after the “BYE” command must be entered. Entering a Carriage Return will startthe interpreter as if “C” was entered.

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Appendix F: Detailed electrical diagrams

Core Board - processor / ACIA / 6264 - part 1 (of 3)

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Core Board - PIA / EPROMs / Decode logic - part 2 (of 3)

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Core Board - Clock circuit - part 3 (of 3)

I/O Board - Decode Logic / bypass C’s - part 1 (of 3)

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I/O Board - output & input ports #0 - #3 - part 2 (of 3)

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I/O Board - output & input ports #4 - #7 - part 3 (of 3)

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Sources

! ASxxxx Cross Assembler (for 6809) - by Alan R. Baldwinhttp://shop-pdp.kent.edu/ashtml/asxxxx.htm

! MinGW - Minimalist GNU for Windows (C compiler for SIMH)http://www.mingw.org/download.shtmlor go to http://www.mingw.org/ and from there to the Download page.Get from the File list entry “Current” the MinGW (MinGW-3.1.0-1.exe 14,8 Mb).

! SIMH simulator program - “The Computer Simulation History” projecthttp://simh.trailing-edge.com/

! Data sheets MC6809, MC6821, MC6850Motorola Microprocessors Data Manual, 1982

! Data sheets 27128, 27256, 6264, etc. [great source]http://www.jameco.com

! Philips Logic TTL, Signetics ICs 1978

! 6809 assembly language programmingLance A. LeventhalOsborne/McGraw-Hill, ISBN 0-07-913035-4

! Eagle CAD Layout Editor software packagehttp://www.cadsoft.de

! The Real Console project http://www.pdp-11.nl/Click the Homebrew ‘PDP-11’ link in the menu at the left side.