Helix scan: A scan design for diagnosis

TSINGHUA SCIENCE AND TECHNOLOGY ISSN 1007-0214 15/49 pp83-88 Volume 12, Number S1, July 2007

Helix Scan: A Scan Design for Diagnosis*

WANG Fei (王飞)**, HU Yu (胡瑜)†, LI Xiaowei (李晓维)†

Graduate School of Chinese Academy of Sciences, Beijing 100080, China; † Key Laboratory of Computer System and Architecture, Institute of Computing

Technology, Chinese Academy of Sciences, Beijing 100080, China

Abstract: Scan design is a widely used design-for-testability technique to improve test quality and efficiency.

For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for

silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the sub-

sequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we pro-

pose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue.

Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without

losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and

achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness

of our design.

Key words: test; diagnosis; scan chain diagnosis; design for diagnosis (DFD)

Introduction

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. The memory elements in circuit such as flip-flops and latches are replaced with scan flip-flops, and then the scan flip-flops are concatenated to shift register called scan chain. For scan-designed VLSI circuit, scan chain can take up as much as 30% silicon area[1]. If simply assuming scan circuits to be fault free, we may not only result in inaccuracy testing or diagnosis results but also result in serious yield loss. Therefore, scan chain diagnosis received many attentions. The previous works on scan chain diagnosis can be classified into two categories: software-based scan chain diagnosis

and hardware-based solutions. In the first category, software-based solutions ad-

dress the diagnosis problem with sophisticated algo-rithms[1-9]. The diagnostic process generally consists of five steps. (1) Shift in and shift out test patterns uninter-ruptedly to confirm the faulty type. (2) Simulate the scan-capture-scan process on the fault-free circuit-under-diagnosis (CUD) to derive the fault-free re-sponse. (3) Inject a possible fault position into CUD. (4) Run scan-capture-scan process to get failing responses. (5) Score the possible position according to the failing response. The process will go on until get certifiable scores or time out. Although there is no area overhead of software-based solutions, the diagnosis process may be time consuming especially in the case of long scan chains.

The second category is hardware-based solutions. Schafer et al.[10] provided a method to connect the out-put of each custom D-type flip-flop (DFF) to the input of its partner DFF. Therefore, the output of faulty scan cell can be bypassed to the partner DFF and observed

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Received: 2007-02-01 Supported partly by the National Natural Science Foundation of China (No. 60633060) and the National Basic Research and Development (973) Program of China (No. 2005CB321604) To whom correspondence should be addressed. E-mail: [email protected]; Tel: 86-10-62798998

Tsinghua Science and Technology, July 2007, 12(S1): 83-88

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by the other scan chain. Schafer’s idea can pinpoint the fault scan cell; however, the routing overhead is tre-mendous large. Edirisooriya and Edirisooriya[11] pro-posed to add a two-input XOR gate between two scan cells. One input of the XOR gate was driven directly by the output of the preceding scan cell. Another input of the XOR gate was a common control signal which connected to each XOR gate so as to set/reset each scan cell. Narayanan and Das[12] proposed another set/reset method, which flipped the content of scan cells without extra signal line but adding a pulse gen-erator into each DFF. The disadvantage of this ap-proach is high area overhead. By adding a global sig-nal to each DFF, Wu[13] can diagnosis not only stuck-at (SA) fault but also hold-time faults in the scan flip-flop.

However, the above-mentioned solutions only diag-nosis the faulty scan chains, none of them can carry on diagnosis of CUD with faulty chains after scan chain diagnosis. In this work, we will propose a design-for-diagnosis (DFD) scan strategy that diagnosis of CUD in the case of faulty scan chains, meanwhile delivering high resolution and precision for diagnosing the faulty scan chain.

1 Helix Scan 1.1 Architecture of helix scan

As shown in Fig. 1, HS cells are concatenated to form an helix scan (HS) chain. The length of chain L is the number of scan cells. Each scan cell is given an index number in descending order from scan input to scan output. For example, the leftmost scan cell in Fig. 1 is indexed eight, while the rightmost scan cell is indexed zero. Same as the conventional multiplexer-type scan architecture, there is a scan-input (SI) signal and a scan enable (SE) signal connected to every scan cell. How-ever, HS has one more global signal named diagnosis enable (DE) to control the diagnosis mode.

Fig. 1 Architecture of helix scan

We use the same definition of upstream scan cell and downstream scan cell as Ref. [6]. For a given scan cell i, the cells that are indexed higher than i are up-stream to cell i. The cells that are indexed lower than i are downstream to cell i. In Fig. 1, given cell 8, cell 7, cell 6, cell 5, and cell 4 are upstream of cell 3 while cell 0, cell 1, and cell 2 are downstream of cell 3. Next, we define even chain and odd chain as follows. Even chain is the virtual chain in logic that consists of even indexed scan cells, while odd chain consists of odd in-dexed scan cells. Furthermore, for a given scan cell i, its upstream cells in even chain are denoted as even upstream (EU), and its downstream cells in even chain are denoted as even downstream (ED). Similarly, its upstream cells in odd chain are denoted as odd up-stream (OU), while the downstream cells in odd chain are denoted as odd downstream (OD). For the same example as shown in Fig. 1, given cell 3, its EU in-cludes cell 8, cell 6, and cell 4, ED includes cell 2 and cell 0, while OU and OD includes cell 7, cell 5, and cell 1, respectively. Figure 1 also illustrates the data path in the HS chain. The solid line represents the data path of even chain, while the dash line represents the data path of odd chain. Since the shape of the two data paths looks like helix lines, we name the proposed ar-chitecture as helix scan.

1.2 Structure of helix scan cell

Figure 2 shows the structure of helix scan cell. HS cell consists of two parts: the conventional multiplexer-type scan DFF and the extra DFD circuit. The DFD circuit has three PMOS transistors, one NMOS transis-tor and two invertors and a two-input NAND gate. As-sume each inverter has two transistors and an NAND gate has four transistors, we can see the area overhead of the DFD circuit is twelve transistors. In the DFD circuit, the two invertors form a latch. SE and DE to-gether control whether the latch is updated with signal SI or not. When the NAND gate outputs 1, then T3 connects Q' to G3 while T4 disconnects the DFD latch to G3, which let the content stored in the conventional scan DFF been propagated to the next HS cell and the combinational logic. When the NAND gate outputs 0, then T3 disconnects Q' while T4 connects the DFD latch to G3, which let the content stored in the DFD latch been propagated to the next HS cell and the

WANG Fei (王飞) et al：Helix Scan: A Scan Design for Diagnosis

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combinational logic.

Fig. 2 Structure of helix scan cell

HS scan cell has three operation modes: function, scan, and diagnosis. The DFD circuit always follows the value of SI in function model or in scan mode. When SE = 1 and DE = 0, the DFD latch is updated to the value of SI while when SE = 0 and DE = 1, the DFD latch is updated to the value of SI-bar. Setting SE=1 and DE=1, the HS cell entries into diagnosis mode. In this mode, the data latched in DFD circuit is-sues out into its first downstream cells. That is to say, DFD circuits can issues SI or SI-bar to its first down-stream cell. In diagnosis mode, if SI is issued out into the first downstream cell, we denote this operation as “+”. Otherwise, issue SI-bar is denoted as “−”. Note that we do not simultaneously set SE=0 and DE=0 in order to prevent fight of inverters.

2 Scan Chain Diagnosis

In this section, we introduce the diagnostic algorithm to diagnose the HS chain itself. We use the hypothesis of single-stuck-at mode (SSA), which supposes there is only one stuck-at fault in a scan chain. With the design of HS cell, the diagnosis procedure is greatly simpli-fied compared to other software-based solutions. The diagnosis procedure has three steps as follows.

Setp 1 Load 0011 flush pattern and shift out unin-terruptedly in scan mode to screen out the faulty chain. As for an SA1 fault, the response pattern is an all-one pattern. While for SA0 fault, the response pattern con-sists of all zeros. That is, after Step 1, we have known the faulty chain and faulty type.

Step 2 Load an all-zero pattern if the scan chain has an SA1 fault or load an all-one pattern if the scan chain has an SA0 fault, then set the scan chain in diag-nosis mode and conduct the “+” operation. After one clock cycle, set the scan chain in scan mode and

unload the response. A stuck-at fault on the scan path between two scan cells results in a part-zero-part-one response. However, a stuck-at fault on the scan path in a scan cell will toggle just one bit of the test pattern, and the location of the toggled bit indicates the first downstream cell of the faulty scan cell. Therefore, if the fault is on the scan path in a scan cell, then we al-ready diagnose it, and the diagnosis procedure is end. If the fault is on the scan path between two scan cells, then go to Step 3.

Step 3 Load all-zero pattern if the scan chain has an SA0 fault or load an all-one pattern if the scan chain has an SA1 fault, then set the scan chain in diagnosis mode and conduct the “−” operation. After one clock cycle, set the scan chain in scan mode and shift out the response. The “−” operation toggles all bits in the scan chain to none SA value except the first downstream cell of the faulty cell. During the unload procedure, as the fault distorts the upstream cells of the faulty cell, we will get a response pattern that consists of a se-quence of none SA value followed by a sequence of SA value. The position of SA1 is on the scan path be-tween two smallest indexed scan cells whose logic value is 1. Similarly, the position of SA0 is on the scan path between two smallest indexed scan cells whose logic value is 0.

We still use the scan chain shown in Fig.1 as an ex-ample to explain the diagnosis procedure. Assume cell 3 has an SA1 fault. First, run 0011 flush test. Second, shift in an all-zero pattern in scan mode and then set “+” operation in diagnosis mode. The pattern in faulty chain is 000001111. After “+” operation, the pattern in faulty chain turns into 000001011. As SA1, we will fi-nally get 111111011. We can easily find that the first downstream (cell 2) of the faulty cell is zero while oth-ers are all ones.

Then assume there is an SA1 fault on scan path be-tween cell 3 and cell 4. We will also get an all-one re-sponse after the first step. However, when running the all-zero pattern in Step 2, the response is 000001111. In the third step, shift in an all-one pattern in scan mode. Then setting “−” operation in diagnosis mode, the pattern in faulty chain turns into 000001000. After shift out, we get 111111000 and the fault position is between the first and the second one denoted in Italic bold face.

3 Diagnosis Algorithms with Faulty Scan Chain

When the scan chain is faulty, HS can carry on


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diagnosing the circuit-under-test while previously pro-posed approaches abort the diagnosis procedure. As there is a fault in the scan chain, diagnostic patterns generated by automatic test pattern generation (ATPG) tool need to be converted before being applied to CUT. This section introduces the diagnosis algorithm of HS to transform test patterns.

3.1 Diagnostic pattern generation

As described in Section 1.1, the faulty chain consists of two virtual scan chains: even chain and odd chain. The faulty virtual chain that consists of all even or odd cells can be partitioned into EU/OU and ED/OD of faulty cell. Therefore, given a faulty cell i, its EU/OU and the faulty free virtual chain load in test patterns through the SI port, while ED/OD cells load in test patterns through the output port of cell i. As the logic value of cell i is permanently equal to the stuck-at fault value, we obtain the test patterns for ED/OD cells by setting the faulty scan chain in diagnosis mode with “+” op-erations and “−” operations. Hence by operating “+” and “−” in the procedure of shift-in test patterns, we load the original ATPG test patterns in the faulty scan chain. In other words, the test patterns of ED/OD con-sist of “+” or “−” instead of “0” or “1”. Let D (d0, d1, d2,…,dn) denote the original patterns of ED/OD, D′ ( 0 ,d ′ 1,d ′ 2 ,d ′ …, nd ′ ) denote new patterns obtained by “−” or “+” operation. n is the number of the patterns. In D′ , let “1” represents “−” operation, while “0” represents “+” operation. Then, Eq. (1) describes the relationship between D′ and D. SA is the stuck-at value of faulty chain.

1

( ) SA, 0i

i j ij n

d d d i n+

=

′ ′= + ⊕ <∑ ≤ (1)

As DE and SE are global signal lines, the shift-in process should finish at the same time. Each part may have its own start time to shift in diagnostic patterns. Faulty free chain starts at first and its start point can be

considered as zero while others may be several cycles later. We calculate the start point in different circum-stances in Table 1. EU/OU and ED/OD choose the start point according to the scan chain length and fault posi-tion to guarantee finish the shift in process at the same time. Note under the condition of multiple scan chains, the start time of the longest scan chain can be consid-ered as zero. Let P (p0, p1, p2,…,pm)) denote the origi-nal pattern of EU/OU or faulty free chain, while P′

( 0 ,p′ 1,p′ 2 ,p′ …, np′ ) denotes the HS pattern of EU/OU

or faulty free chain. m is the number of the patterns. Given D and P, the start time of P, tP, and the start time of D, tD can be used to calculate the transition of P to P′ according to Table 1. Equation (2) formulates the transition.

P D

P D

, 0 , 0, 0m t t

i j i jj i t t

p b p j b i m+ −

= + −

′ = + ∀ < = <∑ ≤ (2)

Let us explain Eqs. (1) and (2) by an example. As-sume a scan chain has 16 scan cells, and cell 6 has an SA fault. Therefore, fault free chain is odd chain con-sisting of all the even cells. EU consists of cells 8, 10, 12, and 14. ED consists of cells 0, 2, and 4. According to the Table 1, EU starts 4 cycles latter than even chain and ED starts 5 cycles latter than even chain. Without loss of generality, we suppose the pattern to shift in is 1100100101110011. Therefore, the pattern shifted in odd chain is 1010010101. The pattern shifted in EU is 1001 and the pattern shifted in ED is 101. As shown in Fig. 3, the leftmost has the biggest index number while the rightmost has the smallest index number, as shown in Fig. 4. According to Eq. (1), the calculation result of each bits are marked under the bit. After ED pattern generated, we revise the patterns of odd chain and EU as shown in Fig. 4. All bits in odd chain and EU pat-tern should be inverted before the vertical line as these bits have the earlier start time than the “−” operation.

Table 1 Start point calculation

The parity of scan chain L length

The parity of fault position F

The max. of scan chain length

Start point of OU/EU of faulty cell

Start point of OD/ED of faulty cell

Even Even L/2 F/2+1 L/2−F/2 Even Odd L/2 /2F⎡ ⎤⎢ ⎥ /2 /2L F− ⎢ ⎥⎣ ⎦

Odd Even /2L⎢ ⎥⎣ ⎦ /2F / 2 / 2L F−⎢ ⎥⎣ ⎦

Odd Odd / 2L⎡ ⎤⎢ ⎥ / 2 1F +⎡ ⎤⎢ ⎥ /2 /2L F−⎡ ⎤ ⎢ ⎥⎢ ⎥ ⎣ ⎦

WANG Fei (王飞) et al：Helix Scan: A Scan Design for Diagnosis

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Fig. 3 Example of pattern generation for OD

Fig. 4 Example of patterns generation for odd chain and EU

3.2 Shift out the diagnostic pattern

As for the shift-out process, it needs three steps to achieve. First, shift out even/odd chain that is fault free in diagnosis mode with “+” operation. Since the length of even/odd chain is about one-half of whole chain, half of cycles in scan mode are needed to shift the data out in diagnosis mode. As the content of upstream cells is distorted during shifting out, we need run shift-in and capture process again to rebuild the data in second step. This step needs about another half of shift-in cy-cles in scan mode. Third, shift one more cycle in scan mode to shift the data in faulty virtual chain to fault free virtual chain. Then shift out like described in first step. As a result, the whole number of cycles consumed in shift-out process is about 1.5 times of the length of the scan chain.

4 Experimental Results

We use Hspice to evaluate the perform impaction of HS cell in function mode and scan mode in 0.13-µm technology shown in Fig. 5. The solid line presents the system clock. The dot-dash line is the response of traditional DFF when the positive clock edge coming. The dash line shows the response of HS cell. Figure 5a illustrates the falling transition from 1 to 0. While Fig. 5b shows the rising

Fig. 5 Comparison of response speed

transition from 0 to 1. In this case, the falling time of HS cell is about 50 ps latter than traditional DFF. How-ever, the timing is determined by the transition from 0 to 1; therefore, we lay emphasis on optimizing the rais-ing time and relax the constriction of falling time pur-posely. As shown in Fig. 5b, the rising time of HS cell is about 10 ps later than traditional DFF. As a whole, the timing penalty of HS cell is about 10 ps.

Table 2 compares area overheads of the proposed approach with other hardware-based diagnosis tech-niques. Since the layout rules are not available, we use the total transistor active area as the metric of the area overhead. Scharfer’s method[10] has the lowest area overhead but the routing overhead is two times the original scan chain. While Nayayanan’s method[12] has no route overhead but the area overhead is tremendous. With comparable area overhead to that of Wu’s[13], our design can carry on the diagnosis process when there is a fault in a scan cell.

4 Conclusions

This paper proposed a design-for-diagnosis scan struc-ture. This design can carry on the sequent diagnostic process after scan chain diagnosis when the scan chain is faulty. Moreover, it can precisely diagnose the fault. As the DFD circuit of the proposed scan cell is com-pletely transparent to in function mode and scan mode,


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our design is entirely compatible with conventional scan-based design. Experiments show the performance

impact is 10 ps in 0.13-µm technology and the average area overhead is 10%.

Table 2 Comparison area overhead with other hardware-based diagnosis techniques

% increase with ISCAS89 benchmarks

DFF ratio Schafer[10] Edirsooriya[11] Narayanan[12] Wu[13] Helix scan

s386 16.5 6.3 7.6 14.0 7.0 7.6 s510 14.7 5.6 6.8 12.4 6.2 6.8 s832 8.6 3.3 4.0 7.3 3.6 4.0 s1196 17.1 6.6 7.9 14.5 7.2 7.9 s9234 23.3 9.0 10.8 19.7 9.9 10.8 s15850 30.9 11.9 14.2 26.1 13.1 14.2 s38417 37.6 14.5 17.4 31.8 16.0 17.4 s38584 32.3 12.4 14.9 27.3 13.7 14.9

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Helix scan: A scan design for diagnosis