HEF4047B Monostable/astable multivibrator · 1. General description The HEF4047B consists of a gatable astable multivibrator incorporating logic techniques to permit positive or negative

1. General description

The HEF4047B consists of a gatable astable multivibrator incorporating logic techniques to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options.

Inputs include +TRIGGER, TRIGGER, ASTABLE, ASTABLE, RETRIGGER and MR (master reset). Buffered outputs are O, O and OSCILLATOR OUTPUT. In all modes of operation an external capacitor (Ct) must be connected between CTC and RCTC, and an external resistor (Rt) must be connected between RTC and RCTC.

A HIGH level on the ASTABLE input enables astable operation. The period of the square wave at O and O outputs is a function of the external components employed. ‘True’ input pulses on the ASTABLE or ‘complement’ pulses on the ASTABLE input, allow the circuit to be used as a gatable multivibrator. The OSCILLATOR OUTPUT period is half of the O output in the astable mode. However, a 50% duty factor is not guaranteed at this output.

In the monostable mode, positive edge-triggering is accomplished by applying a leading-edge pulse to the +TRIGGER input and a LOW level to the TRIGGER input. For negative edge-triggering, a trailing-edge pulse is applied to the TRIGGER and a HIGH level to the +TRIGGER. Input pulses may be of any duration relative to the output pulse. The multivibrator can be retriggered (on the leading-edge only) by applying a common pulse to both the RETRIGGER and +TRIGGER inputs. In this mode, the output pulse remains HIGH as long as the input pulse period is shorter than the period determined by the RC components.

An external count down option implements coupling O to an external ‘N’ counter and resetting the counter with the trigger pulse. The counter output pulse is fed back to the ASTABLE input and has a duration equal to N times the period of the multivibrator. A HIGH level on the MR input assures no output pulse during an ON-power condition. This input can also be activated to terminate the output pulse at any time. In the monostable mode, a HIGH level or power-ON reset pulse must be applied to MR, whenever VDD is applied.

2. Features and benefits

2.1 General

Monostable (one-shot) or astable (free-running) operation

True and complemented buffered outputs

Only one external resistor and capacitor required

HEF4047BMonostable/astable multivibratorRev. 4 — 15 September 2014 Product data sheet

NXP Semiconductors HEF4047BMonostable/astable multivibrator

2.2 Monostable multivibrator

Positive- or negative-edge triggering

Output pulse width independent of trigger pulse duration

Retriggerable option for pulse-width expansion

Long pulse width possible using small RC components

with external counter provision

Fast recovery time independent of pulse width

Pulse-width accuracy maintained at duty cycles

approaching 100%

2.3 Astable multivibrator

Free-running or gatable operating modes

50% duty cycle

Oscillator output available

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Name Description Version

HEF4047BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4047BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig 1. Functional diagram

HEF4047B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet Rev. 4 — 15 September 2014 2 of 21


5. Pinning information

5.1 Pinning

(1) Special input protection that allows operating input voltages outside the supply voltage lines. Compared to the standard input

protection pin 3 (RCTC) is more sensitive to static discharge; extra handling precautions are recommended.

Fig 2. Logic diagram

Fig 3. Pin configuration




5.2 Pin description

6. Limiting values

[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

Table 2. Pin description

Symbol Pin Description

CTC 1 external capacitor connection

RTC 2 external resistor connection

RCTC 3 external capacitor/resistor connection

ASTABLE 4 input

ASTABLE 5 input

TRIGGER 6 input

VSS 7 ground supply voltage

+TRIGGER 8 input

MR 9 master reset input

O 10 output

O 11 output

RETRIGGER 12 input

OSCILLATOR OUTPUT 13 oscillator output

VDD 14 supply voltage

Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 18 V

IIK input clamping current VI < 0.5 V or VI > VDD + 0.5 V - 10 mA

VI input voltage 0.5 VDD + 0.5 V

IOK output clamping current VO < 0.5 V or VO > VDD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +85 C

Ptot total power dissipation Tamb = 40 C to +85 C

DIP14 package [1] - 750 mW

SO14 package [2] - 500 mW

P power dissipation per output - 100 mW




7. Recommended operating conditions

8. Static characteristics

Table 4. Operating conditions

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 3 15 V

VI input voltage 0 VDD V

Tamb ambient temperature in free air 40 +85 C

t/V input transition rise and fall rate

VDD = 5 V - 3.75 s/V

VDD = 10 V - 0.5 s/V

VDD = 15 V - 0.08 s/V

Table 5. Static characteristicsVSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit

Min Max Min Max Min Max

VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA

VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA

VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA

VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

II input leakage current 15 V - 0.3 - 0.3 - 1.0 A

output transistor OFF; pin 3 at VDD or VSS

15 V - 0.3 - 0.3 - 1.0 A

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A

10 V - 40 - 40 - 300 A

15 V - 80 - 80 - 600 A

CI input capacitance - - - - 7.5 - - pF




9. Dynamic characteristics

Table 6. Dynamic characteristicsVSS = 0 V; Tamb = 25 C; for test circuit and waveform, see Figure 4 and Figure 5; unless otherwise specified.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

tPHL HIGH to LOW propagation delay

ASTABLE, ASTABLE to OSCILLATOR OUTPUT

5 V [1] 68 ns + (0.55 ns/pF)CL - 95 190 ns

10 V [1] 43 ns + (0.23 ns/pF)CL - 45 90 ns

15 V [1] 22 ns + (0.16 ns/pF)CL - 30 60 ns

tPLH LOW to HIGH propagation delay

ASTABLE, ASTABLE to OSCILLATOR OUTPUT

5 V [1] 58 ns + (0.55 ns/pF)CL - 85 170 ns

10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns

15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns


ASTABLE, ASTABLE to O, O

5 V [1] 123 ns + (0.55 ns/pF)CL - 150 300 ns

10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns

15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns


ASTABLE, ASTABLE to O, O

5 V [1] 103 ns + (0.55 ns/pF)CL - 130 260 ns

10 V 49 ns + (0.23 ns/pF)CL - 60 120 ns

15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns


+/TRIGGER to O, O 5 V [1] 133 ns + (0.55 ns/pF)CL - 160 320 ns

10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns

15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns


+/TRIGGER to O, O 5 V [1] 128 ns + (0.55 ns/pF)CL - 155 310 ns

10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns

15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns


+TRIGGER, RETRIGGER to O

5 V [1] 38 ns + (0.55 ns/pF)CL - 65 130 ns

10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns

15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns


+TRIGGER, RETRIGGER to O

5 V [1] 68 ns + (0.55 ns/pF)CL - 95 190 ns

10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns

15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns


MR to O 5 V [1] 83 ns + (0.55 ns/pF)CL - 100 200 ns

10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns

15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns


MR to O 5 V [1] 83 ns + (0.55 ns/pF)CL - 100 200 ns

10 V 34 ns + (0.23 ns/pF)CL - 45 90 ns

15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns

tTHL HIGH to LOW output transition time

5 V [1] 10 ns + (1.0 ns/pF)CL - 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns

15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns

tTLH LOW to HIGH output transition time

5 V [1] 10 ns + (1.0 ns/pF)CL - 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns

15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns




[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

10. Waveforms

tW pulse width any input except MR 5 V - 220 110 - ns

10 V - 100 50 - ns

15 V - 70 35 - ns

MR HIGH 5 V - 60 30 - ns

10 V - 30 15 - ns

15 V - 20 10 - ns

Table 6. Dynamic characteristics …continuedVSS = 0 V; Tamb = 25 C; for test circuit and waveform, see Figure 4 and Figure 5; unless otherwise specified.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

Measurement points are given in Table 7.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. input to output propagation delays, output transition time and pulse width

Table 7. Measurement points

Supply voltage Input Output

VDD VM VM

5 V to 15 V 0.5VDD 0.5VDD




11. Application information

a. Input waveform

b. Test circuit

Test and measurement data is given in Table 8.

Definitions test circuit:

DUT = Device Under Test.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 5. Test circuit for measuring switching times

Table 8. Test data

Supply voltage Input Load VEXT

VI tr, tf CL RL tPLH, tPHL

5 V to 15 V VDD 20 ns 50 pF 1 k open

Table 9. Functional connections [1]

Function Pins connected to Output pulse from pins

Output period or pulse widthVDD VSS input pulse

Astable multivibrator

Free running 4, 5, 6, 14 7, 8, 9, 12 - 10, 11, 13 at pins 10, 11; tA = 4.40 RtCt at pin 13:tA = 2.20 RtCt

True gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13

Complement gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13




[1] In all cases, external resistor between pins 2 and 3, external capacitor between pins 1 and 3.

[2] Input pulse to RESET of external counting chip: external counting chip output to pin 4.

11.1 Astable mode design information

11.1.1 Unit-to-unit transfer voltage variations

The following analysis presents worst case variations from unit-to-unit as a function of transfer voltage (VTR) shift for free running (astable) operation.

(1)

(2)

(3)

, where tA = astable mode pulse width; see Table 10.

[1] Therefore if tA = 4.40 RtCt is used, the maximum variation is (+7.0%; 0.0%) at 10 V.

Monostable multivibrator

Positive edge-triggering 4, 14 5, 6, 7, 9, 12 8 10, 11 at pins 10, 11; tM = 2.48 RtCt Negative edge-triggering 4, 8, 14 5, 7, 9, 12 6 10, 11

Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11

External countdown[2] 14 5, 6, 7, 8, 9, 12

- 10, 11

Table 9. Functional connections …continued[1]

Function Pins connected to Output pulse from pins

Output period or pulse widthVDD VSS input pulse

Fig 6. Astable mode waveforms

Table 10. Values for astable mode pulse width (tA)

VTR tA

Min Typ Max Min Typ[1] Max

VDD = 5 V or 10 V 0.3 VDD 0.5 VDD 0.7 VDD 4.71 RtCt 4.40 RtCt 4.71 RtCt

VDD = 15 V 4 V 0.5 VDD 11 V 4.84 RtCt 4.40 RtCt 4.84 RtCt

t1 RtCt InVTR

VDD VTR+---------------------------–=

t2 RtCt InVDD VTR–

2VDD VTR–-----------------------------–=

tA 2 t1 t2+ 2RtCt InVTR VDD VTR–

VDD VTR+ 2VDD VTR– ------------------------------------------------------------------–= =




11.1.2 Variations due to changes in VDD

In addition to variations from unit-to-unit, the astable period may vary as a function of frequency with respect to VDD. Typical variations are presented graphically in Figure 7 and Figure 8 with 10 V as a reference.

(1) Tamb = 25 C; fo = 10 kHz; Ct = 100 pF; Rt = 220 k.



Fig 7. Typical O and O period accuracy as a function of supply voltage; astable mode.





Fig 8. Typical O and O period accuracy as a function of supply voltage; astable mode.




11.2 Monostable mode design information

The following analysis presents worst case variations from unit-to-unit as a function of transfer voltage (VTR) shift for one-shot (monostable) operation.

(4)

(5)

(6)

, where tM = monostable mode pulse width; see table Table 11.

[1] In the astable mode, the first positive half cycle has a duration of tM: succeeding durations are 1⁄2 tA. Therefore if tM = 2.48 RtCt is used, the maximum variation is (+12%; 0.0%) at 10 V.

Fig 9. Monostable waveforms.

Table 11. Values for monostable mode pulse width (tM)

VTR tM

Min Typ Max Min Typ[1] Max

VDD = 5 V or 10 V 0.3 VDD 0.5 VDD 0.7 VDD 2.78 RtCt 2.48 RtCt 2.52 RtCt

VDD = 15 V 4 V 0.5 VDD 11 V 2.88 RtCt 2.48 RtCt 2.56 RtCt

t1' R– tCt InVTR

2VDD

--------------=

tM t1' t2+ =

tM RtCt InVTR VDD VTR–

2VDD VTR– 2VDD -----------------------------------------------------–=




11.2.1 Retrigger mode operation

The HEF4047B can be used in the retrigger mode to extend the output pulse duration. It can also be used to compare the frequency of an input signal with the frequency of the internal oscillator. In the retrigger mode, the input pulse is applied to pins 8 and 12, and the output is taken from pin 10 or 11. Normal monostable action is obtained when one retrigger pulse is applied (see Figure 10). Extended pulse duration is obtained when more

than one pulse is applied. For two input pulses, . For more than two

pulses, tRE (output O), terminates at some variable time, tD, after the termination of the last retrigger pulse. tD is variable because tRE (output O) terminates after the second positive edge of the oscillator output appears at flip-flop 4.

11.2.2 External counter option

The use of external counting circuitry extends time tM by any amount. Advantages include digitally controlled pulse duration, small timing capacitors for long time periods, and extremely fast recovery time. A typical implementation is shown in Figure 11.

The pulse duration at the output is:

(7)

Where text = pulse duration of the circuitry, and N is the number of counts used.

Fig 10. Retrigger mode waveforms.

tRE t1' t1 2t2+ +=

text N 1– tA tM 1/2 tA+ +=




11.2.3 Timing component limitations

The capacitor used in the circuit should be non-polarized and have low leakage (that is the parallel resistance of the capacitor should be an order of magnitude greater than the external resistor used). There is no upper or lower limit for either Rt or Ct value to maintain oscillation. However, for accuracy, Ct must be much larger than the inherent stray capacitance in the system (unless this capacitance can be measured and taken into account). Rt must be much larger than the LOCMOS ‘ON’ resistance in series with it, which typically is hundreds of ohms.

The recommended values for Rt and Ct to comply with previously calculated formulae without trimming should be:

– Ct 100 pF, up to any practical value

– 10 k Rt 1 M

11.2.4 Power consumption

In the standby mode (monostable or astable), power dissipation is a function of leakage current in the circuit. For dynamic operation, the power required to charge the external timing capacitor Ct is shown in the following formulae:

Astable mode:

(8)

(9)

Monostable mode:

(10)

Because the power dissipation does not depend on Rt, a design for minimum power dissipation would be a small value of Ct. The value of R would depend on the desired period (within the limitations discussed previously). Typical power consumption in astable mode is shown in Figure 12, Figure 13 and Figure 14.

Fig 11. Implementation of external counter option.

P 2 Ct V2 f= f at output pin 13

P 4 Ct V2 f= f at output pins 10 and 11

P2.9 Ct V

2 duty cycle T

----------------------------------------------------------= f at output pins 10 and 11




VDD = 5 V.

(1) Ct = 100 nF.

(2) Ct = 10 nF.

(3) Ct = 1 nF.

(4) Ct = 100 pF.

(5) Ct = 10 pF.

Fig 12. Power consumption as a function of the output frequency at O or O; astable mode.

VDD = 10 V.

(1) Ct = 100 nF.

(2) Ct = 10 nF.

(3) Ct = 1 nF.

(4) Ct = 100 pF.

(5) Ct = 10 pF.





VDD = 15 V.

(1) Ct = 100 nF.

(2) Ct = 10 nF.

(3) Ct = 1 nF.

(4) Ct = 100 pF.

(5) Ct = 10 pF.





12. Package outline

Fig 15. Package outline SOT27-1 (DIP14)




Fig 16. Package outline SOT108-1 (SO14)




13. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4047B v.4 20140915 Product data sheet - HEF4047B_CVN_3

Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

HEF4047B_CVN_3 19950101 Product specification - -




14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.



http://www.nxp.com

http://www.nxp.com/profile/terms


Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

14.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]




16. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 12.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Monostable multivibrator. . . . . . . . . . . . . . . . . . 22.3 Astable multivibrator . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 35.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Recommended operating conditions. . . . . . . . 5

8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

11 Application information. . . . . . . . . . . . . . . . . . . 811.1 Astable mode design information . . . . . . . . . . . 911.1.1 Unit-to-unit transfer voltage variations . . . . . . . 911.1.2 Variations due to changes in VDD . . . . . . . . . . 1011.2 Monostable mode design information. . . . . . . 1111.2.1 Retrigger mode operation. . . . . . . . . . . . . . . . 1211.2.2 External counter option. . . . . . . . . . . . . . . . . . 1211.2.3 Timing component limitations . . . . . . . . . . . . . 1311.2.4 Power consumption . . . . . . . . . . . . . . . . . . . . 13

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 1914.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1914.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1914.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

15 Contact information. . . . . . . . . . . . . . . . . . . . . 20

16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

© NXP Semiconductors N.V. 2014. All rights reserved.

For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 15 September 2014

Document identifier: HEF4047B

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

Documents

HEF4047B Monostable/astable multivibrator · 1. General description The HEF4047B consists of a gatable astable multivibrator incorporating logic techniques to permit positive or negative