He Thong Nhung 2014

5/21/2018 He Thong Nhung 2014

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TM TT L THUYT


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HTHNG NHNG

(Embedded System


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Embedded System

An embedded system is a comsystem designed to perform one or a dedicated functions often with real-timcomputing constraints. It is embedded

a complete device often including harmechanical parts. By contrast, a genepurpose computer, such as a persona(PC), is designed to be flexible and towide range of end-user needs. Embedsystems control many devices in comtoday.


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Embedded System

Embedded systems are controlleor more main processing cores thtypically either microcontrollers o

signal processors (DSP).The keycharacteristic, however, is being to handle a particular task, whichrequire very powerful processors


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Embedded System

Since the embedded system is dto specific tasks, design engineeroptimize it to reduce the size andthe product and increase the reliaperformance.

In general, "embedded system" isstrictly definable term, as most syhave some element of extensibiliprogrammability.


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Embedded System

Peter Marwedel, Embedded System DesignSystems Foundations of Cyber-Physical SysEmbedded systems are information procesembedded into enclosing products.

Examples include embedded systems in carplanes, and telecommunication or fabricatioSuch systems come with a large number of characteristics, including real-time constraindependabilityas well as efficiencyrequireEmbedded software is software integrated processes. The technical problem is managconcurrency in computational systems.


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Embedded System

Application areas:Automotive electronics: These include

control systems, engine control systems,systems (ABS), electronic stability progra

and other safety features, air-conditioningsystems, anti-theft protection, and many

Avionics: A significant amount of the totairplanes is due to the information procesequipment, including flight control system

collision systems, pilot information systemothers.


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Embedded System Telecommunication: Mobile phones have

the fastest growing markets in the recent yemobile phones, radio frequency (RF) designsignal processing and low power design are

Health sector: There is a huge potential forthe medical service by taking advantage of iprocessing within medical equipment. Therdiverse techniques that can be applied in thi

Security: The interest in various kinds of seincreasing. Embedded systems can be usedsecurity in many ways. This includes secureidentification or authentication of people, for

with finger print sensors or face recognition Consumer electronics: Video and audio e

a very important sector of the electronics ind


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Embedded System

Fabrication equipment: Fabrication equipmtraditional area in which embedded systemsemployed for decades. Safety is very importsystems, the energy consumption is less im

Smart buildings: Information processing caincrease the comfort level in buildings, can renergy consumption within buildings, and casafety and security.

Robotics: Robotics is also a traditional areembedded physical systems have been use

kinds of robots, modeled after animals or huhave been designed.


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Embedded SystemCommon characteristics

1/ Reliability: Reliability is the probability that a system w2/ Maintainability: Maintainability is the probability that

can be repaired within a certain time-frame.3/ Availability: Availability is the probability that the syste

Both the reliability and the maintainability must be highachieve a high availability.

4/ Safety: This term describes the property that a systemany harm.5/ Security: This term describes the property that confid

remains confidential and that authentic communication

Embedded systems must be efficient. Energy

Run-time Efficiency Code size Weight Cost


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Embedded System

Avalon Switch Fabri


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Concepts A Field Programmable Gate Array (FPGA) is an in

designed to be configured by the customer or designmanufacturing.

SOC (System on a Chip)

SOPC (System on a Programmable Chip)

SOPC Builder (System on a Programmable Chip Busoftware made by Altera that automates connecting components to create a complete computer system tof its various FPGA chips.

PSoC (Programmable System on Chip) is a family ocircuits made by Cypress Semiconductor. These chipCPU and mixed-signal arrays of configurable integra

digital peripherals.


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NIOS II

Nios II is a 32-bit embedded-procearchitecture designed specifically foAltera family of FPGAs. Nios II inco

many enhancements over the originarchitecture, making it more suitablwider range of embedded computinapplications, from DSP to system-c


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IP core

An IP (intellectual property) core is a blocor data that is used in making a field proggate array ( FPGA) or application-specificircuit ( ASIC ) for a product. As essentiaof design reuse , IP cores are part of the

electronic design automation ( EDA) indutowards repeated use of previously desigcomponents. Ideally, an IP core should b

portable - that is, able to easily be insertevendor technology or design methodolog


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IP core

IP cores fall into one of three categories:, firm cores, or soft cores. Hard cores amanifestations of the IP design. These aplug-and-play applications, and are less

and flexible than the other two types of cthe hard cores, firm (sometimes called scores also carry placement data but are to various applications. The most flexiblethree, soft cores exist either as a netlist(

logic gate s and associated interconnectup an integrated circuit ) or hardware delanguage ( HDL) code.


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Logic Elements (LEs)

The main building block of the progdevices we use in the TM-2a is a LoElement (or LE). The only parts of t

we use are the LUT, Cascade chainprogrammable register (or FF).Note that it is not necessary to us

these elements. The FFs and LUTsused independently. However, if on

use both a LUT and a FF in the samhave to be connected in the order s


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The FPGA LUT (Look-Up Table) is ROM with several address inputs adata output. A common size is 16x1

four inputs and one output. By settiproper bits in that ROM, it becomesdesired boolean logic function havinfour inputs and one output. That's w

sometimes called a function genera


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Cascade Chain

The cascadechain can usea logical ANDor logical OR(via

DeMorgansinversion) toconnect the

outputs ofadjacent LEs.


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Avalon Switch Fabric

Avalon switch fabric ?

Nios II uses the Avalon switch fabric ainterface to its embedded peripherals.

to a traditional bus in a processor-baswhich lets only one bus master accessa time, the Avalon switch fabric, using side arbitration scheme, lets multiple moperate simultaneously.


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Six different interface type

Avalon Memory Mapped Interface (Avalon-MM) - an read/write interface typical of masterslave connections

Avalon Streaming Interface (Avalon-ST) - an interfacthe unidirectional flow of data, including multiplexed streand DSP data.

Avalon Memory Mapped Tristate Interface - an addre

read/write interface to support off-chip peripherals. Multcan share data and address buses to reduce the pin coand the number of traces on the PCB.

Avalon Clock - an interface that drives or receives clocsignals to synchronize interfaces and provide reset con

Avalon Interrupt - an interface that allows componentsto other components.

Avalon Conduit - an interface that allows signals to bethe top level of an SOPC Builder system where they cato other modules of the design or FPGA pins.


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Wishbone

WishboneThe Wishbone specification is now controlOpenCores.org. The Wishbone IP core budeveloped to interconnect IP cores within

and does not support external buses. The developer site had provided VHDL code, bhas been off-line for months. The specificaalways available by the link provided abovWishbone standard allows IP core interconthe VHDL code may have to be developedThe Full title: WISHBONE System-on-ChipInterconnection Architecture for Portable I


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HNG DN THC TP


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Thc tp Hthng nhngBi tp th nghim s1:

Gii thiu board ALTERA DE2

Development and Education.I. Board ALTERA DE2 Development and Education.

Hnh 1.1

Sau y l phn cng trn Board DE2 : Altera Cyclone II EP2C35F672C6. Thit bcu hnh ni tip Altera EPCS16. USB Blaster cho lp trnh v iu khin ngi dng API, JTAG V ACTIVE ni

tip c htrlp trnh trn DE2. 512 Kbyte SRAM. 8 Mbyte SDRAM. 4 Mbyte bnhFLASH. cm thSD. 4 Cng tc nhn.

18 cng tc bt tt.


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Thc tp Hthng nhng 18 LEDS . 9 LEDS xanh l cy. Bdao ng 50MHz v 27 MHz cho ng h. 24 bit CD-quality gii m m thanh vi line-in, line-out, microphone trong gic

cm. VGA DAC 10bit DAC tc cao vi kt ni cng VGA out. TV decoder (NTSC/PAL) v kt ni cng TV-in. 10/100 kt ni ETHERNET. USB host/slave iu khin USB vi loi kt ni A v B. RS-232 thu , pht vi 9-pin kt ni. PS/2 kt ni chut / bn phm. IrDA thu pht. 40 Pin mrng vi diode bo v.

II.

Kim tra Board DE2.B1: Kt ni ngun in 9V v cp USB vi cng USB blaster. Bt cng tc ngun ON.

Kim tra Driver USB trn my: Click chut phi vo My ComputerManageDevice ManagerUniversal Serial Bus Controllersnu thy Altera USB-Blasterth my nhn Driver.

Hnh 1.2


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Thc tp Hthng nhng Nu my cha nhn Driver USB-Blaster sc cnh bo chm than nh

sau:

Hnh 1.3

Click chut pahir vo USB-BlasterUpdate DriverInstall from a listor Specific location (Advance)nextcheck vo Include this locationin the searchBrowern C:\altera\10.1\quartus\drivers\usb-

blaster next finish.

Hnh 1.4


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Thc tp Hthng nhng

Hnh 1.5

B2: Thit lp chuyn i RUN / PROG (Cng tc nm bn tri LCD) chRUN.B3:Khi ng phn mm QUARTUS IIB4:Trong ca sphn mm QUARTUS II chn ToolsProgrammerc 2 phn chnl Harware Setupschn USB-Blasterv Modeschn JTAG.

Hnh 1.6


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Thc tp Hthng nhng

B5: Click chut tri chn Harware SetupChn USB-Blastertrong khung Curentlyselected harware close

Hnh 1.7B6: Sau khi kt ni Driver USB-Blaster xong, tip tc chn Add File...C:\DE2_Control_ panel DE2_USB_API.sofSauk hi load file DE2_USB_API.sof Start np chng trnh xung Board DE2.


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Thc tp Hthng nhngHnh 1.8

B7: Mchng trnh DE2_control_panel.exe OpenOpen USB Port 0v btu Test t!ng module phn cng trn Board.

PS2 & 7-SEG.

LED & LCD. FLASH.

SDRAM. SRAM.

VGA.

Hnh 1.9


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Hng Dn SDng Phn Mm Modelsim

B.1

Bi tp th nghim s1:

HNG DN SDNG QUARTUS II 10.1

Altera Quartus II 10.1 l phn mm thit k mch logic kh trnh ca Altera chophp phn tch v tng hp thit kngn ngm tphn cng, cho php bin dch thitk, thc hin phn tch thi gian, kim tra sRTL, m phng thit kv np chngtrnh ln board FPGA.

Trong hng dn ny shng dn: cch to project mi, xy dng hthng, gnchn cho hthng bng Verilog HDL hoc bng skhi v np chng trnh thit k

xung board.

Khi double click vo biu tng Quartus II 10.1 ta sthy ca snhHnh A.1, tiptheo chn Create a New Project hoc trn thanh cng cvo File/New Project Wizard

Hnh A.1

Ktip chn Next qua phn hng dn n phn chn ni lu, t tn project v tnthmc (Hnh A.2), phn t tn sc t theo ng quy tc, tn project v tn thmc phi c t trng nhau. V d: h thng c lu vo a D, tn th mc lBai_Huong_Dan v tn project c!ng l Bai_Huong_Dan (Hnh A.3). Chn Next v Next.

Ty thu"c vo board ang sdng thit khthng nhng chn thit bcho phhp, do hng dn trn board DE2 sdng Cyclone II EP2C35F672C6 (c 33216 logicelements, b"nh483840 bit v tng schn I/O l 475) c trnh by #Hnh A.4. Tip


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B.2

theo chn Next hai ln sxut hin bng tm tt nhthhin #Hnh A.5 v kt thc phnto project chn Finish.

Hnh A.2

Hnh A.3

Bc u chn ni lu trh thng thit kcoi nh hon tt, tip theo l phnxy dng hthng nhng bng chng trnh SOPC Builder. Trn thanh cng cQuartuschn Tools/SOPC Builder hoc chn biu tng skhi v sau xut hin h"p thoinhHnh A.6 t tn cho hthng, tn hthng c tht tn theo mun (theo quytc t tn hp l) v chn ngn ngm tVerilog HDL hoc VHDL xy dng hthng, v dt tn: nios_sys v ngn ngVerilog HDL.


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B.3

Hnh A.4

Hnh A.5

Hnh A.6


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B.4

$u tin ca phn xy dng h thng, thit kphn CPU nhHnh A.7, A.8, lachn core Nios II cho ph hp vi phn thit kv sau y l phn trnh by nhng chc

n%ng ca m&i loi core:-

Nios II/f c dng trong cc phn thit kcn hiu sut cao v m"t schc n%ngsau:

' Ty chn MMU (Memory Management Unit) v MPU (MicroProcessor Unit).' Truy c(p ln n 2 GB khng gian a ch)bn ngoi.' Tchn lin kt b"nhcho Instructions and Data.' Ty chn chia phn cng.' Rnhnh "ng.' Nhiu lp phn cng.' Caches Instruction v Data ring bit.'

Module sa l&i JTAG.- Nios II/s c dng duy tr cn bng gia hiu sut v chi ph, c m"t s chc

n%ng sau:' Caches Instruction.

' Rnhnh tnh.' Nhiu lp, phn chia v thay i phn cng.' Module sa l&i JTAG.

- Nios II/e c dng trong cc ng dng nh.

Hnh A.7


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B.5

Hnh A.8Chn Next n phn chn cp "debug, do chn Nios II/e nn ch)c thchn #cp

"1 (Hnh A.9). Kt thc phn cu hnh core Nios II chn Finish.

Hnh A.9


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B.6

Tip theo, l phn xy dng b"nhcho hthng cha lnh v dliu. Phn mmSOPC Builder h&trgm cc b"nh: SDRAM, SRAM, RAM, ROM, Flash. Hng dn

chn b"nhRAM c dung lng 32768 byte c thhin #Hnh A.10, A.11.

Hnh A.10


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B.7

Hnh A.11

Sau khi tao b"nhRAM double-click CPU gn b"nhcho n nhHnh A.12.

Hnh A.12

System IDl module cung cp m"t stc dng nh(n dng hthng phn cng trnboard DE2. Trong Nios II, System ID c sdng xc nh chng trnh thc thic bin dch tng thch vi phn cng cu hnh b#i SOPC Builder, khi ID cha cthit ktrong hthng SOPC Builder, chng trnh c thkhng thc thi (Hnh A.13 vA.14).


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B.8

Hnh A.13

Hnh A.14

JTAG UART: c chc n%ng kt ni d liu t*my chPC vi board DE2 thngqua cng USB Blaster, phng php truyn chu&i k tni tip v cu hnh JTAG UARTchn #ch"mc nh (Hnh A.15 v A.16).


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B.9

Hnh A.15

Hnh A.16

Xy dng timer cho ng dng c trnh by #Hnh A.17, A.18, ty thu"c vothoi gian delay cn thit km ta c ththay i gi trtrong Period, n vtrong Unitsv Hardware Options-Preset chn Simple periodic interrupt.


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B.10

Hnh A.17

Hnh A.18

$tin hnh bin dch hthng, trc ht cn phi gn a ch)nn cho cc core thit kv c thc hin #ch"t"ng bng cch trn thanh cng cAltera SOPCBuilder chn System/Auto-Assign Base Addresses (Hnh A.19) kt qutrc v sau khign a ch)nn c thhin trn Hnh A.20 v A.21.


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B.11

Hnh A.19

Hnh A.20

Hnh A.21

Chn Generate bin dich hthng thit kv xut hin hp thoi (Hnh A.22)lu li hthng vi tn (Hnh A.23) trng vi tn t #phn m tthit kbng ngnngVerilog HDL (Hnh A.6).


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B.12

Hnh A.22

Hnh A.23

Chm"t khong thi gian bit kt qubin dch, kt qubin dch thnh cngc thhin trn Hnh A.24 v nu kt qusai l do phn cu hnh cc core c thbl&i.

Hnh A.24

Quay li phn mm Quartus II 10.1 vo Files trong ca sProject Navigator clickchu"t phi chn Add/Remove Files in Project sxut hin hp thoi nhHnh A.25. Sau, ch)n file .v vi tn t #Hnh A.6, chn Add, chn OK v kt qunhHnhA.26.


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B.13

Hnh A.25

Hnh A.26

Phn gn chn cho hthng c hai cch:

- To file Verilog HDL gn chn cho hthng: T*ca sproject Quartuss chnNew/Verilog HDL File (Hnh A.27), to file gn chn cho hthng bng ngn ngVerilog HDL Hnh A.28 v lu li vi tn trng vi tn module (Bai_Huon-g_Dan.v).


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B.14

Hnh A.27

- Gn chn trc tip ln skhi hthng:' Trong ca sproject Quartuss vo File/New chn Block Diagram/Schematic

Flie xut hin ca sgn chn cho hthng.' Vo Symbol Tool doubleclick vo nios_sys (Hnh A.29) ly skhi h

thng to ra t*SOPC Builder (Hnh A.30).


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B.15

Hnh A.28

Hnh A.29

Hnh A.30

' Thc hin gn chn cho hthng tng ng (Hnh A.31) vi ngvo clk_0 lCLOCK_50 v reset_n l KEY[0]. Vo Pin Tool ly ng voInput/Output/Bidir, chn Orthogonal Node Tool ly dy ni.

Hnh A.31

Nhp chu"t phi vo Bai_Huong_Dan.v chn Set as Top-Level Entily, sau voAssignments/Import Assignments ch)n t(p tin DE2_pin_assignments.csv.

Nhp chu"t vo biu tng Start Compilation trn thanh cng c hoc voProcessing chn Start Compilation bin dch, kim tra l&i v gn chn. Khi bin dch

thnh cng kt qugn chn (Hnh A.32), kim tra cc chn c gn c thvo


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B.16

Pin Planner v nu kt qubin dich sai c th do: dy ni gia cc chn, t tn file,setup license

Hnh A.32

Cui cng np file Bai_Huong_Dan.sof xung board cn nhng hthng ng dng

vo Programmer v hin h"p thoi nhHnh A.33 v sau chn Add File ch)n fileng dng (Bai_Huong_Dan.sof) thit k. $ np file Bai_Huong_Dan, nhp voProgrammer Hnh 20, trong Hardware Setup chn Hardware l USB-Blaster Hnh A.34v kt thc np ng dng thnh cng bng cch nhp vo Start.

Ty thu"c vo ng dng m xy dng cc core, cu hnh cho ph hp vi mc dchca ng dng, vphn thit knhtrn ch)mang tnh hng dn cbn vthit km"tng dng nhv nhng im chnh nhto project mi, t tn cho hthng ng dng,gn a ch)nn, gn chn, bin dch v np h thng nhng xung board phi ng vihng dn trnh by.


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B.17

Hnh A.33

Hnh A.34


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Thc tp Hthng nhng

II.1

Bi tp th nghim s2:

SOPC Builder v NIOS II IDEu tin chng ta sto mt project trn phn mm Altera Quatus II 10.1:

Vo File/New Project WizardChn th mc cha project v tn project Hnh2.1.

Hnh 2.1To project mi

Chn chip Cyclone II EP2C35F672C6 Hnh 2.2.

Hnh 2.2Chn chip xl

Trong project ny chng ta sthc hin to mt hthng SOPC bng cch sdngSOPC Builder. Hthng SOPC ny sc to ra bng file Verilog HDL:


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Thc tp Hthng nhng

II.2

Trong ca sca project Lab2, chn biu tng SOPC Builder tin hnhto mt hthng SOPC. Xut hin mt yu cu t tn cho hthng v ngn ng

to cc tp tin h thng. t tn cho h thng l nios_sys v chn ngn ngVerilog Hnh 2.3.

Hnh 2.3To hthng phn cng

To mt hthng SOPC n gin bao gm: CPU (Nios II Processor), RAM (On-chip Memory), JTAG UART, System ID:

Hnh 2.4

CPU (Nios II Processor): b x l trung tm, iu khin hot ng ca hthng. Cu hnhNios II Processor Hnh 2.4, Hnh 2.5.

RAM (On-chip Memory): dng lu dliu v lnh chng trnh. c cuhnhvi dung lng 32kb Hnh 2.6.

JTAG UART: dng kt ni vi my tnh PC np chng trnh hthngxung board DE2 Hnh 2.7.


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Thc tp Hthng nhng

II.3

Hnh 2.5

Hnh 2.6

System ID: xc nh chng trnh thc thi c bin dch tng thch vi phncng cu hnh bi SOPC Builder, khi cha to System ID trong h thng,chng trnh np xung hthng c thkhng thc thi Hnh 2.8.


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Thc tp Hthng nhng

II.4

Hnh 2.7

Hnh 2.8

Sau khi chn xong cc thnh phn cn thit cho h thng, vo System/Auto-Assign Base Addresses nh li a ch nn cho cc module. Ch g!n b nh voReset Vector v Exception Vector Hnh 2.9.

Hthng sau khi hon thnh Hnh 2.10. Sau khi hon tt chn Gernerate tocc tp tin m ththng.


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Thc tp Hthng nhng

II.5

Hnh 2.9

Hnh 2.10

Mt vi thc hin ca h thng ny trn project Quartuss: gn chn, bin dch vnp chng trnh hthng xung board DE2.

Trc khi gn chn cho hthng, trong Project Navigator chn Files/ Add/RemoveFiles in Projec chn file nios_sys.v sau chn Add/Apply/OK Hnh 2.11.

Hnh 2.11

Gn chn cho hthng

C 2 cch gn chn cbn cho hthng:

Gn chn trc tip ln skhi hthng:

Trong ca sproject Quartuss vo File\New chn Block Diagram/Sche-matic

Flie xut hin ca sgn chn cho h thng. Vo Symbol Tool ly skhi hthng (nios_sys) to ra t"SOPC Builder Hnh 2.12.


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Thc tp Hthng nhng

II.6

Hnh 2.12

Thc hin gn chn cho hthng tng ng vi ng vo clk_0 l CLOCK_50v reset_n l KEY[0] Hnh 2.13. Vo ly ng vo Input, chn ly

dy ni.

Hnh 2.13

Vo Assignments/Import Assignments d#n tp tin DE2_pin_assign-ments.csv vo mc File name xc nh chn cthng vi CLOCK_50 vKEY[0] Hnh 2.14.


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Thc tp Hthng nhng

II.7

Hnh 2.14

Lu li v thc hin bin dch, kim tra li v gn chn (nhp vo StartCompilation ). Bo bin dch thnh cng nhHnh 2.15.

Hnh 2.15

Khi gn chn thnh cng c th xem cc chn c gn, nhp vo Pin

Planner xem chi tit.

To file Verilog HDL gn chn cho hthng:

T" ca s project Quartuss chn New\Verilog HDL File. To file gn chncho h thng bng ngn ngVerilog HDL Hnh 2.16 v lu li vi tn trngvi tn module (Lab2.v).

Nhp chut phi vo Lab2.v chn Set as Top-Level Entily Hnh 2.17 sau vo Assignments\Import Assignments d#n tp tin DE2_pin_ assignments.csvvo mc File name Hnh 2.18.

Nhp chut vo biu tng Start Compilation bin dch, kim tra l$i v

gn chn. Khi gn chn thnh cng c thvo Pin Planner kim tra cc chn c gn Hnh 2.19.

Lu : trong phn ny gii thiu chai cch gn chn cho hthng nhng khi thchin chdng mt cch duy nht, khng nn thc hin chai cch v khi bin dch sgpl$i.


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Thc tp Hthng nhng

II.8

Hnh 2.16

Hnh 2.17

Hnh 2.18


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Thc tp Hthng nhng

II.9

Hnh 2.19

Sau khi bin dch np file Lab2.sof xung board DE2. np file ny, nhp vo

Programmer Hnh 2.21. Tip theo vo Hardware Setup chn Hardware l USB-Blaster Hnh 2.20.

Hnh 2.20


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Thc tp Hthng nhng

II.10

Hnh 2.21

Chn Start np file *.sof xung board. Kt qunp xung thnh cng Hnh 2.2.

Hnh 2.22

Sau khi np thnh cng h thng phn cng xung board DE2, ta s dng giphn mm Nios II Software Builder Tool for Eclipse vit chng trnh ng dng chohthng phn cng c thit k.


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Thc tp Hthng nhng

II.11

Trong ca sAltera SOPC Builder chn Nios II Software Build Tools for EclipsenhHnh 2.3.

Hnh 2.23

Chn %ng d#n ni lu trphn mm ng dng Hnh 2.4.

Hnh 2.24

Sau khi chn %ng d#n, Nios II Software Builder Tool for Eclipse to ra ca sson tho chng trnh ng dng. To project mi lm vic, vo File\New chn Nios

II Application and BSP form Template Hnh 2.5. Xut hin ca sNios II Applicationand BSP form Template Hnh 2.6.


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Thc tp Hthng nhng

II.12

Hnh 2.25

Hnh 2.26

Trong mc Target hardware information, SOPC Information File name, chn %ngd#n n file nios_sys.sopcinfo cha thng tin phn cng hthng. Trong mc Application

project, t tn cho project ca chng trnh ng dng (v dlab2). Trong mc Project


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Thc tp Hthng nhng

II.13

template chn project m#u l Hello world small cha chng trnh m#u. Chn Finish to project mi, project lab2 c to nhHnh 2.7

Hnh 2.27

Nhp chut phi vo lab2_bsp [nios_sys] chn Properties\Nios II BSP Properties,thit t nhHnh 2.8, chn Apply\OK.

Hnh 2.28

Thc hin bin dch chng trnh ng dng, nhp chut phi vo lab2 chn BuildProject. Chng trnh ng dng trong bi tp lab2 ny s dng code m#u c s&n caproject m#u Hello world small Hnh 2.9 thc hin chc n'ng n gin xut ra mn Hnh2.chui k tHello from Nios II! chui k tny c ththay i theo mun.


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Thc tp Hthng nhng

II.14

Hnh 2.29

Chy chng trnh ng dng, nhp chut phi ln lab2 chn Run As\ Run-Configurations... Hnh 2.30. Xut hin ca sRun Configurations Hnh 2.31.

Hnh 2.30


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Thc tp Hthng nhng

II.15

Hnh 2.31

Nhp p vo Nios II Hardware to New_configurations, chn tab TargetConnection, mc System ID Check chn Ignore mismatched system ID v Ignoremismatched system timestamp tip theo chn Apply v Run np chng trnh ngdng xung phn cng Hnh 2.32.

Kt qu chy c ca chng trnh l hin th chui k t Hello from Nios IItrong ca sNios II Console Hnh 2.33.


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II.16

Hnh 2.32

Hnh 2.33


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III.1

Bi tp th nghim s3:

Hthng n ginMc ch ca bi tp ny l hc cch to v sdng mt hthng my tnh n gin

nh th no. H thng bao gm Altera Nios II processor v chng trnh ng dng.Chng ta ssdng phn mm Quartus II v SOPC Builder to thnh phn phn cngca hthng. V chng ta ssdng phn mm Altera Programe Monitor bin dch,np v chy chng trnh ng dng.

Phn I

Trong by tp ny, bn ssdng SOPC Builder to hthng trong Hnh 3.1. Hthng ny bao gm mt khi xl Nios II/e processor v mt bnh. Nios II/e processordng xl dliu, khi bnhdng lu trlnh v dliu (ging nhlab2).

Hnh 3.1 Hthng my tnh n gin

Thc hin hthng trong Hnh 3.1 nhsau:

1.To mi mt project Quartus II. Chn chip Cyclone II EP2C35F672C6, n lchip FPGA trn board DE2

2.Sdng SOPC Builder to hthng c t tn l nios_system, hthngbao gm cc thnh phn nhsau:

3.Nios II/e vi JTAG Debug Module Level 1

4.On-chip memory - chRAM c dung lng 32 Kb vrng dliu 32 bit.

5.T"menu hthng, chn Auto-Assign Base Addresses tng gn a chnn cho hthng. Bn nn to hthng ging nhHnh 3.1.

6.To hthng, sau khi to xong, thot khi SOPC v trli phn mm Quartus II

7.Thc hin gn chn cho hthng, c ththc hin mt trong hai cch bi tplab2, kt ni cc chn nhsau:

clk PIN_N2 (xung clock ny l 50 MHz)

reset n PIN_G26 (chn ny l KEY0)

8.Bin dch project Quartus II


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III.2

9.Sau khi bin dch hthng c ththc hin nhng chng trnh ng dng npxung. sdng hthng, chng ta c mt chng trnh ng dng thchin, ta sthc hin n phn II ca bi tp.

Phn IITrong my tnh s, tt cdliu c biu di(n bng chu$i s1 v 0. Chng trnh

vit bng ngn ngassembly trong kim tra dliu v xc nh chu$i s1 lin tip lnnht trong dliu ny. Cho v d, gi trca dliu l 0x937a (1001001101111010) c 4s1 l gi trln nht ca chu$i 4 smt lin tip. Code bn di xc nh schu$i s1lin tip cho dliu c gi trl 0x90abcdef.

.include "nios_macros.s"

.text

.equ TEST_NUM, 0x90abcdef /* so duoc test */

.global _start_start:movia r7,TEST_NUM /* khoi tao r7 co gia tri la TEST_NUM */mov r4, r7 /* copy TEST_NUM vao r4 */

STRING_COUNTER:mov r2, r0 /* khoi tao r2 bang 0 (bien dem) */

STRING_COUNTER_LOOP: /* vong lap tinh so bit 1 lien tiep lon nhat */beq r4, r0, END_STRING_COUNTERsrli r5, r4, 1 /* tinh so bit 1 lien tiep bang cach dich du

lieu duoc*/and r4, r4, r5 /* test sang phai 1 bit va and no voi du lieu ban

dau */addi r2, r2, 1 * tang bien dem len 1 */br STRING_COUNTER_LOOP

END_STRING_COUNTER:mov r16, r2 /* ket qua cuoi cung luu vao r16 */

END:br END

.end

Thc hin chng trnh trn nhsau:

1.MAltera Monitor Program v ci t n sdng hthng to phn Iv chng trnh ng dng trong trn.

2.Vo File/New Projectchn %ng d#n thmc cha project v tn project.


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III.3

Hnh 3.2 To thmc project

Hnh 3.3 Chn file hthng .sof v .ptf

Hnh 3.4 Chn ngn nglp trnh

Hnh 3.5 Add file chng trnh hthng .s (ngn ngAssembly)


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III.4

Hnh 3.6 Ch%ng d)n ti file .s

Hnh 3.7 Add vo

3.Bin dch v np chng trnh .

Hnh 3.8

4.Tr%ng hp mun thay i code source ta ng Altera Monitor Program (nuang m) v mli chng trnh, chn Open Project mli project

to. Sau khi mli project chn , chn tab Program Settings, chn filesource cchn remove, nhp vo Addchn file source mi v tin hnhbin dch, np chng trnh.

5.Chy chng trnh t"ng bc v xem cc thay i trong cc thanh ghi xl nhthno.

Ch rng khi kt thc chng trnh th kt qutrvl 4 trong thanh ghi r16, ktqutrong Hnh 3.9.


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III.5

Hnh 3.9 Kt quchng trnh sau khi chy

6.t Program Counter ti 0x00008000. Ti a chny cho php chng ta thchin li chng trnh, trong khi b*qua 2 lnh u tin.

7.im d"ng chng trnh a ch0x00008028, kt"a chtuy cp chngtrnh cng thm 0x28, v thchng trnh stng d"ng li cui chngtrnh.

8.t thanh ghi r7 c gi trl 0xabcdef90. C bao nhiu bit 1 lin tip trong sny? Chy li chng trnh xem nu bn on ng.


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III.6

Hnh 3.10Kt qukhi thay i chu$i bt u vo (0xabcdef90)

Phn III

Trong phn ln cc chng trnh ng dng th cc thnh phn ca code sc thchin nhiu th%i gian t"nhng vtr khc nhau trong chng trnh. Cc phn ca code cththc hin bng chng trnh con. Chng trnh con c thchy t"nhng vtr bt ktrong chng trnh bng cch sdng lnh gi. Chng trnh trvsau lnh gi chngtrnh con (khi chng trnh con thc hin xong), chng trnh con kt thc vi lnhret. Chng ta sto ra chng trnh con ngay by gi%tnh sbt 1 lin tip c+ng nhtnh sbit 0 lin tip trong dliu cho.

B!t u vi chng trnh cho phn II v chnh sa n li nhbn di:

1.Ly code tnh sbit 1 lin tip v to cho n mt chng trnh con. Chngtrnh con sdng thanh ghi r4 nhn dliu vo v thanh ghi r2 xut rakt qu.

2.Gi chng trnh con v"a mi to 2 ln, mt tnh sbit 1 lin tip v mttnh sbit 0 lin tip.

3.Ghi sbitb1 lin tip vo thanh ghi r16 v sbit 0 vo thanh ghi r17.


.text

.equ TEST_NUM, 90abcdef /* so duoc test */

.equ bit1, 0x00000000

.equ bit0, 0xffffffff

.global _start

_start:


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III.7

movia r9, bit1movia r10, bit0movia r7, TEST_NUM

movia r8, bit1call CALCULATE /* goi chuong trinh con lan 1 */

mov r16, r2 /* r16 chua so bit 1 lien tiep */

movia r8, bit0call CALCULATE /* goi chuong trinh con lan 2 */

mov r17, r2 /* r16 chua so bit 0 lien tiep */

END:br END

CALCULATE: /*chuong trinh con */mov r4, r7mov r2, r0

beq r8, r9, STRING_COUNTER_LOOP_1beq r8, r10, STRING_COUNTER_LOOP_0

STRING_COUNTER_LOOP_1: /* vong lap tinh so bit 1 lien tiep */beq r4, r8, END_STRING_COUNTER

srli r5, r4, 1and r4, r4, r5addi r2, r2, 1br STRING_COUNTER_LOOP_1

STRING_COUNTER_LOOP_0: /* vong lap tinh so bit 0 lien tiep */beq r4, r8, END_STRING_COUNTERsrli r5, r4, 1or r4, r4, r5addi r2, r2, 1

br STRING_COUNTER_LOOP_0END_STRING_COUNTER:

mov r2, r2ret

.end

Kt qusau khi thc hin chng trnh trn:


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III.8

Hnh 3.11 Kt quthc thi chng trnh


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IV.1

Bi tp th nghim 4:

Chng trnh iu khin xut/nhpMc ch ca bi tp ny: nghin cu sdng cc thit b, cc khn'ng cung cp

ng vo v ng ra cho bxl v c iu khin bng phn mm. Chng ta skim trachng trnh iu khin hot ng xut/nhp ny t"hai phn: phn cng v phn mm xem chi tit hn. Chng ta s s dng cc giao din nh: parallel, PIO trong h thngNios II v c thc thi trn board DE2. Trc tin cn phi c kin thc nn lm bitp ny, c th tm hiu t" ti liu hng d#n: Introduction to the Altera Nios II SoftProcessor v Introduction to the Altera SOPC Builder (tm ti liu ny trn web site caAltera).

Trong bi tp ny sdng giao din PIO, cu hnh PIO to ra bng cch sdngSOPC Builder v cp d liu truyn vo trong m$i ng vo hoc ng ra hoc c hai.

%ng truyn chc thchp nhn: song song v t"1 n 32 bit. Sbit v %ng i cadliu c nh ngh,bng cch ng%i dng thng qua SOPC Builder v giao din PIOc thcha bn thanh ghi trnh by trong Hnh 4.1.

Hnh 4.1Thanh ghi trong giao din PIO

M$i thanh ghi Hnh 4.1 c di n bit. Cc thanh ghi c chc n'ng nhsau:

- Thanh ghi Data cha n bit dliu, dliu truyn vo thanh ghi Data t"giao dinPIO v bxl Nios II. Thanh ghi Data thc hin nh: ng vo, ng ra hoc ngvo ra thit kbi SOPC Builder.

- Thanh ghi nh hng xc nh hng truyn t"ng bit dliu khi giao thc ngvo ra c to ra.

- Thanh ghi Interrupt-mask c sdng cho php ng!t (xl ng!t cho php haykhng cho php) cc u vo kt ni vi PIO.

- Thanh ghi chn cnh: cho thy khi thay i mc logic c pht hin trong tn

hiu trn u vo kt ni vi PIO.


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IV.2

Tt cthanh ghi Hnh 4.1 khng phi mt giao thc PIO cthno (u vo, u rav u vo ra) c+ng to ra cc thanh ghi , m ch thanh ghi nh hng mi c giaothc ng vo ra.

Thanh ghi PIO c thtruy cp nhl a chbnh, a chnn c t nht 4 bit vn c thc gn ti PIO (nh%vo chng trnh SOPC Builder tng lm vic ny)vi a chu tin l thanh ghi Data v 3 thanh ghi tip theo sc lch 4, 8, 12 bytetng ng vi 1, 2 v 3 word. di(n tchi tit hn vmodule PIO chng ta c thtm trong ti liu PIO Core with Avalon Interface c trn web site ca Altera.

-ng dng trong bi tp ny l thc hin php ton cng dn snhphn c ti a8 bit thng qua swich trn board DE2, kt qushin thtrn LED hoc 7-segment.

Bi tp 1:

Chng ta sdng 8 switch (t"switch 0 n swich 7) nhp scho ng vo, 8 LED

xanh (t"LED 0 n LED 7) hin th snhp vo t" switch v kt qu cng dn sc hin thln 16 LED *(t"LED 0 n LED 15). Do phn h thng cn 3 giaothc PIO thc hin yu cu t ra.

Trong phn PIO sto ra 3 kt ni nhsau:

-Kt ni vi switch dng lm ng vo d liu ti a 8 bit chng trnh iukhin c thc.

-Kt ni vi LED xanh c ti a 8 bit dng hin thsnhp dliu t"switch.-Kt ni vi LED *c ti a 16 bit dng hin thkt qusau m$i ln cng v

kt qusc cng dn.

Thc hin yu cu phn cng a ra bng cng ch thng Nios II trn boardDE2 nhsau:

-To ra project Quartus II 10.1 mi, cc bc to project thc hin t"ng tnhbi th nghim Lab 2.

-Sdng SOPC Builder to ra mch mong mun vi tn nios_sys (Hnh 4.2)bao gm cc thnh phn:

Hnh 4.2t tn cho hthng SOPC Builder


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IV.3

Trong Nios II Processor: phn select a Nios II core chn Nios II/s, HardwareMultiply chn Embedded Multipliers v check vo Hardware Divide (Hnh4.3) v phn select a debugging level chn Level 1 (Hnh 4.4).

Hnh 4.3Chn cu hnh Nios II

On-Chip Memory (RAM or ROM) kiu RAM v 32 Kbyte trong size (Hnh4.5).

Trong phn giao thc PIO sthit kba mch kt ni (Hnh 4.6 v 4.7) gm:1 u ra 8bit (LED xanh), 1 u ra 16bit (LED *) v 1 u vo 8bit (switch).

Hnh 4.4Chn cp Debug


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IV.4

Hnh 4.5Cu hnh bnhon-chip memory

Hnh 4.6Thnh phn trong hthng SOPC Builder


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IV.5

Hnh 4.7Cu hnh PIO

Hthng SOPC Builder stng gn cc tn nh: pio_0, pio_1 v pio_2 cho bathnh phn PIO. Chng ta c th thay i tn ba thnh phn PIO cho ph hp vingh,a ca tnh hung, v d: pio_0 i thnh New_number, pio_1 i thnh Green_LEDsv pio_2 i thnh Red_LEDs (Hnh 4.8).

Hnh 4.8Hthng ng dng

Thit kthm cho hthng phn system ID (chn chmc nh) nhHnh 4.9,cui cng vo menu System chn Auto-Assign Base Addresses tng gn a chcho tt ccu hnh trong hthng thit kv kt quc thhin Hnh 4.10.


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IV.6

Hnh 4.9Chn thnh phn System ID

Hnh 4.10Kt quthit khthng ng dng

Khi to hthng Nios c to ra trong mt tp tin HDL Verilog hoc skhihthng biu thcc kt ni cn thit ti cc switch v cc LED trn board DE2.

Gn cc chn cn thit lm cho cc kt ni hon thnh, bng cch voAssignment/Import Assignments ch n file DE2_pin_assignments.csv. Cui cngbin dch project Quartus II project.

Bi tp 2:

Sdng ngn ngAssembly thc hin bi tp nhsau:

- Vit chng trnh c ni dung ca cc switch, hin thgi trtng ng ln LEDxanh, tch lu.cc ln cng v hin thtng ln LED *.

- Sdng phn mm Altera Program Monitor kt ni v ti chng trnh.- Thng qua chng trnh kim tra kt qu bng cch nhp mt vi s t" switch.

Ch chng trnh ch cho php s ng vo khng thay i nhiu s (trong 8switch mt ln chthay i trng thi mt trong 8 switch ).

File Lab4_Bai2.equ.s c ni dung sau:

.equ NEW_NUMBER, 0x00011000

.equ GREEN_LEDS, 0x00011010

.equ RED_LEDS, 0x00011020


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IV.7

File Lab4_Bai2.s c ni dung sau:


.include "Lab4_Bai2.equ.s"

.text

.global _start_start:

add r17, r0, r0movia r8, NEW_NUMBERmovia r9, GREEN_LEDSmovia r10, RED_LEDS

MAIN_LOOP:ldwio r16, 0(r8)stwio r16, 0(r9)

add r17, r17, r16stwio r17, 0(r10)br MAIN_LOOP

.end

Kt qu:

Khi nhp s12t"switch sc lu vo thanh ghi r16, gi trtrong thanh ghi r16cng vi gi tr trong thanh ghi r17 (ban u c gi trbng khng) sau lu kt qunhn c c gi trl 1 vo thanh ghi r17 nhthhin trn Hnh 4.11.

Tip theo nhp s1002t"switch c lu vo thanh ghi r16, r16 cng vi r17 (c

gi trl 12) v kt qunhn c thanh ghi r17 nhtrnh by Hnh 4.12 v 4.13.

Hnh 4.11Gi trtrong thanh ghi


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IV.8



Bi tp 3:

Trong bi tp ny, mun thm khn'ng chy chng trnh ng dng lin tc v iukhin c smi bng cch nhn mt pushbutton bi ng%i sdng khi smi s&n sngc. Mong mun chng trnh hot ng cng sktip bng cch chuyn i switchcho ph hp vi scn nhp sau nhn pushbutton chra rng con sny honthnh cho vic c.

hon thnh bi tp ny cn phi thc hin c ch theo di trng thi ng vo.-ng dng xut/nhp thng th%ng sdng c%trng thi ban u xa v0. Trong chng


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IV.9

trnh ny c%trng thi ban u c t mc 1 ngay sau khi cc thit bs&n sng chovic truyn dliu ktip, sau khi truyn dliu c%trng thi sxa v0. Do , bxl th'm d c%trng thi xc nh vic thc hin truyn dliu.

Trong tr%ng hp ny, thit bxut/nhp c ng%i sdng t bng tay cho ccswitch. c c%trng thi, chng ta sto mch PIO c bit ch1 bit v sdng chcn'ng pht hin cnh xung. Giao din PIO c to ra rt ging vi PIO thng th%ngnhng ph hp vi s thanh ghi Hnh 4.1 v c nh ngh,a trong th mcaltera_up_avalon_DE2_pio (c thly t"Altera University Program hoc link http://ww-w.mediafire.com/?ln92t5fa50bvtso).

Sau y l cc bc hng d#n thc hin:

- To project mi v thc hin xy dng hthng ging nhbi tp 1.- Copy thmc altera_up_avalon_DE2_pio vo trong project. MSOPC, trn thanh

menu chn File/Refresh System (F5). Phn DE2-PIO s xut hin bn diComponents Library/Project/University Program DE2 Board (Hnh 4.14).

Hnh 4.14Chn giao din DE2 PIO

- To c%trng thi sdng cu hnh DE2-PIO v ng vo l 1 bit. Trong tab InputOption chn Synchronously capture khi ng tnh n'ng c bit Falling trongEdge Type.

- Thay i file Verilog ca bi tp 1 hon thnh hthng. Sdng nt nhn KEY1 lm ng vo cho c%trng thi (nt nhn hot ng mc thp).

- Gn chn v bin dch project.- Thay i chng trnh ng dng smi c chp nhn khi KEY 1 c nhn.

Chng trnh skim tra bit ca c%trng thi t"mc cao xung mc thp.- Download v chy chng trnh kim tra kt qulm vic. Chng trnh chy

lin tc v smi sc cng vo sau m$i ln nhn KEY 1.


.equ NEW_NUMBER, 0x00011000

.equ GREEN_LEDS, 0x00011010

.equ RED_LEDS, 0x00011020


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IV.10

.equ STATUS_FLAG, 0x00011030




.text

.global _start

_start:

add r17, r0, r0

movia r7, STATUS_FLAG

movia r8, NEW_NUMBER

movia r9, GREEN_LEDS

movia r10, RED_LEDS

MAIN_LOOP:

ldwio r15, 0(r7)

ldwio r16, 0(r8)

stwio r16, 0(r9)

bne r15, r0, MAIN_LOOP

END_MAIN_LOOP:

ldwio r15, 0(r7)

beq r15, r0, END_MAIN_LOOP

add r17, r17, r16

stwio r17, 0(r10)

br MAIN_LOOP

.end

Kt qu:Khi nhp sB616 t"switch sc lu vo thanh ghi r16, trong th%i gian ny c

ththay i gi tr, khi gi trng vi mong mun v ch%trng thi trong thanh ghi r15c gi tr l khng s thc hin cng gi tr ca r16 vi r17 (ban u c gi tr bngkhng) sau lu kt quvo r17 nhthhin trn Hnh 4.16. Ngc li trang thi trongthanh ghi r15 bng 1 chng trnh sng ch%v r17 v#n gi nguyn gi tr ban u(Hnh 4.15).


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IV.11

Hnh 4.15 Hnh 4.16


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V.1

Bi tp th nghim lab 5:

Chng trnh con v ngn xpMc ch ca bi tp ny l hc vchng trnh con v lin kt chng trnh con

trong mi tr%ng Nios II. Bao gm khi nim vtruyn tham sv ng'n xp.

Phn I

Chng ta s s dng h thng Nios II bao gm b nh on-chip v module JTAGUART cho giao tip vi my tnh ch.

Hnh 5.1

Thc hin hthng nhbn di:

1.To mi mt project Quartus II, chn chip xl Cyclone II EP2C35F672C6.

2.Sdng SOPC Builder to hthng vi tn nios_system bao gm cc thnhphn:

Khi xl Nios II/s prosessor vi JTAG Debug Module Level 1. Bnhon-chip (RAM) vi dung lng 32 Kbytes.

3.T"menu hthng, chn Auto-Assign Base Addresses. Bn nn to hthngnhHnh 5.1.

4.To hthng, thot kh*i SOPC Builder v trli phn mm Quartus II

5.Thc hin gn chn, bin dch v np xung board DE2 nhcc bi tp thnghim trc.

Phn II

Chng ta s!p xp danh sch cc snguyn 32 bit theo th t t'ng dn. Danh schny c Hnh 5.thc l mt tp tin vi su tin l kch thc ca chui s 32 bit cnc s!p xp v phn cn li l cc sc s!p xp. Thc hin cng vic mong munbng cch sdng ngn ngassembly:

6.Vit chng trnh c ths!p xp danh sch cc scha trong tp tin c npxung bnhb!t u ti vtr LIST FILE. Gisdanh sch ln v thnkhng thsao chp trong bnh.


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V.2

7.Do , qu trnh s!p xp phi thc hin ti ch, nn c2 danh sch scs!p xp v danh sch sban u u chim vtr nhnhau trong bnh.

8.Bin dch v download chng trnh ca bn sdng Altera Program Monitor.

9.To danh sch m#u, np n vo bnhv chy chng trnh ca bn. Danhsch sc to bng file .txt. Np danh sch vo bnhnhsau:

Sau khi bin dch v np thnh cng chng trnh Lab5_part2.s, ta npdanh sch cc s cn s!p xp xung b nh. Trong Altera ProgrameMonitor, chn tab Memory, xut hin a chcc vng bnhnhHnh 5.2.Ta thc hin lu file danh sch cc s ti vng a ch 0x00009000 (sHex). G*s9000 vo Address (hex) ri bm Go di chuyn ti vng ach9000 Hnh 5.3.

Hnh 5.2


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V.3

Hnh 5.3

Nhp phi chut, chn Load file into memory, vo Browse ch%ng d#n n file danh sch .txt (number.txt), chn du , lm ng'n cchgia cc strong danh sch, kch thc ca m$i sl 4 byte (Value size),a chb!t u l 9000. Gi trca cc strong danh sch c np vo bnh nh Hnh 5.4. Danh sch cc s trong number.txt nh sau:f,6,11,22,4,90,100,50,9,76,12,11,13,54,67,44 trong s f (12) u tintrong danh sch l slng cc sc s!p xp.

Hnh 5.4


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V.4

Kt qutrc khi chy chng trnh Hnh 5.5:

Hnh 5.5

Kt quchng trnh sau khi chy l Hnh 5.6:


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V.5

Hnh 5.6

Khi thay i gi trcc strong danh sch cc sc s!p xp c+ng nhslngcc s trong danh sch th vic s!p xp v#n ng v dcho chng trnh s!p xp danhsch cc snhsau: 7, 9, 7, 8, 6, 3, 5, 2 trong s7 u tin trong danh sch l slngcc sc s!p xp.

Trc khi chy chng trnh kt qunhHnh 5.7:


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V.6

Hnh 5.7

Sau khi chy chng trnh kt qunhHnh 5.8:


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Thc tp hthng nhng

V.7

Hnh 5.8

Ch : tp tin cha danh sch c thc np vo bnhbng cch sdng AlteraProgram Monitor. chng trnh c ths!p xp cc strong danh sch theo thtgimdn ta sthay lnh bltbng lnh bgt.

Lab5_part2.s.include "nios_macros.s".text

/**************************************************************/

/* Sap xep danh sach so 32 bit trong bo nho *//* r8 - kich thuoc dia chi cua danh sach cac so *//* r9 - dia chi cua so dau tien trong danh sach *//* r10 - dia chi phan tu hien tai dang duoc kiem tra *//* r16 - so dau tien duoc so sanh *//* r17 - so thu hai duoc so sanh *//* r18 - co chi rang hoan doi vi tri da xay ra *//* r19 - kiem tra khi moi thanh phan duoc kiem tra *//* r20 - kich thuoc cua danh sach cac so */.global _start

_start:


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V.8

movia r8, SIZEmovia r9, LIST

BEGIN_SORT:ldwio r20, 0(r8)

RESTART_SORT:mov r18, r0movi r19, 1mov r10, r9

SORT_LOOP:ldwio r16, 0(r10)ldwio r17, 4(r10)blt r16, r17, SKIP_SWAP

SWAP:stwio r17, 0(r10)stwio r16, 4(r10)movi r18, 1

SKIP_SWAP:addi r19, r19, 1addi r10, r10, 4

bne r19, r20, SORT_LOOPbne r18, r0, RESTART_SORT

END:br END

.org 0x01000LIST_FILE:SIZE:.word 0LIST:

.end

Phn III

Trong phn ny, chng ta sdng chng trnh con thc hin cng vic s!p xp.to chng trnh con tng qut, ni dung thanh ghi c sdng bng chng trnhcon lu vo ng'n xp v phc hi li trc khi r%i kh*i chng trnh con. Ch rngng'n xp c to bng cch khi to con tr*ng'n xp, thanh ghi r27. N l cch thchin thng dng khi to ng'n xp v tr a chcao ca bnhv lm n hngtheo a chthp.


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Thc tp hthng nhng

V.9

Con tr*ng'n xp c iu chnh r rng khi c t vo hoc xa kh*i ng'n xp.to ng'n xp t"a chcao n a chthp, con tr*ng'n xp c lm gim 4 n vtrc khi nhp mi vo ng'n xp v n c t'ng 4 n vsau khi ng'n xp c xa.

Thc hin cng vic ny bng cch sa i chng trnh ca bn t"phn II nhsau:1. Vit chng trnh con, c gi l SORT, n c ths!p xp danh sch c

kch thc bt k/mt a chty trong bnh. Gisrng kch thcv vtr ca danh sch l cc tham sc thng qua chng trnh conbng thanh ghi sao cho:

Tham skch thc cho bi ni dung trong thanh ghi r2 a chnhp vo u tin trong danh sch cho bi ni dung trong thanh ghi

r3.

2. Vit chng trnh chnh, n khi to con tr*ng'n xp, t yu cu tham s

trong thanh ghi r2 v r3 v gi chng trnh con SORT. Danh sch cti trong bnhvtr LIST FILE.

3. Bin dch v np chng trnh ca bn.

4. To danh sch m#u, ti n vo trong bnh, v chy chng trnh cabn.

Khung code bng ngn ngassembly cho Lab5_part3.s


.text

.equ STACK, 0xB000


movia sp, STACKmov fp, sp

movia r8, SIZEmovia r9, LIST

ldwio r2, 0(r8)mov r3, r9

call SORTEND:

br END

/**************************************************************//* chuong trinh con *//* Sap xep danh sach so 32 bit trong bo nho *//* r2 - kich thuoc cua danh sach cac so *//* r3 - dia chi cua so dau tien trong danh sach */

/* r8 - dia chi phan tu hien tai dang duoc kiem tra */


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Thc tp hthng nhng

V.10

/* r16 - so dau tien duoc so sanh *//* r17 - so thu hai duoc so sanh *//* r18 - co chi rang hoan doi vi tri da xay ra */

/* r19 - kiem tra khi moi thanh phan duoc kiem tra *//* r20 - kich thuoc cua danh sach cac so */

SORT:subi sp, sp, 28 /* luu tat ca cac thanh ghi duoc su dung vao ngan

xep */stw ra, 0(sp)stw fp, 4(sp)stw r8, 8(sp)stw r16, 12(sp)stw r17, 16(sp)stw r18, 20(sp)stw r19, 24(sp)addi fp, sp, 28

BEGIN_SORT:RESTART_SORT:

mov r18, r0movi r19, 1mov r8, r3

SORT_LOOP:

ldwio r16, 0(r8)ldwio r17, 4(r8)blt r16, r17, SKIP_SWAP

SWAP:stwio r17, 0(r8)stwio r16, 4(r8)movi r18, 1

SKIP_SWAP:addi r19, r19, 1addi r8, r8, 4

bne r19, r2, SORT_LOOPbne r18, r0, RESTART_SORT

END_SORT:

ldw ra, 0(sp) /* gia tri */ldw fp, 4(sp)ldw r8, 8(sp)ldw r16, 12(sp)ldw r17, 16(sp)

ldw r18, 20(sp)


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Thc tp hthng nhng

V.11

ldw r19, 24(sp)addi sp, sp, 28ret

/* ket qua tu chuong trinh con */

.org 0x01000LIST_FILE:SIZE:.word 0LIST:

.end

Kt quca chng trnh phn III ny ging vi kt quca chng trnh phn

II.


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Thc tp hthng nhng

VI.1

Bi tp th nghim lab 6:

c lin tc v ngtMc ch ca thc hnh ny l tm hiu lm thno gi v nhn d liu t"

thit bxut /nhp, c hai phng php c sdng nhn bit c hay khng c dliu, c thgi hoc s&n sng nhn t" thit bxut/nhp. Phng php u tin, c dliu lin tc, bxl truy cp n cc thit bkim tra xem c nhn c dliu haykhng. Phng php thhai, dng ng!t, cc thit bbo cho bxl bit n c thnhnc dliu hoc dliu c s&n m khng xl theo yu cu mt cch r rng.

Mt chng trnh n gin v th%ng sdng chuyn dliu gia bxl vthit b xut/nhp c gi l UART (Universal Asynchronous Receiver Transmitter).

Giao thc (mch) UART c t gia bxl v thit bxut/nhp. Vic chuyn giaodliu gia UART v bxl c thc hin mt cch song song, ni m tt ccc bitca mt k tc chuyn giao ti cng mt th%i im sdng %ng truyn ring bit.Tuy nhin, vic chuyn giao dliu gia UART v thit bxut/nhp c thc hin theocch truyn ni tip v cng th%i im.

SOPC Builder c th thc hin giao din ca cc loi UART sdng trong hthng Nios II v c gi l JTAG UART. JTAG UART c thc to ra cung cpkt ni gia bxl Nios II v host computer kt ni n board DE2. Hnh 6.1 l skhi ca giao din JTAG UART, trong core JTAG UART c hai thanh ghi (Hnh 6.2):thanh ghi Data v thanh ghi Control, c truy cp trong bx l nhl v tr bnh,

m$i thanh ghi c 4 byte v a chca thanh ghi Control ln hn so vi a chc gncho thanh ghi Data. Ngoi ra, trong core cn cha hai FIFO ng vai tr nhl blu trm, cho php truyn v nhn dliu t"my ch.

Hnh 6.1 Skhi giao din JTAG UART


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Thc tp hthng nhng

VI.2

Hnh 6.2Skhi thanh ghi trong JTAG UART

Cc tr%ng trong thanh ghi Data c sdng nhsau:

- T"bit 0 bit 7 (tr%ng DATA): k t8 bit c t vo trong Write FIFO khithc hin thao tc lu trt"bxl hoc k tc ct"Read FIFO khi thchin thao tc ti dliu.

- Bit 15 (tr%ng RVALID) cho bit trong tr%ng DATA c k tbxl c thc. Nu trong tr%ng DATA c d liu th bit 15 c gi trl 1 v ngc li cgi trl 0.

- T"bit 16 bit 31 (RAVAIL) cho bit sk tcn li trong Read FIFO.

Cc tr%ng trong thanh ghi Control c sdng nhsau:

- Bit 0 (RE) cho pht c ng!t khi t ln 1.- Bit 1 (WE) cho php xl ng!t khi t ln 1.- Bit 8 (RI) cho bit c ng!t ang ch%c nu c gi trl 1. Khi c thanh ghi Data

RI sxa v0.- Bit 9 (WI) cho bit c mt ng!t ang ch%xl nu c gi trl 1.- Bit 10 (AC) cho bit JTAG ang hot ng (host computer gi JTAG UART

kim tra kt ni c tn ti hay khng) khi AC c gi trl 0.- Bit 16 bit 31 (WSPACE) cho bit skhong trng trong Write FIFO.

Trong bi tp 1 v 2 ssdng JTAG UART truyn k tASCII gia bxl

Nios II trn board DE2 v host computer. Ngoi ra, trong bi tp 3 sdng thm phninterval timer nh tr(cho chng trnh ng dng.

Bi tp 1:

S dng SOPC Builder to h thng nh Hnh 6.3 gm c: b x l Nios II,JTAG UART, bnhv Interval Timer.

Hthng c thc hin nhsau:

- To project mi, chn Cyclone II EP2C35F672C6.- Sdng SOPC Builder to hthng tn nios_sys bao gm cc thnh phn sau:

Nios II/s processor vi JTAG Debug Module Level 1.


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Thc tp hthng nhng

VI.3

Kch thc bnhRAM l 32 Kbyte (On-chip memory).JTAG UART sdng chmc nh.

Interval Timer t li hai thnh phn sau: Timeout period- Period chn500ms nh Hnh 6.4 v Hardware Options-Preset chn Simple periodicinterrupt.

Hnh 6.3Skhi hthng ng dng

Phn gn a chnn nhbi tp th nghim trc v kt quhthng c to ranhHnh 6.5:

Cui cng l phn to file Verilog HDL gn kt ni cc chn:

- Clk PIN N2 (tn s50MHz).- Reset_n PIN G26 (KEY 0).

Bi tp 2:

JTAG UART c thgi k tASCII n Altera Program Monitor v hin thk t trong ca sTerminal. Khi tr%ng WSPACE trong thanh ghi Control c gi trkhckhng cho bit c thJTAG UART ghi k tmi n Altera Program Monitor. K tghi

ti Altera Program Monitor, sc lin tc vo thanh ghi trc khi c khong trng. Khic khong trng k tASCII c thghi vo trong thanh ghi Data ca JTAG UART.

Vit chng trnh bng ngn ngAssembly hin thi chZ khong 500ms trongca sTerminal ca ASCII n Altera Program Monitor. To v thc thi chng trnhsau:

- Sdng ngn ngAsembly vit vng lp c thanh ghi Control trong JTAG UARTv nhy ti ch$trc khi mt vi khong trng ghi s&n sng.

- Ghi chZ n thanh ghi Data.- Sdng phn mm Altera Program Monitor bin dch v np chng trnh

Assembly.


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Thc tp hthng nhng

VI.4

- To delay sao cho in ra 1 k tsau khong 0.5s.- Bin dch, np v chy chng trnh.

Hnh 6.4Cu hnh cho Interval Timer

Hnh 6.5Kt quthit khthng ng dng


.equ JTAG_UART, 0x00011028

.equ TIMER, 0x00011000

.equ STACK, 0x00010800




.text



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Thc tp hthng nhng

VI.5

movia sp, STACKmov fp, sp

movia r8, JTAG_UARTmovi r16, Z

PUT_CHAR_LOOP:ldwio r17, 0(r8)andhi r17, r17, 0xffffbeq r17, r0, PUT_CHAR_LOOPstwio r16, 0(r8)mov r18, r0

DELAY_LOOP:addi r18, r18, 1

andhi r19, r18, 0x0010beq r19, r0, DELAY_LOOPbr PUT_CHAR_LOOP

END:br END

.end

Kt qu: c thhin trn Hnh 6.6 v 6.7.


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Thc tp hthng nhng

VI.6


Hnh 6.7Ca sTerminal

Bi tp 3:

JTAG UART c thnhn k tASCII t"thit bu cui window, c+ng nhghi lnJTAG UART. Bit RVALID (bit 15) trong thanh ghi dliu cho bit c hay khng c ktASCII trong tr%ng DATA. Nu c k ttrong tr%ng DATA ng ch%c c thtr%ng RVALID sc gi trkhc khng.


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Thc tp hthng nhng

VI.7

Vit chng trnh thc hin nhim v nh "my nh ch", c m$i k t nhnc bi JTAG UART t"host computer v sau hin thk t trong ca sthit b

u cui ca chng trnh Altera Program Monitor.Lu : con tr*phi a vo trong ca sthit bu cui ca chng trnh Altera

Program Monitor vit k tn cng JTAG UART.


.equ JTAG_UART, 0x00011028

.equ TIMER, 0x00011000

.equ STACK, 0x00010800




.text


movia sp, STACKmov fp, spmovia r6, JTAG_UART

PUT_CHAR_LOOP:ldwio r4, 0(r6)

andi r8, r4, 0x8000beq r8, r0, PUT_CHAR_LOOPandi r5, r4, 0x00ff

call PUT_JTAGbr PUT_CHAR_LOOP

.global PUT_JTAGPUT_JTAG:

subi sp, sp, 4stw r4, 0(sp)ldwio r4, 4(r6)andhi r4, r4, 0xffffbeq r4, r0, END_PUT

stwio r5, 0(r6)END_PUT:

ldw r4, 0(sp)addi sp, sp, 4ret

.end

Kt qu: c thhin trn Hnh 6.8 v 6.9.


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Thc tp hthng nhng

VI.8


Hnh 6.9Ca sTerminal

Bi tp 4:

JTAG UART ch%nhp k tnhhai bi bp trn l khng hiu qudo lng ph th%igian cho vic ch%c thanh ghi ca n xc nh trng thi UART. Nu xc nh ti


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Thc tp hthng nhng

VI.9

th%i im k tc trong thanh ghi th tc ng ng kn hiu sut ca chng trnh.Thay v ch% nhp k t, c th s dng c ch ng!t, cho php b x l lm cng vic

khc trong th%i gian ch%i thao tc xut nhp.To ra mt phc vng!t c cc k tnhn bi JTAG UART t"host computer.

Ti vtr phc vng!t c a ch0x20, bi v y l vtr mc nh xl ngoi lcla chn bi hthng SOPC Builder. a chngoi lstrli trong thanh ghi ea v phigim i 4 cho ng!t ngoi.

Nios II c thanh ghi iu khin ctl3, c+ng c gi l ienable (cho php ng!t trnnn ring bit). Ch , hthng to ra bi tp u tin lc ta c gi trca ng!t bngkhng, khi thanh ghi iu khin ctl3 c a ln 1 th lc ny cho php ng!t JTAGUART. Ngoi ra , thanh ghi iu khin ctl0 (gi l thanh ghi trng thi) khi sdng cn

phi set ln 1 v b x l cho php ng!t bit (thit lp ln 1 nu mun thc hin ng!tngoi).

Phn gi thc hin sau:

- To mt phc vng!t oc k tt"JTAG UART:- Phc vng!t phi t ti a chbnh0x20.- cho php ng!t, gi trph hp phi c ghi vo thanh ghi Control ca JTAG

UART v thanh ghi ctl0, ctl3 ca Nios II.- Trong phc vng!t, sdng phng php nhn cc k tt"host computer hin

thcc k ttrong ca sthit bu cui ca chng trnh Altera ProgramMonitor.

Hon thnh, bin dch, np v chy chng trnh sau:


.text

.org 0x20ISR:

rdctl et, ctl4beq et, r0, SKIP_EA_DECsubi ea, ea, 4

SKIP_EA_DEC:

/*Thtc ngtEND:

eret.global _start

_start:/*Vit lnh cho php ngt chng trnh./*Vit lnh chng trnh chnh.

LOOP:br LOOP

.end


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Thc tp hthng nhng

VI.10

Nu chng trnh ca bn chy ln u thc hin khng ng cng vic th bnphi tm l$i v sa l$i. Chng trnh Altera Program Monitor c h$trtnh n'ng sa l$i

bng cch chy t"ng bc (step), cho php ng%i dng quan st kt quthc thi ca t"nglnh v ni dung cc thanh ghi ca Nios II. Tuy nhin, phng php ny khng thsdng khi lin quan ti ng!t, v ng!t sc tng v hiu ha khi chy t"ng bc thngqua chng trnh. V vy, trong tr%ng hp chng trnh c sdng ng!t ta phi dngim ng!t (breakpoint) trgip g0ri.

C+ng lu rng ng!t stng v hiu ha khi thc hin ng!t lp i lp li, iuny c ngh,a rng nu mt sng dng yu cu ng!t lng nhau, cc ng!t sphi c sdng th%ng xuyn gin on.


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Thc tp Hthng nhng Bi tp thc tp 7

Lp trnh cho NIOS II sdng ngn ngC

Trong bi ny hng dn cch to v lp trnh cho Board DE2 sdng ngn ngC. V dtrong bi sdng giao tip I/O hin thsthay i ca switch ln led xanh tng ng.

1. Gii thiu:

Skhi cc thnh phn c sdng trong th nghim thhin trong Hnh 7.1.

Hnh 7.1: Cc thnh phn sdng trong lab7

Chng ta sdng 8 switch (t0 n 7) nhp ng vo, 8 led xanh (t0 n 7) hin

thcc gi trnhp vo tswitch tng ng ra led xanh.

Trong project ny chng ta sthc hinto mt hthng SOPC bng cch sdng SOPC Builder.

Hthng SOPC ny sc tp ra bng file Verilog HDL.

2. Cc bc thc hin:

u tin chng ta sto mt project trn phn mm Altera Quatus II 10.1:

- Vo File\New Project Wizard Chn thu mc cha project v tn project


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Hnh 7.2: To project mi

Chn chip Cyclone II EP2C35F672C6 nhHnh 7.3.

Hnh 7.3:Chn chip xl.

Trong ca sca project Lab7, chn cng cSOPC Builder tin hnh to mt hthng SOPC.

t tn l nios_sys v chn ngn ngl Verilog.

Hnh 7.4: To hthng phn cng

To mt h thng SOPC n gin bao gm: CPU(Nios II Processor), RAM( On-chip

Memory), JTAG UART, System ID, PIO Hnh 7.5.

CPU (Nios II Processor): bx l trunng tm, iu khin hot ng ca h thng. Cu

hnh Nios II/s.

RAM (On-chip Memory): cu hnh 32k.

Giao thc PIO sthit k2 kt ni: 1 u vo 8 bit (switch), 1 u ra 8 bit (led xanh).

JTAG UART: kt ni PC vi Board DEII, mc nh.

System ID: Xc nh cu hnh phn cng thch hp.


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Hnh 7.5: Cu hnh phn cng

Sau khi chn xong cc thnh phn cn thit cho hthng, vo System/Auto-Assign Base

Addresses t a ch! nn cho module. Ch gn b nh vo Reset Vector v Exception

Vector Hnh 7.6.

Hnh 7.6.

Sau khi hon tt vic to phn cng n vo Gernerate to tp tin m ththng.

Gn chn cho hthng:

Trong ca sproject chn File\New chn Block Diagram\Sche-matic xut hin ca sgn chn

hthng. Gn cc chn tng ng nhHnh 7.7.

Hnh 7.7

Vo Assingnments/Import Assignments dn tp tin DE2_pin_assign-ments.csv vo mc File

name dxc nh chn cthng vi CLOCK_50, KEY[0], SW[7..0] v LEDG[7..0].

Sau n Run tin hnh bin dch, nu xy ra l"i kim tra li v sa l"i.

Tin hnh np xung Board DE2 bng cch n vo . Kt qu np thnh cng c th hin

trong Hnh 7.8.

Hnh 7.8: Np xung thnh cng.

Sau khi np thnh cng hthng phn cng xung Board DE2, ta sdng gi phn mm Nios II

Software Builder Tool for Eclipse vit chng trnh ng dng bng ngn ngC cho hthng

phn cng thit k.


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Vit chng trnh ng dng cho hthng phn cng:

Tr#li ca sAltera SOPC Builder chon Nios II Software Build Tools for Eclipse

Hnh 7. 9:

Hnh 7.9: Nios II Software Build Tools for EclipseChn vtr lu phn mm ng dng Hnh 7.10:

Hnh 7.10: Ca sworkspace.

To project mi, vo File\New\Nios II Application and BSP form temple Hnh 7.11.

Hnh 7.11: to ng dng mi.


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Trong ca shin ln chn $ng dn n file nios_sys.sopcinfo trong SOPC Information File

name, t tn project l lab7 v chn Templates l Hello world small Hnh 7.11.

Hnh 7.11: to project Eclipse mi.

Click phi vo lab7_bsp[nios_sys] chn Properties\Nios II BSP properties v thit t nhhnh

Hnh 7.12: Thit lp Properties cho Lab7_bsp.


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Tr#li thmc Lab7, vo file hello_world_small.c v nh on code sau thay thcho chng

trnh c s%n.

/*C application example

*/

#include

#include

#include

int main()

{

int status;

printf("Beginning.\n");

while (1)

{

status = IORD_8DIRECT(0x00011000, 0x0);

IOWR_8DIRECT(0x00011010, 0x0, status);}

return 0;

}

Hnh 7.13:C language code to control the LEDs

Click phi vo Thmc Lab7 n Build Project.


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Bin dich chng trnh:

Click chut phi vo Lab7\Run as\Run Configurations . Hnh 7.14.

Hnh 7.14.

Click p vo Nios II Hardware to New_configurations, chn tab Target Connection, mc

System ID check Ignore mismatched ID v Ignore mismatched system timestamp sau Apply,

Run Hnh7.15.

Hnh 7.15: ca schy chng trnh.


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Cc nh chp mn hnh Lab 7 (c ln)


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