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HD EIE 42075 88M -108MHz Phase Lock Loop FREQUENCY SYNTHSIZER WONG TANG PAAI DILLIAN 01111911D WONG WAI TING KENNETH 01901021D. Content Introduction Process Example Difficulties Problem Solving Achievement Improvement. Introduction. VHF phase Lock Loop frequency synthesizer - PowerPoint PPT Presentation
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1
HD EIE 42075
88M -108MHz Phase Lock Loop FREQUENCY SYNTHSIZER
WONG TANG PAAI DILLIAN 01111911D
WONG WAI TING KENNETH 01901021D
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Content
1. Introduction
2. Process
3. Example
4. Difficulties
5. Problem Solving
6. Achievement
7. Improvement
3
Introduction
4
VHF phase Lock Loop frequency synthesizer
Use the feedback and frequency comparator, to detect input frequency and send an error signal to request the change of frequency.
When the input frequency is appropriate, the error signal will goes stables, and the frequency is locked.
The frequency is actually generated by Voltage Control Oscillator.
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LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
Reference frequency
RC tank circuit
Change the phase input into
DC offsetVariable
Register R, N
~V
~f
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Process
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8051 Programming
Voltage Control Oscillator
Low Pass Filter
Frequency synthesizer
Phase Lock Loop
8
Example
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LPF
VCO & Buffer
8051
÷ R=?
÷ N=?
Comparator
12MHz
R=120,N=1000
~V
~f
10
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
12MHz
100kHz
10V
105.8MHz
105.8kHz
ΔΦ 1
11
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
12MHz
100kHz
8V
103.8MHz
103.8kHz
ΔΦ 2
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LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
12MHz
100kHz
6V
101MHz
101kHz
ΔΦ 3
13
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
12MHz
100kHz
5.5V
99.5MHz
99.5kHz
ΔΦ 4
14
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1000
Comparator
12MHz
100kHz
5.9V
100MHz
100kHz
ΔΦ 5
15
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1050
Comparator
12MHz
100kHz
5.9V
100MHz
95.2kHz
ΔΦ 5
R=120,N=1050
16
LPF
VCO & Buffer
8051
÷ R=120
÷ N=1050
Comparator
12MHz
100kHz
8.5V
105MHz
100kHz
ΔΦ 6
17
Difficulties
18
Programming
Parasitic
Capacitance
Oscillation
Wiring
Grounding
Connection
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Grounding is the key parameter for determining the performance of PLL frequency synthesizer. If the grounding is handled inappropriate or not well enough for some critical point, some ac noise signal will be superimposed on the output signal, or modulate output signal with fm signal ruining the phase noise performance.
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Problem Solving
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To minimize the noise effects, we should place a regular or an ac short circuit capacitor near the critical point, like supply power of chip. The ac fluctuation dual to current drop must be eliminated or at least minimized, we can ac grounding it immediately, making the wire as short as possible to minimize the antenna effect. Bold wire should be used to reduce the resistance, or use one ground plane to reduce the resistance with lesser complexity.
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The feedback path is as short as possible
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Regulator place a regular near the supply power of chip.
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8.8 Grounding for chip
place an ac short circuit capacitor near the critical point, like supply power of chip.
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Use bold wire to reduce the resistance
Each component will not influence each other, the fluctuation will not superimposed
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Achievement
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Technical Specification
Frequency Range 88M-108MHz
Frequency Error ±6KHz
Channel Spacing 100KHz
Output Power -12dB
Lock time 10ms
Operating Voltage 20V
Operating Current 28mA
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Center frequency = 100MHz, Span=100kHz
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Center frequency = 108MHz, Span=100kHz
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Center frequency = 108MHz, Span=200kHz
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4.6 Linearity
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35
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Improvement
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107MHz Control Voltage
100MHz Control Voltage
Transient response of LPF
(5/10)x 100 % = 50 % overshoot
15V
10V
40
50 % overshoot
10~20 % overshoot
By Reducing the feedback gain of LPF