Confidential

SK hynix Inc. October 2014

© 2014 SK hynix Inc. This material is proprietary of SK hynix Inc. and subject to change without notice.

HBM: Memory Solution for High Performance Processors Kevin Tran and June Ahn

Agenda

“Completion of HBM1 Qualification” Announcement

Landscape of memory solution challenges

Why HBM is the suitable solution

HBM Architecture Review

Conclusion

SK hynix achieved Customer Qualification Level samples in Sep’14

Achievement of HBM1 Qualification

SK hynix TSV chronicle SK hynix World-First HBM Products

‘08 4Gb Flash

‘10 4Gb DRAM DDP-WLP

‘11 16Gb DRAM

9MCP

‘11 16/ 32GB

DIMM

‘11 4hi KGSD

WIO

’13 5mKGSD

HBM (Bottom View) (Top View ) (Section View )

Worldwide first HBM provider

Customer Qualification Samples shipping today

Volume production begins Q1’15

HBM2 design wins in progress with major SoCs

in multiple markets

Agenda

“Completion of HBM1 Qualification” Announcement

Landscape of memory solution challenges

Why HBM is the suitable solution

HBM Architecture Review

Conclusion

All DRAMs expect to face immense bandwidth requirement

Challenges#1) Bandwidth

• DRAM transistor and tester limit over 10Gbps

• Trade off with power consumption

• Severe die overhead

Gb/s/pin IO

GDDR5 7.0 X32

DDR4 3.2 X16

LPDDR4 4.2 X32

Data Rate/Pin Challenges

Density has increased by 1000X over the past two decades, Latency has decreased only by 56%

Challenges#2) Density/Latency

Density Mode tRC(ns)

1992 4Mb Cache DRAM 110

2002 256Mb DDR 6X

2003 1Gb DDR2 5X

2012 4Gb DDR3 4X~5X

2014 8Gb DDR4 4X

• Capacity / Cost Limitation

• DRAM Scaling Challenges

• Severe die overhead increase

Density/Latency Challenges

Reducing power and increasing performance are always trade-offs

Challenges#3) Power Efficiency

Power

Perf

orm

ance

• Trade-off between performance and power

Nor

mal

ized

DDR2

56 =

100

%

Power Efficiency Challenges

System level board design challenges for # of DRAM

Challenges#4) Form Factor

TSV is a revolutionary technology enabling next generation memories

Revolutionary Changes with TSV memories

▼ High Speed

▼ Lower Power

▼ High Density

▼ Small Form Factor

Agenda

“Completion of HBM1 Qualification” Announcement

Landscape of memory solution challenges

Why HBM is the suitable solution

HBM Architecture Review

Conclusion

Each application has different memory requirement, but most common are high bandwidth and density based on real time random operation.

General Memory Requirements

Graphics Networking

HPC

Datacenter

Real time Based

Random Operation

Bandwidth Density Power

Bandwidth Power Latency

Density Bandwidth Power Latency

Bandwidth Latency Power

Lower speed/pin and Cio reduce power consumption by 42% compared to GDDR5

Low Power

Pseudo channel improves tFAW by 60% compared to DDR4

Low Latency

1GB HBM package size is smaller than 1 tablet of aspirin

Small Form Factor

DDR4

HBM

DDR3

X37 bigger

X44 bigger

SoC

HBM 1GB

HBM 1GB

HBM 1GB

HBM 1GB

vs.

PKG Size 2.5D stacking size

X1

SiP enhances memory channel conditions

Silicon in Package

Items DRAM (Off-chip)

SiP (2.5D)

Physical dimension very large small

Signal Distance long short

Signal Loading high low

Driver Strength large small

IO Speed /Pin high low

Termination need no

Power Consumption high Low

Long Distance Loading, Power , C&R ↑

Speed, tDV ↓

Memory Channel Conditions DRAM vs. SiP

DRAM SiP

Agenda

“Completion of HBM1 Qualification” Announcement

Landscape of memory solution challenges

Why HBM is the suitable solution

HBM Architecture Review

Conclusion

TSV is the underlying technology for 3D Stack (High Density / Small size PKG / High speed)

Through Silicon Via - TSV

Die Pad

Die #2

Die #1

Bond wire

PKG Pad

PKG Pad

TSV

Die Pad

< Wire bonding PKG > < TSV PKG >

System-in-Package implementation with KGSD*

HBM 2.5D SiP Structure

FBGA

PHY TSV DA ball

DRAM Slice

DRAM Slice

DRAM Slice

DRAM Slice

Interposer

SoC

KGSD

PHY

HBM in 2.5D SiP

Side

Mol

ding

Side

Mol

ding

* KGSD (Known Good Stacked Die)

3D Memory(HBM)

Base die Silicon die

PKG Substrate

(Source : esilicon)

HBM Overall specification

Base Die

Interposer

HBM1 2Gb Density per DRAM die

1Gbps speed /pin

128GB/s Bandwidth

4 Hi Stack (1GB)

HBM2 8Gb per DRAM die

2Gbps speed/pin

256GBps Bandwidth/Stack

4/8 Hi Stack (4GB/8GB)

x1024 IO

1.2V VDD

KGSD w/ μBump

4 Core DRAM + 1 Base logic die (Chip on Wafer)

HBM Architecture Overview

DA POWER/TSV PHY

Core Die 0

Core Die 1

Core Die 2

Core Die 3

Base Logic Die

128 I/O

Microbump array

Probe PAD(Microbump

depopulated)

128 I/O

1024 TSV I/O

B3 B1

B2 B0

B7 B5

B6 B4

B3 B1

B2 B0

B7 B5

B6 B4

Items Target # of Stack 4(Core) + 1(Base)

Ch./Slice 2

Total Ch. for KGSD 8

IO/Ch. 128

Total IO/KGSD 1024(=128 x 8)

Address/CMD Dual CMD

Data Rate DDR

[1] D.U Lee, SK hynix, ISSCC 2014

Each HBM die has 2channels 1 channel consists of 128 TSV I/O with 2n prefetch

HBM Core Architecture

[2] D.U Lee, SK hynix, ISSCC 2014

B0 B1

YCTRL YCTRL

B2 B3

XCTR

LXC

TRL

C

B0 B1

YCTRL YCTRL

B2 B3XC

TRL

XCTR

L

C

B4 B5

YCTRL YCTRL

B6 B7

XCTR

LXC

TRL

C

B4 B5

YCTRL YCTRL

B6 B7

XCTR

LXC

TRL

C

DWORD 032 I/O

DWORD 132 I/O AWORD DWORD 2

32 I/ODWORD 3

32 I/O

B0 B1

YCTRL YCTRL

B2 B3

XCTR

LXC

TRL

C

B0 B1

YCTRL YCTRL

B2 B3

XCTR

LXC

TRL

C

B4 B5

YCTRL YCTRL

B6 B7

XCTR

LXC

TRL

C

B4 B5

YCTRL YCTRL

B6 B7

XCTR

LXC

TRL

C

DWORD 032 I/O

DWORD 132 I/O AWORD DWORD 2

32 I/ODWORD 3

32 I/O

CH-Left CH-Right

1 bank : 2 sub-banks(64Mb) non-shared I/O between sub-banks

Base die consists of 3 Areas – PHY, TSV, Test Port Area

HBM Base Die Architecture

HBM ballout area 6,050x3,264 μm

[3] D.U Lee, SK hynix, ISSCC 2014

• HBM is comprised of 8ch (2Channel/die) with 128DQs per channel. • Each channel(CH) consists of 2 Pseudo Channel(PS). Only BL4 is supported.

Pseudo Channel Concept

CH-0

B0 B1

B2 B3

B4 B5

B6 B7

64I/O

B0 B1

B2 B3

B4 B5

B6 B7

64I/OADDCMD

PS-CH0 PS-CH1CH-1

B0 B1

B2 B3

B4 B5

B6 B7

64I/O

B0 B1

B2 B3

B4 B5

B6 B7

64I/OADDCMD

PS-CH0 PS-CH1

CH-2 CH-3CH-4 CH-5

CH-6 CH-7

(Note : Pseudo channel is only applicable to HBM2)

Each pseudo channel share AWORD, but has separated banks & independent 64 I/Os

Pseudo Channel Mode

Channel # CMD

Channel # ACT#-RD#

128DQ D0 128

D1 128

D2 128

D3 128

16Bank / CH

Channel # CMD

CH #_PC0 ACT#0-RD#0

64DQ D0 64

D1 64

D2 64

D3 64

CH #_PC1 ACT#1-RD#1

64DQ D0 64

D1 64

D2 64

D3 64

16Bank/PC1

16Bank/PC0

• For Legacy Mode, Each channel has 2KB page size • Restriction of Gapless Bank Activation by tFAW(4 activate window) tFAW=30ns > 4Bank*tRRD=16ns Lower efficiency of Band Width

• Suppose tCK=2ns, tFAW=30ns, tRRD=4ns

Restriction of tFAW in Legacy mode

Gap

Gap

Gap

• Pseudo channel has reduced page size compared to Legacy mode. : 2KB 1KB • Lower Active Power(IDD0) by 1K Page size • Define tEAW (1KB x 8 ACT) instead of tFAW (2KB x 4 ACT) • Bandwidth improvement by more Activations during tFAW

Benefit of Pseudo Channel

Memory Die

Logic Layer Host I/F + Memory I/F + Base Logic/IP Block

Base Die Customization – Future HBM Concept

27

Customization to meet various requirements

Overcome Memory Scaling

- Timing - Refresh

- Parallel-to-Serial(P2S)/S2P - JTAG, PMBIST - Configuration Registers - Error Handling - …

Agenda

“HBM1 Qualification Sample” Announcement

Landscape of memory solution challenges

Why HBM is the suitable solution

HBM Architecture Review

Conclusion

Complicated TSV Ecosystem requires close collaboration

among all stakeholders

TSV Ecosystem

OSATs

Set Makers

IP Enablers

Memory Vendors

SiP Assy’ & Test

SoC & Interposer Business Model for SiP

PHY & MC IP Controller IP

KGSD/KGD

Foundries

Conclusion

HBM enables new memory subsystem architecture for Next Generation high performance processors. SK hynix is the leader in HBM technology

SK hynix HBM1 Customer Qualification samples are shipping

HBM addresses the major memory requirements with lower power, lower

latency, and smaller form factor.

HBM2 Pseudo channel improves bus utilization and system performance

Thank You