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CS 4120 Hardware Description Languages and Synthesis Homework 7: MIPS Microprocessor (50 points)

Overview

In this project, you will implement an MIPS pipeline microprocessor. The microprocessor has

five stages: IF (instruction fetch), ID (instruction decode/register read), EX (execution), MEM

(data memory read/write) and WB (register write back). Do implement pipeline, but do not

worry about data hazard or control hazard.

Reference

For more information on the MIPS processor, see chapters 3 to 6 of "Computer Organization &

Design - The Hardware/Software Interface" by David A. Patterson and John L. Hennessy.

Instruction Set

The following instructions need to be implemented. For instruction format details, see the MIPS

handout.

J Unconditional jump

BEQ Branch on equal

LW Load word (not byte!) from memory

SW Store word (not byte!) to memory

ADDI Addition Immediate

ADD Addition

SUB Subtraction

AND Logical AND

SLL Shift left logical

NOP No operation

If an instruction contains all 0, it is considered as an NOP (no operation). No action is taken for

an NOP, and PC increments to the next instruction.

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Load Memory

You need to initialize the instruction memory and data memory. The following is the Verilog

code that loads file IMEM.dat to the instruction memory imem:

module load_memory_example();

reg [0:31] imem[0:49];

initial // load imem

$readmemh("IMEM.dat", imem);

initial // show content

$monitor($time,, "imem[0]=%h imem[1]=%h", imem[0], imem[1]);

endmodule

where IMEM.dat holds

01234567

89ABCEDF

the result will be

0 imem[0]=01234567 imem[1]=89abcdef

Initialization and Output

In order for the TA to grade your design, your design must meet the following requirements:

• Initialize your memories with all 0's, and then load IMEM.dat to the instruction memory

(imem) and DMEM.dat to the data memory (dmem). Don't use a different file name.

• Initialize your PC to be 0.

• Stop your simulation after 50 cycles.

Suggestions

Since the MIPS processor is pipelined, each instruction is completed in five stages, and each

stage is completed in one clock cycle. The function units or modules in the processor can be

organized as follows:

• A top module that instantiates all the components.

• Instruction memory. This is also the first stage.

• Register file. This is part of the second stage, and also the fifth stage.

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• Control unit.

• Arithmetic and logic unit (ALU). This is the third stage.

• Data memory. This is the fourth stage.

• Four interface modules for the modules of the 5 stages.

• Other parts such as MUX's, PC, and address adders.

Simplifications

You can assume both the instruction memory and the data memory are of size 50 words, each 32

bits. You can also assume the register file contains only 8 registers $0, $1, ..., $7, each 32 bits.

Register $0 always contains 0. You can test each module by applying particular inputs to see

whether the outputs of that module are correct. After you finish the whole project, you can test

the whole design by including the data memory and instruction memory in a test bench and

preload the memory with a test program.

Remarks

1. The instruction and data memories are word (4 bytes) accessible. Whenever instructions or

data are accessed by an address, a word (not a byte) is fetched from the imem or dmem,

respectively.

For example,

The first 4 instructions in imem and the PC for them are

00000000 (Instruction 1) PC = 0 8C010000 (Instruction 2) PC = 1 8C020001 (Instruction 3) PC = 2 8C030002 (Instruction 4) PC = 3

The first 4 data values in dmem and address for them are

0000001 (Data 1) Address = 0 0000002 (Data 2) Address = 1 0000003 (Data 3) Address = 2 0000004 (Data 4) Address = 3

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2. As the instruction memory is word accessible, PC has to incremented by 1 and not by 4 every

cycle.

3. For implementing “SLL” (shift left) and “J” (jump) instructions, you have to make some

small changes to the MIPS architecture shown in the handout.

4. You have to display all the 8 registers and the first 8 locations of the data memory

whenever they change.

5. The jump instruction should use absolute addressing. So the jump offset would give the new

PC. The branch instruction has to use relative addressing. So the present PC added to the

branch offset would give the new PC.

6. You do not have to worry about overflows in the ALU.

Report Requirements

The homework is due by noon, 05/22/2003. You need to submit the following items:

1. A brief description of your design, including the module hierarchy and the function of

each module.

2. Your Verilog code.

3. Your testbench and simulation result for the given test program. (You can download

the test program from the course website.)

Please compress all of your files into one file. Name the file as “YourStudentID_hw7.zip”

(where YourStudentID is your student ID, e.g., “g914380”), and email it to

tacs4120@nthucad.cs.nthu.edu.tw. Please note that the due time is strictly followed. (No late

submission will be accepted.)