System Modeling Lab 3

1 | P a g e Muhammad Amir Yousaf Najeem Lawal

Laboratory 3: Hardware co-simulation with Xilinx System Generator

Goals:

This lab aims to give practical experience with Xilinx Blockset and System Generator in Simulink.

System Generator is a DSP design tool that enables the use of The Mathworks model-based design

environment Simulink for FPGA design......

In this lab you will co-simulate an FPGA design using Xilinx System Generator in Simulink. ......

Hardware co-simulation

Hardware co-simulation with Xilinx System Generator makes it possible to incorporate a design in an

FPGA directly into a Simulink simulation....

Useful readings before you start

i. User Guide: System Generator for DSP (chapter 3)

ii. Getting Started Guide: System Generator for DSP (Introduction)

iii. Use Simulink Help to read the detailed description of the blocks you are using in your model.

This description gives you useful information about the blocks scope and functionality and

important parameters to set for suitable data flow, latency and selection of functionality etc.

For example a block, 5x5Filter that is available in Xilinx Refernce Blockset Imaging.

The help menu show the description as:

Also the block parameters:

These details also help in setting other parameters for overall system to run. For example after reading

the description about 5x5filter and Vertex2 5 Line Buffer you can set the Simulink System

Period in System Generators options window.

System Modeling Lab 3

2 | P a g e Muhammad Amir Yousaf Najeem Lawal

Documents are uploaded on the course web page along with this lab instruction document.

Lab Assignment

The block diagram is an image of model for Edge-detection system using Sobel algorithm. The system

is modelled using Xilinx System Generator in Simulink.

The system reads the image from MATLAB workspace; pass it to Xilinx Blockset and where the edge

detection operation is performed over the image data and the result is handed over back to MATLAB

workspace.

System Modeling Lab 3

3 | P a g e Muhammad Amir Yousaf Najeem Lawal

Callback functions can be used to do the pre and post processing on image and to display the input and

output images.

a) Make a system model that read the image data from the workspace or from file, perform Sobel

edge detection over it using Xilinx Blockset and stream the result back to workspace or show

it with image viewer.

Use call back functions for pre and post processing of images, same as they wre used in Lab2.

b) Generate a hardware co-simulation block for the FPGA in Nexys2 borad using Sytem

Generator . The hardware co-simulation block loads the Xilinx Blocksets design in the

FPGA.1

c) Make a new model that read the image from the workspace or from file same as task-a, stream

the image data to hw- co-simulation block that loops the data through the FPGA where the

(Sobel Edge Detection) algorithm is applied over it. The result should be sent back to

Simulink.

Note: New compilation target.pdf explains the steps to add a new target for hardware co simulation.

Report Submission:

Remember that for higher grades you must have explained your work comprehensively and

pedagogically. It is always better to present your understanding about how the lab work is helpful in

solving the problems in research and development in electronics.

Write about the tools e.g. System Generator and Xilinx tools you learned in the lab and what else

they can be used for.

After you perform in the lab tasks, demonstrate them to lab teachers and send your reports to

amir.yousaf@miun.se before 9th of May.

Useful Links:

http://www.mathworks.com/help/pdf_doc/simulink/sl_gs.pdf

Digilent Nexys 2 board: http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2