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Hardware Accelerated SDR Platform for Adaptive Air Interfaces Tarik Kazaz, Christophe Van Praet, Merima Kulin, Pieter Willemen, Ingrid Moerman

Overview  

§  Introduc)on  

§  Common  SDR  approach  

§  Propposed  approach  

§  The  future  of  compu)ng  

§  Hardware  accelerated  SDR  

§  Example  Use  case  

Introduc/on  

RF Plane

Radio Processing Plane

Access Plane Controller  

Controller  

APP   APP   APP  

Control  Plane  

Control  Protocols  

Data  Plane  

Common  SDR  approach  

§  Intensive  signal  processing  is  done  in  host  PC  §  Real  &me  processing  is  hard  to  achieve  §  Significant  power  and  space  consump)on  (no  portability)  

             

§  FPGA  is  seriously  underu&lized!  

USRP (N Series)

Host PC

?

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

IFFT   P/S  &    add  CP  

Pulse  shaping  

DAC  &  RF  

Transmitter

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

IFFT   P/S  &    add  CP  

Pulse  shaping  

Baseband processing DAC  &  RF  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

IFFT   P/S  &    add  CP  

Pulse  shaping  

Baseband processing DAC  &  RF  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

IFFT   P/S  &    add  CP  

Pulse  shaping  

Baseband processing DAC  &  RF  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

P/S  &    add  CP  

Baseband processing DAC  &  RF  IFFT   Pulse  

shaping  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

Baseband processing DAC  &  RF  IFFT   Pulse  

shaping  P/S  &    add  CP  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

P/S  &    add  CP  

Baseband processing DAC  &  RF  IFFT   Pulse  

shaping  

Common  SDR  approach  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

P/S  &    add  CP  

Baseband processing DAC  &  RF  IFFT   Pulse  

shaping  

?

Proposed  approach  –  Tx  side  

Coding  &  Interleaving  

QAM  mapping  

Pilot  Inser/on  &  S/P  

P/S  &    add  CP  

DAC  &  RF  IFFT   Pulse  

shaping  

Proposed  approach  –  Rx  side  

Timing  and  Freq  Sync  ADC  RF  

Rx  

CP  rem

oval  

P/S   FFT   S/P  Equalizer  QAM          de-­‐mapping  

de-­‐interleaving  de-­‐coding  

Current  Pure  SoKware  Compu/ng  approach  

Sources: Marr et al., “Scaling Energy Per Operation via an Asynchronous Pipeline”; Koomey et al., “Implications of Historical Trends in the Electrical Efficiency of Computing”

Future  compu/ng  –  Hybrid  SoKware  &  Hardware  approach    

Source: Qualcomm website (01.17.2015)

Future  compu/ng  –  Hybrid  SoKware  &  Hardware  approach  (1)    

Source: Intel website (01.17.2015)

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (1)  

Xilinx Zynq Dual Core ARM Cortex A9

GNU Radio FPGA Accelerated

Block

Linux Kernel Device Driver

RFNoC Router

FPGA Accelerator FPGA Fabric

§  SW  components  §  GnuRadio  with  HW  accelera/on  capabili/es  –  RFNoC  

§  Reconfigura/on  Capabili/es  

§  SW  –  HW  interface  

§  shared  memory  

§  separate  control  and  data  plane  interfaces  

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (2)  

§  Real  /me  re-­‐configurability  §  Par&al  reconfigura&on  via  PCAP  

Configuration Port or ICAP

Configuration Port Full

Bit File

Partial Bit Files

Function B1

Function C1 Function C

Function B

Function A

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (3)  

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (4)  

§  This  concept  enables  §  Offload  of  SW  Radio  blocks  to  FPGA  

§  Frees  up  processor  to  

perform  other  tasks  

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (5)  

§  This  concept  enables  §  Offload  of  SW  Radio  blocks  to  FPGA  

§  Whole  SDR  system  should  fit  on  one  board  

 

§  Frees  processor  to  perform  other  tasks  

Hardware  accelerated  SDR  plaQorm  on  top  of  Hybrid  FPGA  (6)  

Example  Scenario  

§  Different  applica/ons  –  different  wireless  standards  

§  Our  plaLorm  should  support  various  exis&ng  and  future  emerging  wireless  technologies  at  same  )me    à      IoT  HUB

IoT-CUBE HUB

Internet Repository

of SDR library and HW ACC

802.11g device 802.11ac

device

802.15.4 device

BLE device

802.11ah

xyz device

§  Download  SDR  packages  from  

cloud  à  Air  Interface  as  a  Service  

Questions?

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