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Memory Devices

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Memory Memory –– ChallengesChallenges

Issues & challenges in memory design:Issues & challenges in memory design:CostCostPerformancePerformancePowerPowerScalabilityScalability

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Memory Memory -- OverviewOverview

Definitions:Definitions:

RAM RAM –– random access memoryrandom access memoryDRAM DRAM –– dynamic RAMdynamic RAMSRAM SRAM –– static RAMstatic RAMVolatile memory Volatile memory –– the RAMs lose data the RAMs lose data when power is removedwhen power is removedNonvolatile memory Nonvolatile memory –– retain data when retain data when the power is offthe power is offISP ISP –– inin--system programmablesystem programmable

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Static RAM (SRAM)Static RAM (SRAM)•• FunctionalityFunctionality

A word, once written at a location, A word, once written at a location, remains stored as long as power is on, remains stored as long as power is on, unless the same location is written to unless the same location is written to againagain

•• Basic structure and operationsBasic structure and operationsRead operation:Read operation: while the address is while the address is asserted, and CS (chip select) and OE asserted, and CS (chip select) and OE (output enable) are asserted, DOUT (output enable) are asserted, DOUT are read outare read outWrite operation:Write operation: while the address while the address and CS/WE are asserted (write and CS/WE are asserted (write enable), a data word placed on DIN enable), a data word placed on DIN (data input) is written into the memory(data input) is written into the memory

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SRAM SRAM –– Timing (1)Timing (1)Read operation timing parametersRead operation timing parametersttAAAA –– access time from addressaccess time from addressttACSACS –– access time from chip selectaccess time from chip selectttOEOE –– outputoutput--enable timeenable timettOZOZ –– outputoutput--disable timedisable timettOHOH –– outputoutput--hold timehold time

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Write operation timing parametersWrite operation timing parametersttASAS –– address setup time before writeaddress setup time before writettAHAH –– address hold time after writeaddress hold time after writettCSWCSW –– chipchip--select setup time before end of writeselect setup time before end of writettWPWP –– write pulse widthwrite pulse widthttDSDS –– data setup time before end of writedata setup time before end of writettDHDH –– data hold time after end of writedata hold time after end of write

SRAM SRAM –– Timing (2)Timing (2)

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Synchronous SRAMSynchronous SRAM

•• Synchronous Synchronous Clocked interfaces for Clocked interfaces for control, address and datacontrol, address and data

•• Internal structureInternal structureEdgeEdge--triggered registers triggered registers

AREG for addressAREG for addressCREG for controlCREG for controlINREG for input dataINREG for input dataOUTREG for output dataOUTREG for output data

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Dynamic RAM (DRAM)Dynamic RAM (DRAM)

•• Operation of One Bit CellOperation of One Bit CellWrite operation:Write operation: Set word line HIGH; Set word line HIGH; To store 1, set bit line HIGH, charging To store 1, set bit line HIGH, charging the capacitor; To store 0, set LOW on the the capacitor; To store 0, set LOW on the bit line, discharging the capacitorbit line, discharging the capacitorRead operation:Read operation: Set word line HIGH; Set word line HIGH; Bit line is precharged halfway between Bit line is precharged halfway between HIGH and LOW; The capacitor voltage HIGH and LOW; The capacitor voltage pulls the bit line slightly higher or lower; pulls the bit line slightly higher or lower; A sense amplifier detects this small A sense amplifier detects this small change and recovers 1 or 0.change and recovers 1 or 0.

•• Functionality Functionality Periodically refresh the stored data by reading it and then writPeriodically refresh the stored data by reading it and then writing it ing it back, otherwise the data disappearsback, otherwise the data disappears

11--bit storage cellbit storage cell

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DRAM Basic StructureDRAM Basic Structure

Basic one transistor storage cell together with Basic one transistor storage cell together with crosscross--coupled latch sense amplifiercoupled latch sense amplifier

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DRAM DRAM –– RefreshingRefreshingReading destroys the original voltage on the capacitor, so that Reading destroys the original voltage on the capacitor, so that the recovered data must be written back into the cell after the recovered data must be written back into the cell after readingreadingDRAM uses refresh cycles to periodically update memory cellsDRAM uses refresh cycles to periodically update memory cellsSequentially reading the degraded contents of each cell into a Sequentially reading the degraded contents of each cell into a D latch and writing it back to a solid LOW or HIGHD latch and writing it back to a solid LOW or HIGH

Voltage stored in a DRAM cell after writing and refresh operations

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The physical array is square, for example, 64K X 1 containing The physical array is square, for example, 64K X 1 containing 256 X 256 bits256 X 256 bitsOnly 8 multiplexed address inputs, saving pins which are Only 8 multiplexed address inputs, saving pins which are important for compact design of memory systemimportant for compact design of memory systemA complete 16A complete 16--bit address is presented in two steps controlled by bit address is presented in two steps controlled by two signals:two signals:RAS_L RAS_L –– row address stroberow address strobeCAS_L CAS_L –– column address strobecolumn address strobe

DRAM DRAM –– Internal StructureInternal Structure

Internal structure of a 64K X 1 DRAMInternal structure of a 64K X 1 DRAM

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Read operation Read operation Read a selected row into the row latchRead a selected row into the row latchcolumn address is applied and stored in the column address regiscolumn address is applied and stored in the column address register on the ter on the falling edge of CAS_Lfalling edge of CAS_LThe column address is used to select one bit of the read rowThe column address is used to select one bit of the read rowAs long as CAS_L is asserted, a threeAs long as CAS_L is asserted, a three--state pin, DOUT, is outputstate pin, DOUT, is output--enabledenabledAs soon as RAS_L is negated, the entire row is written backAs soon as RAS_L is negated, the entire row is written back

DRAM DRAM –– Timing (1)Timing (1)

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Write operation Write operation WE_L(write enable) must be asserted before CAS_L is asserted to select a write cycle and to disable DOUT for the rest of the cycleonce the selected row is read into the row latch, WE_L also forces the input bit on DIN to be merged into the row latch, in the bit position selected by column addressWhen the row is subsequently written back into the array on the rising edge of RAS_L, it contains a new value in the selected column

DRAM DRAM –– Timing (2)Timing (2)

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DRAM DRAM –– Other Timing TypesOther Timing Types

CASCAS--beforebefore--RAS refresh cycle RAS refresh cycle ReadRead--modifymodify--write cyclewrite cyclePagePage--mode read cyclemode read cyclePagePage--mode write cyclemode write cycle

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Synchronous DRAM (SDRAM)Synchronous DRAM (SDRAM)•• Why synchronous Why synchronous

The conventional RAS/CAS edgeThe conventional RAS/CAS edge--based DRAM can not based DRAM can not run fast and need to meet timing margins when interfacing run fast and need to meet timing margins when interfacing with the rest of the systemwith the rest of the system

•• External signalsExternal signalsCLK: samples an SDRAMCLK: samples an SDRAM’’s control signal and address s control signal and address inputs on the rising edge of a common clock signalinputs on the rising edge of a common clock signalCKE: clock enable signal so that inputs are ignored if CKE: clock enable signal so that inputs are ignored if CKE is not assertedCKE is not assertedRAS_L, CAS_L and WE_L: command wordsRAS_L, CAS_L and WE_L: command wordsHighHigh--order address bits: interpreted as a bank select to order address bits: interpreted as a bank select to indicate which bank a command word applies to indicate which bank a command word applies to

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DRAM DRAM –– Other TypesOther Types

FPM (Fast Page Mode) DRAM FPM (Fast Page Mode) DRAM EDO DRAM (Extended Data Out DRAM)EDO DRAM (Extended Data Out DRAM)RLDRAM (Reduced Latency DRAM)RLDRAM (Reduced Latency DRAM)

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Special Application Memory (1)Special Application Memory (1)•• Video RAM (VRAM)Video RAM (VRAM)

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Special Application Memory (2)Special Application Memory (2)•• DualDual--Port RAMPort RAM

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ReadRead--Only Memory (ROM)Only Memory (ROM)

Mask ROMMask ROMProgrammable ROM (PROM)Programmable ROM (PROM)Erasable programmable ROM (EPROM)Erasable programmable ROM (EPROM)Electrically erasable programmable ROM Electrically erasable programmable ROM (EEPROM)(EEPROM)

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Flash MemoryFlash Memory

Electrically erasable, programmable, Electrically erasable, programmable, and nonvolatileand nonvolatileWrite or erase data in blocksWrite or erase data in blocksMuch faster than EEPROMMuch faster than EEPROM

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Banks and RanksBanks and RanksBank: the entire memory array of individual bit cells is Bank: the entire memory array of individual bit cells is divided into subdivided into sub--arrays called banksarrays called banks•• Banks allow a deviceBanks allow a device’’s memory core to be repaired of s memory core to be repaired of

manufacturing defects by mapping in redundant core manufacturing defects by mapping in redundant core componentscomponents

•• Banks increase performance of a single device by Banks increase performance of a single device by facilitating concurrent operationsfacilitating concurrent operations

Rank: A term that is descriptive of a multichip memory Rank: A term that is descriptive of a multichip memory modulemodule•• A rank is a group of memory chips on a memory module A rank is a group of memory chips on a memory module

that get selected simultaneously and that together form a that get selected simultaneously and that together form a data word width identical to the width of the memory data data word width identical to the width of the memory data busbus

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DDR (Double Data Rate) SDRAMDDR (Double Data Rate) SDRAM

Definition:Definition:DDR SDRAM (double data rate synchronous DRAM) is DDR SDRAM (double data rate synchronous DRAM) is

a type of DRAM that realize twice the data transfer rate of a type of DRAM that realize twice the data transfer rate of conventional SDRAMconventional SDRAM

DDR SDRAM is synchronous DRAM that realizes highDDR SDRAM is synchronous DRAM that realizes high--speed data transfer while adhering to the specifications of speed data transfer while adhering to the specifications of SDRAM as much as possibleSDRAM as much as possible

Differences from SDRAMDifferences from SDRAMFunctions and specificationsFunctions and specificationsCommandsCommandsOperation timingOperation timing

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Difference between DDR and SDR SDRAMDifference between DDR and SDR SDRAM-- Functions and specificationsFunctions and specifications

* * Conventional SDRAM is referred to as SDR SDRAM (single data rateConventional SDRAM is referred to as SDR SDRAM (single data ratesynchronous DRAM)synchronous DRAM)

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Difference between DDR and SDR SDRAMDifference between DDR and SDR SDRAM-- Functions and specifications (Functions and specifications (contcont))

•• Twice data transfer rate is achieved by using 2Twice data transfer rate is achieved by using 2--bit prefetch bit prefetch architecture, with read cycle as example herearchitecture, with read cycle as example here

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Difference between DDR and SDR SDRAMDifference between DDR and SDR SDRAM-- Functions and specifications (Functions and specifications (contcont))

•• ExplanationExplanation of read cycleof read cycle–– 2n bits of data are transferred from the memory cell 2n bits of data are transferred from the memory cell

array to the I/O buffer every clock array to the I/O buffer every clock –– Data transferred to the I/O buffer is output n bits at a Data transferred to the I/O buffer is output n bits at a

time every half clocktime every half clock–– As the internal bus width is twice the external bus As the internal bus width is twice the external bus

width, a data output rate twice the data rate of the width, a data output rate twice the data rate of the internal bus is achievedinternal bus is achieved

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Use of DLL in DDR SDRAMUse of DLL in DDR SDRAM

A fast access time and high operation A fast access time and high operation frequencies are realized by controlling frequencies are realized by controlling and adjusting the time lag between and adjusting the time lag between external clock and internal clockexternal clock and internal clock

DLL (delay locked loop) DLL (delay locked loop) circuit is used in DDR circuit is used in DDR SDRAMSDRAM

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Operation Timing of DDR SDRAM Operation Timing of DDR SDRAM •• Read cycle timingRead cycle timing

•• Write cycle timingWrite cycle timing

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Operation Timing of DDR SDRAM (Operation Timing of DDR SDRAM (contcont))

•• ExplanationExplanation of operation timingof operation timing

-- Command signal READ/WRIT at rising edge of clock (CK)Command signal READ/WRIT at rising edge of clock (CK)-- Data input/output timing employs differential clock (CK and Data input/output timing employs differential clock (CK and

/CK)/CK)-- Data strobe signal (DQS) is adopted to achieve highData strobe signal (DQS) is adopted to achieve high--speed speed

data transfer. DQS is output from the device and received by data transfer. DQS is output from the device and received by the receiver, which adjusts the data (DQ) capture timing using the receiver, which adjusts the data (DQ) capture timing using DQSDQS

-- Data is edgeData is edge--aligned to DQS for read data and centeraligned to DQS for read data and center--aligned aligned for write data. This means that when controller receives read for write data. This means that when controller receives read data from DDR SDRAM, it will internally delay the received data from DDR SDRAM, it will internally delay the received strobe to the center of the received data windowstrobe to the center of the received data window

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FCRAM (Fast Cycle RAM)FCRAM (Fast Cycle RAM)

New technology developed by the Fujitsu CorporationNew technology developed by the Fujitsu CorporationChange the DRAM core itself. The process included Change the DRAM core itself. The process included

pipeline operation and core segmentation with the added pipeline operation and core segmentation with the added benefit of power reductionbenefit of power reduction

Address input can be made in parallel with command Address input can be made in parallel with command input. With this pipelining scheme, itinput. With this pipelining scheme, it’’s possible to start a s possible to start a command operation while a data read or write operation is command operation while a data read or write operation is still in process, resulting in an still in process, resulting in an improvementimprovement of the cycle of the cycle timetime

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FCRAM (FCRAM (contcont))

FCRAM cores are used in three types of FCRAM memory FCRAM cores are used in three types of FCRAM memory devices:devices:

Network FCRAM – FCRAM with a DDR synchronous interface used in networking, graphics, and multimedia

Mobile FCRAM – FCRAM with an asynchronous SRAM interface for mobile phone applications

Consumer FCRAM – FCRAM with a synchronous SDR SDRAM interface for use in consumer applications such as cameras, battery-driven devices, and car navigation systems

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FCRAM (FCRAM (contcont))•• Representative values of Network, Mobile, and Consumer Representative values of Network, Mobile, and Consumer FCRAMFCRAM

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FCRAM (FCRAM (contcont))•• Representative values of Network, Mobile, and Consumer Representative values of Network, Mobile, and Consumer FCRAM (cont)FCRAM (cont)

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SigmaRAMSigmaRAM

Definition and features:Definition and features:A family of SRAM products jointly defined by the

SigmaRAM ConsortiumThe SigmaRAM family consists of devices featuring

common I/O busesDesigned especially for networking applications, the

family of devices features higher speed, new packaging, an improved clocking scheme, multimode operation, and low power

SigmaRAM packaging is also designed for networking

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RLDRAM (Reduced Latency DRAM)RLDRAM (Reduced Latency DRAM)

Definition and features:Definition and features:Codeveloped by Micron Technology and Infineon

TechnologiesIts defining characteristics include

• High density• High bandwidth• Reduced cycle time• SRAM-like access

Ideal for switch and router applications, and also for other high-bandwidth, high-speed, and latency-sensitive applications

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DDR SRAM (DDR SRAM (Double Data Rate SRAM Double Data Rate SRAM –– DDR, DDRII SRAMDDR, DDRII SRAM))

•• DSRAM has evolved over time to exhibit higher clock DSRAM has evolved over time to exhibit higher clock frequencies, shorter cycle times, and higher densitiesfrequencies, shorter cycle times, and higher densities

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DDR SRAM (DDR SRAM (contcont))•• Feature comparison of DDR and DDRII SRAM Feature comparison of DDR and DDRII SRAM

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Flash MemoryFlash MemoryElectrically erasable, programmable and nonvolatile Electrically erasable, programmable and nonvolatile Data to be written or erased in blocks other than one Data to be written or erased in blocks other than one

byte at a time like EEPROMbyte at a time like EEPROMApplications: digital cellular phones, digital cameras, Applications: digital cellular phones, digital cameras,

LAN switches, etc; also can be used as embedded LAN switches, etc; also can be used as embedded memory or in packaged, removable memory cards, and memory or in packaged, removable memory cards, and is also a variable choice for solid data storage replacing is also a variable choice for solid data storage replacing magnetic tapes and lowmagnetic tapes and low--density hard disk drives density hard disk drives

Flash densities: range from 1 Mb to 8GbFlash densities: range from 1 Mb to 8GbFlash access times: most applications use flash Flash access times: most applications use flash

devices with random access times of 50devices with random access times of 50--80 ns80 ns

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Flash Memory (Flash Memory (contcont))•• Flash memory performance increases with greater complexity Flash memory performance increases with greater complexity

•• Performance here refers to the speed with which several read Performance here refers to the speed with which several read and write operations can be madeand write operations can be made

•• The major benefit of operating in page mode versus the The major benefit of operating in page mode versus the standard mode is the greater speedstandard mode is the greater speed

•• A A ‘‘pagepage’’ is a small group of memory words that are accessed, is a small group of memory words that are accessed, internal to the memory, in parallel rather than one at a timeinternal to the memory, in parallel rather than one at a time

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Flash Memory (Flash Memory (contcont))•• Example timing diagram for pageExample timing diagram for page--mode read (byte mode)mode read (byte mode)

- The page size of the example device is 8 words (16 bytes). The higher address bits A3-A19 select the page, and the LSB bits A0-A2 (in word mode) and A-1 to A2 (in byte mode) select the specific word/byte within page- The first read has an access time tACC, which is typical of a standard flash device, however a subsequent page read access to a location anywhere within the same page is much faster, and this access time is denoted as tPACC- Fast page-mode accesses are obtained by keeping A3-A19 constant and changing A0-A2 to select the specific word, or changing A-1 to A2 to select the specific byte within that page

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Flash CardsFlash Cards

• Flash memory chips are conveniently packaged as “flash cards” and come in several formats, including the full-size PC Card (ATA PC Card) and the smaller CompactFlash, SmartMedia, and similar formats

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FeRAM (Ferroelectric RAM) and FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive RAM)MRAM (Magnetoresistive RAM)

Features and performance:Features and performance:The next-generation nonvolatile memory for imminent

commercializationMRAM uses magnetic, thin film elements on a silicon substrate.

Data is written and read by pulsing wires that are perpendicular to each other with one set above and the other below the magnetic 7

MRAM can reach theoretical write times down to 2.3 ns, 1,000 times faster than the fastest nonvolatile flash and 20 times faster than FeRAM

MRAM access times are as fast as 3 ns, or 20 times faster than DRAM, consuming less than 1/100 the energy of DRAM

MRAM’s resistance to radiation makes it to be considered a prime replacement for SRAM, which suffers more and more from density-induced, soft-error rates as it scales below 0.1um

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Quad Data Rate (QDR) SRAMQuad Data Rate (QDR) SRAM

Address Rate: 2Address Rate: 2--word burst QDR SRAMword burst QDR SRAM-- Sustain both a 2Sustain both a 2--word read and a 2word read and a 2--word write each clock word write each clock cyclecycle-- The SRAM utilizes first The SRAM utilizes first ½½ clock cycle to perform a read clock cycle to perform a read nadnad the other the other ½½ clock cycle to perform a write operation.clock cycle to perform a write operation.-- The address bus is shared for the read and write data ports, The address bus is shared for the read and write data ports, necessitating double address rate (DAR) operationnecessitating double address rate (DAR) operation-- The clock to register, the read address and the clock to The clock to register, the read address and the clock to register and the write address are 180 out of phaseregister and the write address are 180 out of phase

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QDR SRAM (QDR SRAM (contcont))Address Rate: 4Address Rate: 4--word burst QDR SRAMword burst QDR SRAM

-- Sustain both a 4Sustain both a 4--word read and a 4word read and a 4--word write every clock word write every clock cyclecycle-- The SRAM utilizes first clock cycle to perform a read The SRAM utilizes first clock cycle to perform a read nadnadthe other clock cycle to perform a write operation.the other clock cycle to perform a write operation.-- The 4The 4--word read data is output during two cycles (4word read data is output during two cycles (4--word word burst)burst)-- Double data address rate (DAR) is neededDouble data address rate (DAR) is needed-- The rising edge of the positive signal of differential master The rising edge of the positive signal of differential master clock signal is used to register the read address. The next clock signal is used to register the read address. The next rising edge is used to latch the write address. rising edge is used to latch the write address.

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QDR SRAM (QDR SRAM (contcont))•• Write data Write data placementplacement

•• QDR SRAMs have both input and QDR SRAMs have both input and output clocksoutput clocks

•• One approach to using separate One approach to using separate input and output clocks of the QDR input and output clocks of the QDR SRAMs SRAMs

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QDR SRAM (QDR SRAM (contcont))•• Timing diagram for QDRTiming diagram for QDR

Window of valid data = (tWindow of valid data = (tKHKH KHKH –– ttCOCO) + t) + tDOHDOH-- ttKHKH KHKH : rising edge of clock to rising edge of clock 180 : rising edge of clock to rising edge of clock 180 out of phaseout of phase-- ttCO CO : clock to data output time: clock to data output time-- ttDOH DOH : the data hold time: the data hold time

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Direct Rambus DRAM (DRDRAM)Direct Rambus DRAM (DRDRAM)•• PC memory system architecture for RDRAMPC memory system architecture for RDRAM

•• Electrical topology comparisonElectrical topology comparison

The RDRAM memory interface features:The RDRAM memory interface features:-- The highest bandwidth per pinThe highest bandwidth per pin-- Supported DRAM densities from 128Supported DRAM densities from 128--512 Mb 512 Mb with a roadmap to support up to 1 Gbwith a roadmap to support up to 1 Gb-- Speed bins of 800, 1,066, 1,200, 1,333 Mbps Speed bins of 800, 1,066, 1,200, 1,333 Mbps with a roadmap to support up to 1,600 Mbpswith a roadmap to support up to 1,600 Mbps-- Memory configurable into single or dual Memory configurable into single or dual RIMM modules supporting bandwidths from RIMM modules supporting bandwidths from 1.6 GB/s to 5.3 GB/s with a roadmap to support 1.6 GB/s to 5.3 GB/s with a roadmap to support up to 12.8 GB/set quadup to 12.8 GB/set quad--channel modulechannel module

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DRDRAM (DRDRAM (contcont))•• Comparison of consumer HDTV decoder designs showing reduced chiComparison of consumer HDTV decoder designs showing reduced chip p count with the use of RDRAM count with the use of RDRAM

•• Memory system architecture comparisonMemory system architecture comparison

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DRDRAM (DRDRAM (contcont))•• Overview of a 16Overview of a 16--bit widebit wide--channel systemchannel system

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DRDRAM (DRDRAM (contcont))•• Overview of a Rambus 16Overview of a Rambus 16--bit system motherboardbit system motherboard

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•• Clock generator architectureClock generator architecture

•• Clock output drivers with example Clock output drivers with example component values shown for a channel component values shown for a channel impedance of 28 Ohmimpedance of 28 Ohm

•• Channel termination Channel termination

DRDRAM (DRDRAM (contcont))