Haptic Driver for ERM-LRA with Built-In Library and Smart ... · extensive integrated library (100+ effects) from ... To capture the graphs displayed in the this section, the following

I2C

I/F

Driver

VDD

GND

SDAI2C

Control

Feedback

DetectionSCL

Playback Engine

Auto Calibration

Auto Diagnostic

LRA or

DC Motor

DRV2605

IN/Trigger

2.5 V – 5.5 V

OUT+

OUT-

EN

ROM REG

CVREG

DRV2605

www.ti.com SLOS825B –DECEMBER 2012–REVISED JANUARY 2014

Haptic Driver for ERM and LRA with Built-In Library and Smart Loop ArchitectureCheck for Samples: DRV2605

1FEATURES DESCRIPTIONThe DRV2605 is designed to give extremely flexible• Flexible Haptic/Vibra Driverhaptic control of ERM and LRA actuators over a– LRA (Linear Resonance Actuator) shared I2C compatible bus. This relieves the host

– ERM (Eccentric Rotating Mass) processor from ever generating pulse-widthmodulated (PWM) drive signals, saving both costly• I2C Controlled Digital Playback Enginetimer interrupts and hardware pins.– Royalty-Free Integrated Immersion LibraryThe DRV2605 gives royalty-free access to an– Real-Time Playback Mode via I2Cextensive integrated library (100+ effects) from• Smart Loop Architecture(1)Immersion for ERM and LRA. This eliminates the

– Automatic Overdrive/Braking (ERM/LRA) need to design haptic waveforms.– Automatic Resonance Tracking (LRA) Additionally, the real-time playback mode allows the– Automatic Actuator Diagnostic (ERM/LRA) host processor to bypass the library playback engine

and play waveforms directly from the host via I2C.– Automatic Level Calibration (ERM/LRA)The DRV2605 also contains a smart loop• Audio To Haptics Modearchitecture, which allows effortless auto resonant• Optional PWM Input with 0% to 100% Dutydrive for LRA as well as feedback-optimized ERMCycle Control Range drive. This feedback gives automatic overdrive and

• Optional Analog Input Control braking, which creates a simplified input waveformparadigm as well as reliable motor control and• Optional Hardware Trigger Pinconsistent motor performance. The audio-to-haptics• Efficient Output Drivemode automatically converts an audio input signal to

• Fast Start Up Time meaningful haptic effects.• Constant Acceleration Over Supply Voltage The DRV2605 features a trinary-modulated output• 1.8 V Compatible, VDD Tolerant Digital Pins stage, providing greater efficiency than linear-based

output drivers. The 9-ball WCSP footprint, flexible• Available in a 9-Ball, 0.5 mm Pitch WCSPoperation, and low component count make the

(1) Patent pending control algorithm DRV2605 the ideal choice for portable and touch-enabled vibratory and haptic applications.

APPLICATIONS• Mobile Phones• Tablets• Touch-Enabled Devices

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2012–2014, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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A1 A3

B1 B2 B3

C1 C2 C3

EN OUT+

SCL

IN/TRIG SDA GND

OUT-VDD

A2

VREG

DRV2605

SLOS825B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATIONDevice Packaging Symbolization

DRV2605YZFR 3000 Piece Tape and Reel 2605DRV2605YZFT 250 Piece Tape and Reel 2605

PINOUT INFORMATION

0.5 mm Pitch BGA (WCSP)TOP VIEW

PIN FUNCTIONSPIN INPUT/ OUTPUT/ DESCRIPTIONPOWER (I/O/P)NAME NO. (WCSP)

EN A1 I Device enableIN/TRIG B1 I Multi-mode Input. I2C selectable as PWM, Analog, or Trigger

SDA B2 I/O I2C DataSCL C1 I I2C Clock

VREG A2 O 1.8 V regulator output. 0.1 µF capacitor requiredOUT+ A3 O Positive haptic driver differential outputOUT– C3 O Negative haptic driver differential outputVDD C2 P Supply Input (2.5 V to 5.5 V)GND B3 P Supply ground

2 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated

Product Folder Links: DRV2605


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DRV2605


ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range, TA = 25°C (unless otherwise noted)VALUE UNIT

VDD Supply voltage –0.3 V to 6.0 VVI Input voltage EN, SDA, SCL, IN/TRIG –0.3 to (VDD + 0.3) VTA Operating free-air temperature range –40 to 85 °CTJ Operating junction temperature range –40 to 150 °CTstg Storage temperature range –65 to 150 °C

HBM 2000 VESDProtection CDM 500 V

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operatingconditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

THERMAL INFORMATIONTHERMAL METRIC (1) VALUE UNITS

θJA Junction-to-ambient thermal resistance 145.2θJCtop Junction-to-case (top) thermal resistance 0.9θJB Junction-to-board thermal resistance 105

°C/WψJT Junction-to-top characterization parameter 5.1ψJB Junction-to-board characterization parameter 103.3θJCbot Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

spacer

RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range (unless otherwise noted)

MIN MAX UNITVDD Supply voltage VDD 2.5 5.5 VfPWM PWM input frequency IN/TRIG Pin 10 250 kHzRL Load impedance VDD = 5.5 V 8 ΩVIL Digital input low voltage EN, IN/TRIG, SDA, SCL 0.5 VVIH Digital input high voltage EN, IN/TRIG, SDA, SCL 1.3 VVI-ANA Input voltage (analog mode) IN/TRIG 0 1.8 VfLRA LRA Frequency Range 50 300 Hz

Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 3



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DRV2605


ELECTRICAL CHARACTERISTICSTA = 25°C, VDD = 3.6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVREG VREG 1.84 V|IIL| Digital input low current EN VDD = 5.5 V , VIN = 0 V 1 µA|IIH| Digital input high current EN VDD = 5.5 V, VIN = VDD 3.5 µAVOL Digital output low voltage SDA IOL = 4 mA 0.4 VISD Shut down current VEN = 0 V 1.75 4 µAISB Standby current VEN = 1.8 V, STANDBY = 1 1.9 5 µAIDDQ Quiescent current VEN = 1.8 V, STANDBY = 0, no signal 0.6 1 mARIN Input impedance IN/TRIG to GND 100 kΩ

IN/TRIG Common-Mode Voltage (ACVCM-ANA AC_Couple = 1 0.9 VCoupled)ROUT-SD Output impedance in shutdown OUT+ to GND, OUT- to GND 15 kΩ

Load impedance threshold for over-RL-SD OUT+ to GND, OUT- to GND 4 Ωcurrent detectionTime from GO or external trigger command 0.7to output signal

tSU Start-up time msTime from EN high to output signal 1.5(PWM/Analog Modes)Duty Cycle = 90%, LRA Mode, No Load 2.5 3.25Average battery current duringIBAT, AVG mAoperation Duty Cycle = 90%, ERM Mode, No Load 2.5 3.25

fSW PWM Output Frequency 19.5 20.5 21.5 kHz




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SCL

SDA

tsu2

th2t(buf)

tsu3

Start Condition Stop Condition

SCL

SDA

t (H)w t (L)w

tsu1 th1

DRV2605


TIMING REQUIREMENTSTA = 25°C, VDD = 3.6 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITfSCL Frequency, SCL No wait states 400 kHztW(H) Pulse duration, SCL high 0.6 μstW(L) Pulse duration, SCL low 1.3 μstSU1 Setup time, SDA to SCL 100 nstH1 Hold time, SCL to SDA 10 ns

Bus free time between stop and startt(BUF) 1.3 μsconditiontSU2 Setup time, SCL to start condition 0.6 μstH2 Hold time, start condition to SCL 0.6 μstSU3 Setup time, SCL to stop condition 0.6 μs

Figure 1. SCL and SDA Timing

Figure 2. Timing for Start and Stop Conditions




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ERM

Or

LRA

OUT+

OUT–

100kΩ

100kΩ

470 pF

470 pF

Ch1-Ch2

(Differential)

Oscilloscope

Ch1

Ch2

DRV2605


TYPICAL CHARACTERISTICS

TEST SETUP FOR GRAPHSTo capture the graphs displayed in the this section, the following 1st order, RC filter setup was used, with theexception of "Startup Latency for ERM and LRA", which was captured without any output filter. This filter isrecommended when viewing the outputs signals on an oscilloscope since output PWM modulation is present inall modes. Care must be taken that the filter does not have an effective impedance that is too low, or the closedloop and auto resonance tracking features may be affected; therefore, it is recommended that this exact filter beused for output measurement. Most oscilloscopes have an input impedance of 1 MΩ on each channel, so thereis an approximate 1% loss in measured amplitude due to the voltage divider effect with the filter.

Figure 3. Alternate Test Setup

Default Test Conditions:• VDD = 3.6 V, unless otherwise noted.• Real actuators were used as loads for both ERM and LRA modes with exception of "Supply Voltage vs

Supply Current (Full Vibration)", which used passive RL loads for test repeatability. Real actuators vary widelyin supply current due to variation in back EMF voltages. Because real actuators have back EMF, the realsupply current will generally be less than depicted in the graph due to reduced apparent load impedance, sothe worst case current is represented in the graph.

• All ERM library waveforms taken with Library A in open loop mode• All LRA library waveforms taken with LRA Library in closed loop mode• All traces are 2 V/division except for the accelerometer traces• All accelerometer traces are 0.87 g/division except for "LRA Click with and without Braking (PWM)", which is

1.74 g/division




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t − Time − s

Vol

tage

− (

2V/d

iv)

0 200m 400m 600m 800m 1

SDAAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VERM Open LoopInternal TriggerSequence = 0x01, 0x48

t − Time − s

Vol

tage

− (

2V/d

iv)

0 200m 400m 600m 800m 1

SDAAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VLRA Closed LoopInternal TriggerTransition Click 1 − 100%

t − Time − s

Vol

tage

− (

2V/d

iv)

0 40m 80m 120m 160m 200m

IN/TRIGAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VERM Open LoopExternal Edge TriggerStrong Click − 60%

t − Time − s

Vol

tage

− (

2V/d

iv)

0 40m 80m 120m 160m 200m

IN/TRIGAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VLRA Closed LoopExternal Level TriggerStrong Click − 100%

DRV2605


ERM Click (Library) LRA Click (Library)

Figure 4. Figure 5.

ERM Click-Bounce (Library) LRA Transition-Click (Library)

Figure 6. Figure 7.




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t − Time − s

Vol

tage

− (

2V/d

iv)

0 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m

SDAERM ModeLRA Mode

VDD = 3.6 VClosed LoopNo Filter

VDD − Supply Voltage − V

I DD −

Sup

ply

Cur

rent

− m

A

2.5 3.0 3.5 4.0 4.5 5.0 5.550

60

70

80

90

100ERM Mode, RL = 10 Ω + 100 µH, 1.3 VLRA Mode, RL = 25 Ω + 100 µH, 2 Vrms

t − Time − s

Vol

tage

− (

2V/d

iv)

0 40m 80m 120m 160m 200m

ENSDAAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VERM Closed LoopRTP Mode

t − Time − s

Vol

tage

− (

2V/d

iv)

0 40m 80m 120m 160m 200m

ENIN/TRIGAcceleration[OUT+] − [OUT−] (Filtered)

VDD = 3.6 VLRA Closed LoopPWM Mode

DRV2605


ERM Buzz (RTP) LRA Click with and without Braking (PWM)

Figure 8. Figure 9.

Startup Latency from GO for ERM and LRA Supply Current Vs Supply Voltage (Full Vibration)

Figure 10. Figure 11.




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VDD

DRV2605

EN

IN

Application

Processor

GPIO

SDA GND

OUT+

OUT-

2.5 V to

5.5 V

CVDD

LRA

or

ERMSCL

SDA

SCL

CIN

VREG

CVREG

RPU RPU

Analog

Optional

VDD

DRV2605

EN

IN/TRIG

Application

Processor

GPIO

SDA GND

OUT+

OUT-

2.5 V to

5.5 V

CVDD

SCL

SDA

SCL

VREG

CVREG

PWM/GPIO

RPU RPU

LRA

or

ERM

DRV2605


SYSTEM DIAGRAMS

Figure 12. I2C Control with Optional PWM Input or External Trigger

Figure 13. I2C Control with Audio To Haptics Input and Optional AC Coupling




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Accele

rati

on

(g

)

fRESONANCE

Frequency (Hz)

DRV2605


APPLICATION INFORMATION

ECCENTRIC ROTATING MASS MOTORS (ERM)Eccentric Rotating Mass motors, or ERMs, are typically DC-controlled motors of the bar or coin type. ERMs canbe driven in the clockwise direction or counter-clockwise depending on the polarity of voltage across its twoterminals. Bi-directional drive is made possible in a single-supply system by differential outputs that are capableof sourcing and sinking current. This feature helps eliminate long vibration tails which are undesirable in hapticfeedback systems.

Figure 14. Motor Spin Direction in ERM Motors

Another common approach to driving DC motors is the concept of overdrive voltage. To overcome the inertia ofthe motor's mass, they are often overdriven for a short amount of time before returning to the motor's ratedvoltage to sustain the motor's rotation. Overdrive is also used to stop (or brake) a motor quickly. Reference themotor's datasheet for safe and reliable overdrive voltage and duration.

LINEAR RESONANCE ACTUATORS (LRA)Linear Resonant Actuators, or LRAs, vibrate optimally at their resonant frequency. LRAs have a high-Qfrequency response due to which there is a rapid drop in vibration performance at offsets of 3-5 Hz from theresonant frequency. Many factors also cause a shift or drift in the resonant frequency of the actuator such astemperature, aging, the mass of the product to which the LRA is mounted, and in the case of a portable product,the manner in which it is held. Furthermore, as the actuator is driven to its maximum allowed voltage, manyLRAs will shift several Hz in frequency due to mechanical compression. All of these factors make a real-timetracking auto-resonant algorithm critical when driving LRA to achieve consistent, optimized performance.

Figure 15. Typical LRA Response

AUTO-RESONANCE ENGINE FOR LRAThe DRV2605 auto resonance engine tracks the resonant frequency of an LRA in real time. If the resonantfrequency shifts in the middle of a waveform for any reason, the engine will track it cycle to cycle. The autoresonance engine accomplishes this by constantly monitoring the back-EMF of the actuator. Note that the autoresonance engine is not affected by the auto calibration process, which is only used for level calibration. Nocalibration is required for the auto resonance engine.




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Input /Output

Accleration

“Ideal” Open-Loop Waveform forMotor A

Output With Feedback

“Ideal” Open-Loop Waveform forMotor B

Same Simple Input forBoth Motors

Feedback providesOptimum Output Drive

DRV2605


OPEN LOOP OPERATION FOR LRAThe DRV2605 includes an open loop LRA drive mode for legacy systems. This mode is valid for PWM inputmode only. This mode employs a fixed divider that observes the PWM signal and commutates the output drivesignal at the PWM frequency divided by 128. To accomplish LRA drive, the host should drive the PWMfrequency at 128 times the resonance frequency of the LRA. It is important to note that this will not benefit fromthe auto resonance tracking feature of the DRV2605.

SMART LOOP ARCHITECTUREA key feature of the DRV2605 is the smart loop architecture, which employs actuator feedback control for bothERMs and LRAs. The feedback control de-sensitizes the input waveform from the motor response behavior byproviding automatic overdrive and automatic braking.

An open loop haptic system will typically drive an overdrive voltage at startup that is higher than the actuator’ssteady-state rated voltage to decrease the actuator’s startup latency. Likewise, a braking algorithm must beemployed for effective braking. When using an open loop driver, these behaviors must be contained in the inputwaveform data. Figure 16 illustrates how two different ERMs with different startup behaviors can both be drivenoptimally by the smart loop with a simple square pulse at the input. Note the smart loop works equally well forLRAs with a combination of feedback control and an auto resonance engine.

Figure 16. Waveform Simplification with Smart Loop

AUTO CALIBRATIONThe smart loop architecture utilizes actuator feedback by monitoring the back-EMF behavior of the actuator. Thelevel of back-EMF can vary across actuator manufacturers due to the specific actuator construction. The autocalibration compensates for this variation and also performs scaling for the desired actuator according to thespecified rated voltage and overdrive clamp register settings. After the auto calibration is performed, a 100%signal level at any of the DRV2605 input interfaces will supply the rated voltage to the actuator at steady-state.The feedback will allow the output level to go above the rated voltage level for automatic overdrive and braking,but it will not exceed the programmable overdrive clamp voltage.

See “Auto Calibration Procedure” in Device Programming section for details on performing auto calibration.




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0x00

0x7FF

ERM Library A

LibrarySel = 1

ERM Library E

LibrarySel = 5

LRA Library

LibrarySel = 6

Auxillary Library

Empty

LibrarySel = 7

DRV2605


WAVEFORM LIBRARIESThe DRV2605 has 6 internal ROM libraries designed by Immersion called TS2200. These first five libraries arespecifically tuned for 5 categories of ERM motors in the open loop mode of operation. Library 6 is tuned for LRAdevices. Auxiliary library 7 currently contains no information, but may be populated with other libraries in futuredevice revisions.

WAVEFORM SEQUENCERThe waveform sequencer (See registers 0x04 to 0x0B) is used to queue waveform library identifiers for playback.There are eight sequence registers to queue up to eight library waveforms for sequential playback. A waveformidentifier is an integer value referring to the index position of a waveform in a ROM library. Playback begins atregister address 0x04 when the user asserts the GO bit (Register 0x0C). When playback of that waveform ends,the waveform sequencer plays the next waveform identifier held in register 0x05, if it is non-zero. The waveformsequencer continues in this fashion until it reaches an identifier value of zero, or all eight identifiers are played(register addresses 0x04 through 0x0B), whichever comes first.

The waveform identifier range is 1 to 127. The MSB of each sequence register may be used to implement adelay between sequence waveforms. When the MSB is high, bits [6:0] are used to indicate the length of the waittime. The wait time for that step then becomes WavfrmSeq[6:0] × 10 milliseconds.

LIBRARY PARAMETERIZATIONThe ROM libraries will be augmented by the following 8-bit values in the register map. This parameterization willtake place only for the ROM libraries and not for the other interfaces (e.g. PWM, RTP). The purpose of thisfunctionality is to add “time stretching” (or time shrinking) parameters to the playback. This can be useful forcustomizing the entire library of waveforms for a specific actuator rise time and fall time.

ODT: Overdrive TimeSPT: Sustain Positive TimeSNT: Sustain Negative TimeBRT: Brake Time

The time values are additive offsets and are 8-bit signed values. These values are 0 offset by default. Positivevalues add, and negative values subtract from the “Time” value of the effect that is currently being played. Themost positive value in the waveform is automatically interpreted as the overdrive time, and the most negativevalue in the waveform is automatically interpreted as the brake time. These time offset parameters are applied toboth Voltage/Time pairs and linear ramps. For linear ramps, linear interpolation is shrunken/stretched over thetwo operative points for the period Time+TimeOffset, where TimeOffset is one of the time parameters listedabove.

REAL-TIME PLAYBACK (RTP) MODEThe real time playback mode is a simple, single 8-bit register interface that holds an amplitude value. It isenabled by selecting RTP Mode in the Mode register. Once real-time playback is enabled, the real-time playbackregister will be sent directly to the playback engine. This value is played until the user sets device in STANDBYmode or exits RTP mode. The RTP mode operates exactly like the PWM mode, except the user is entering aregister value over I2C rather than a duty cycle via the input pin; therefore, any API designed to use a PWMgenerator in the host processor can write the data values over I2C rather than writing the data values to the hosttimer. This frees a timer in the host while retaining compatibility with the original software.




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DRV2605


MULTI-MODE INPUT PIN (IN/TRIG)The multi-mode input pin serves four different functions:1. PWM Input Mode2. Analog Input Mode3. Audio To Haptics Mode4. Input Trigger Mode

If the IN/TRIG pin function is not needed, the pin should be tied directly to ground.

PWM Input OptionThe user may enter the PWM mode by setting Mode register value to 3 and setting the nPWM_Analog bit to 0.When in this mode, the DRV2605 accepts PWM data at the IN/TRIG pin. The DRV2605 drives the actuatorcontinuously in this mode until the user sets the device into STANDBY mode, or enters another interface mode.The interpretation of the duty cycle information varies according to the chosen mode of operation. See “Modes OfOperation” for details.

Analog Input OptionThe user may enter the analog input mode by setting Mode register value to 3, and setting the nPWM_Analog bitto 1. When in this mode, the DRV2605 accepts an analog voltage at the IN/TRIG pin. The DRV2605 will drivethe actuator continuously in this mode until the user sets the device into STANDBY mode, or enters anotherinterface mode. The reference voltage in this mode is 1.8 V, so 1.8 V will be interpreted as a 100% input value,0.9 V will be 50%, and 0 V will be 0%. The input value is analogous to the duty cycle percentage in PWM mode.The interpretation of these percentages varies according to the chosen mode of operation. See “Modes OfOperation” for details.

Audio To Haptics ModeThe DRV2605 features an audio to haptics mode that converts an audio input signal into meaningful hapticeffects using the Immersion "BOOMbox" technology. Audio to haptics mode adds a vibratory "bass extension" toportable devices, allowing the user to feel their audio/visual content. This is a key feature because it allows forthe "haptification" of existing applications without the need for additional software drivers. Additionally, event-driven audio effects generated within an operating system can be used to automatically "haptify" a product.

To take advantage of this feature, connect the DRV2605 to a line out source as shown in Figure 13. The full-scale range of the IN/TRIG pin in the audio to haptics mode is 1.8 VPP. The input impedance is 100 kΩ, so aresistive divider can be used if the input source is greater than 1.8 VPP, and a 0.1 µF capacitor is recommendedto AC couple the audio source and the IN/TRIG pin. For sources smaller than 1.8 VPP, the ATH_MaxInputparameter can be used to scale down the input range. To put the device in audio to haptics mode, setMode[2:0] = 4, and set the AC_Couple and nPWM_Analog bits to 1. See the register map for more details.

Input Trigger OptionThe user may enter the external trigger modes by setting the Mode register value to 1 or 2. A value of 1 entersEdge Mode, and a value of 2 enters Level Mode. In these modes, the IN/TRIG pin provides external triggercontrol of the GO bit, which allows ROM waveforms to be fired by GPIO control. This external trigger control canprovide improved latencies in systems where there is significant delay between the time the effect is desired andthe time a GO command can be sent over the I2C interface. Note that the effect to be triggered must already beselected to take advantage of the lower latency, so this works best for accelerating a pre-queued high-priorityeffect (like a button press) or for the repeated firing of the same effect (like scrolling).




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Level Trigger

Haptic Waveform

Level Trigger

Haptic Waveform

Cancellation

Haptic Waveform

Edge Trigger

Haptic Waveform

Edge Trigger

Cancellation

DRV2605


Input Trigger Options (Continued)Edge Mode – A low-to-high transition on the IN/TRIG will cause the GO bit to be set. The playback sequenceindicated in the waveform sequencer will play as per normal. The user may cancel the transaction by clearing theGO bit. Another low-to-high transition while the GO bit is still high will also cancel the transaction, causing theGO bit to clear and reset. Clearing the trigger pin (high-to-low transition) does nothing, so the user may send ashort pulse without knowing how long the waveform is. The pulse width should be at least 1 µs to assuredetection.

Figure 17. Edge Trigger Mode

Level Mode – The GO bit behavior follows the IN/TRIG pin directly. When the IN/TRIG pin is high, the GO bit ishigh, when the trigger pin goes low, the GO bit is cleared; therefore, a falling edge will cancel the transaction.This can implement a GPIO-controlled buzz on/off controller if an appropriately long waveform is selected. Theuser needs to hold the IN/TRIG high for the entire duration of the waveform to complete the effect.

Figure 18. Level Trigger Mode




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DRV2605


DEVICE ENABLEThe EN pin of the DRV2605 is used to gate the active operation. When EN is logic high, the DRV2605 is active,and when EN is logic low, the device enters a state that is equivalent to the low-power STANDBY state. Thedevice registers are not reset. This is particularly useful for constant source PWM/analog input modes tomaintain compatibility with non-I2C device signaling. EN must be high to write I2C device registers. To completelyreset the device into the power up state, set the Dev_Reset bit.

CONSTANT VIBRATION STRENGTHThe DRV2605 PWM input uses a digital level-shifter, so as long as the input voltage meets the VIH and VILlevels, the vibration strength will remain the same even if the digital levels were to vary. The DRV2605 alsofeatures power supply feedback, so if the supply voltage drifts over time (due to battery discharge, for example),the vibration strength will remain the same so long as there is enough supply voltage to sustain the requiredoutput voltage.

EDGE RATE CONTROLThe DRV2605 output driver implements Edge Rate Control (ERC). This ensures that the rise and fallcharacteristics of the output drivers do not emit levels of radiation that could interfere with other circuitry commonin mobile and portable platforms. Because of ERC, no output filter, capacitors, or ferrites are necessary.

CAPACITOR SELECTIONThe DRV2605 has a switching output stage which pulls transient currents through the VDD pin. A 0.1 µF, lowequivalent-series-resistance (ESR) supply bypass capacitor of the X5R or X7R type is recommended to beplaced near the VDD supply pin for smooth operation of the output driver and the digital portion of the device. Asimilar capacitor should be placed from VREG to ground.




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Input

Steady-State

Output Magnitude

ODClamp[7:0]

0 V

Open LoopERM_OpenLoop = 1 OR LRA_OpenLoop = 1

RTP (8-bit) DataFormat_RTP = 0

PWM

Input Interface

0% 50% 100%

RTP (8-bit) DataFormat_RTP = 1 0x00 0x7F 0xFF

0x81 0x00 0x7F

-ODClamp[7:0]

DRV2605


MODES OF OPERATIONThe DRV2605 smart loop architecture has three modes of operation. Each of these modes can be used to driveeither ERM or LRA devices.1. Open Loop Mode2. Closed Loop Mode (Uni-Directional)3. Closed Loop Mode (Bi-Directional)

Each mode has its own advantages and disadvantages. The DRV2605 brings a new, cutting-edge actuatorcontrol with closed loop operation around the back-EMF for automatic overdrive and braking; however, someexisting haptic libraries already include overdrive and braking that is embedded in the waveform data. Open loopmode is used to preserve compatibility with such systems.

The following sections show how the input data for each DRV2605 interface is translated to the output drivesignal.

Open Loop ModeIn open loop mode, the reference level for full-scale drive is set by the ODClamp[7:0] value. A mid-scale inputvalue gives no drive signal, and less than mid-scale give a negative drive value. For ERM, a negative drive valueresults in counter-rotation, or braking. For LRA, this translates to a 180 degree phase shift in commutation.

The RTP mode has 8 bits of resolution over the I2C bus. The RTP data can be in either signed (2’s complement)or unsigned format as defined by DataFormat_RTP.

Restrictions: Open loop operation for LRA is only valid with the PWM interface. See “Open Loop Operation forLRA” for details. All input interfaces shown will work with ERM.




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Input

Steady-State

Output Magnitude

RatedVoltage[7:0]

½ RatedVoltage[7:0]

Full Braking

PWM

Input Interface

0% 50% 100%

RTP (8-bit) DataFormat_RTP = 1 0x00

Closed Loop, BiDir_Input = 0

0x7F 0xFF

DRV2605


Closed Loop Mode, Uni-DirectionalIn closed loop, uni-directional mode, the DRV2605 gives automatic overdrive and braking for both ERM and LRAdevices. This is the most straight-forward mode to use and understand, and uses the full, 8-bit resolution of thedriver. This mode gives the best performance; however, the data format is not physically compatible with theopen loop mode data that may be used in some existing systems

The reference level for steady-state, full-scale drive is set by the RatedVoltage[7:0] value (once auto calibrationis performed). The output voltage may momentarily exceed the rated voltage for automatic overdrive andbraking, but will not exceed the ODClamp[7:0] voltage. Braking happens automatically based on the input signalwhen the back-EMF feedback determines that it is necessary.

Since the system is uni-directional in this mode, only unsigned data should be used. The RTP mode has 8 bits ofresolution over the I2C bus. DataFormat_RTP = 0 (signed) is not recommended for this mode.

Restrictions: For the RTP interface, DataFormat_RTP should be set to 1 (unsigned).




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RTP (8-bit) DataFormat_RTP = 0

Input

Steady-State

Output Magnitude

RatedVoltage[7:0]

½ RatedVoltage[7:0]

PWM

Input Interface

0% 50% 100%

RTP (8-bit) DataFormat_RTP = 1 0x00

Closed Loop, BiDir_Input = 1

0x7F 0xFF

Full Braking

0x81 0x00 0x7F0x3F

0xBF

75%

DRV2605


Closed Loop Mode, Bi-DirectionalIn closed loop, bi-directional mode, the gives automatic overdrive and braking for both ERM and LRA devices.This mode preserves compatibility with data created in open-loop signaling by keeping zero drive strength at themid-scale value. When input values less than the mid-scale value are given, the DRV2605 will treat them thesame as the mid-scale with zero drive.

The reference level for steady-state, full-scale drive is set by the RatedVoltage[7:0] value (once auto calibrationis performed). The output voltage may momentarily exceed the rated voltage for automatic overdrive andbraking, but will not exceed the ODClamp[7:0] voltage. Braking happens automatically based on the input signalwhen the back-EMF feedback determines that it is necessary. Since this mode preserves compatibility withexisting/legacy dataDRV2605 formats, yet still provides closed loop benefits, it is the default configuration atpower up.

The RTP mode has 8 bits of resolution over the I2C bus. The RTP data can be in either signed (2’s complement)or unsigned format as defined by DataFormat_RTP.

Restrictions: This mode is compatible with all DRV2605 interfaces except for TS2200 Library A (with fixedoverdrive programming). Library A should only be used in open loop mode. Libraries B through E (no overdrive)may take advantage of this mode for automatic overdrive and braking.




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DRV2605


BLOCK DIAGRAM




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7-Bit Slave AddressR/W

8-Bit Register Address (N)A8-Bit Register Data For

Address (N)

Start Stop

SDA

SCL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

A8-Bit Register Data For

Address (N)A A

T0035-01

DRV2605


GENERAL I2C OPERATIONThe I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in asystem. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving devicewith an acknowledge bit. Each transfer operation begins with the master device driving a start condition on thebus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the dataterminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition onSDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur withinthe low time of the clock period. Figure 19 shows a typical sequence. The master generates the 7-bit slaveaddress and the read/write (R/W) bit to open communication with a slave device and then waits for anacknowledge condition. The slave device holds SDA low during the acknowledge clock period to indicateacknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device isaddressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signalsvia a bidirectional bus using a wired-AND connection.

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the lastword transfers, the master generates a stop condition to release the bus. A generic data transfer sequence isshown in Figure 19.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull-up resistorsbetween 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2605supply voltage, VDD.

Figure 19. Typical I2C Sequence

The DRV2605 operates as an I2C slave 1.8 V logic thresholds, but can operate up to the VDD voltage. Thedevice address is 0x5A (7-bit), or 1011010 in binary. This is equivalent to 0xB4 (8-bit) for writing and 0xB5 (8-bit)for reading.

SINGLE-BYTE AND MULTIPLE-BYTE TRANSFERSThe serial control interface supports both single-byte and multiple-byte read/write operations for all registers.

During multiple-byte read operations, the DRV2605 responds with data, a byte at a time, starting at the registerassigned, as long as the master device continues to respond with acknowledges.

The DRV2605 supports sequential I2C addressing. For write transactions, if a register is issued followed by datafor that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. ForI2C sequential write transactions, the register issued then serves as the starting point, and the amount of datasubsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.




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D7 D0 ACK

StopCondition

Acknowledge

I C Device Address andRead/Write Bit

2Subaddress Last Data Byte

A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK

StartCondition Acknowledge Acknowledge Acknowledge

First Data Byte

A4 A3A6

Other Data Bytes

ACK

Acknowledge

D0 D7 D0

T0482-01

A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

StartCondition

StopCondition

Acknowledge Acknowledge Acknowledge


2Subaddress Data Byte

T0481-01

DRV2605


SINGLE-BYTE WRITEAs shown in Figure 20, a single-byte data-write transfer begins with the master device transmitting a startcondition followed by the I2C device address and the read/write bit. The read/write bit determines the direction ofthe data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2Cdevice address and the read/write bit, the DRV2605 responds with an acknowledge bit. Next, the mastertransmits the register byte corresponding to theDRV2605 internal memory address being accessed. Afterreceiving the register byte, the DRV2605 again responds with an acknowledge bit. Finally, the master devicetransmits a stop condition to complete the single-byte data-write transfer.

The DRV2605 address is 0x5A (7-bit), or 1011010 in binary.

Figure 20. Single-Byte Write Transfer

MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITEA multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytesare transmitted by the master device to the DRV2605 as shown in Figure 21. After receiving each data byte, theDRV2605 responds with an acknowledge bit.

Figure 21. Multiple-Byte Write Transfer




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A6 A0 ACK

Acknowledge


2

R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK

StartCondition

StopCondition


Last Data Byte

ACK

First Data Byte

Repeat StartCondition

NotAcknowledge


2Subaddress Other Data Bytes

A7 A6 A5 D7 D0 ACK

Acknowledge

D7 D0

T0484-01

A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK

StartCondition

StopCondition



2Subaddress Data Byte

D7 D6 D1 D0 ACK


2

NotAcknowledge

R/WA1 A1

Repeat StartCondition

T0483-01

DRV2605


SINGLE-BYTE READAs shown in Figure 22, a single-byte data-read transfer begins with the master device transmitting a startcondition followed by the I2C device address and the read/write bit. For the data-read transfer, both a writefollowed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memoryaddress to be read. As a result, the read/write bit is set to a 0.

After receiving the DRV2605 address and the read/write bit, the DRV2605 responds with an acknowledge bit.The master then sends the internal memory address byte, after which the DRV2605 issues an acknowledge bit.The master device transmits another start condition followed by the DRV2605 address and the read/write bitagain. This time, the read/write bit is set to 1, indicating a read transfer. Next, the DRV2605 transmits the databyte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

The DRV2605 address is 0x5A (7-bit), or 1011010 in binary.

Figure 22. Single-Byte Read Transfer

MULTIPLE-BYTE READA multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytesare transmitted by the DRV2605 to the master device as shown in Figure 23. With the exception of the last databyte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 23. Multiple-Byte Read Transfer




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DRV2605


REGISTER MAP

Table 1. Register Map OverviewReg# Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x00 0xA0 DeviceID[2] DeviceID[1] DeviceID[0] Diag_Result Feedback_Status OverTemp OC_Detect

0x01 0x40 Dev_Reset STANDBY Mode[2] Mode[1] Mode[0]

0x02 0x00 RTP_Input[7] RTP_Input[6] RTP_Input[5] RTP_Input[4] RTP_Input[3] RTP_Input[2] RTP_Input[1] RTP_Input[0]

0x03 0x00 Hi_Z LibrarySel[2] LibrarySel[1] LibrarySel[0]

0x04 0x01 Wait1 WavfrmSeq1[6] WavfrmSeq1[5] WavfrmSeq1[4] WavfrmSeq1[3] WavfrmSeq1[2] WavfrmSeq1[1] WavfrmSeq1[0]






0x0A 0x00 Wait7 WavfrmSeq7[6] WavfrmSeq7[5] WavfrmSeq7[4] WavfrmSeq7[3] WavfrmSeq7[2] WavfrmSeq7[1] WavfrmSeq7[0]

0x0B 0x00 Wait8 WavfrmSeq8[6] WavfrmSeq8[5] WavfrmSeq8[4] WavfrmSeq8[3] WavfrmSeq8[2] WavfrmSeq8[1] WavfrmSeq8[0]

0x0C 0x00 GO

0x0D 0x00 ODT[7] ODT[6] ODT[5] ODT[4] ODT[3] ODT[2] ODT[1] ODT[0]

0x0E 0x00 SPT[7] SPT[6] SPT[5] SPT[4] SPT[3] SPT[2] SPT[1] SPT[0]

0x0F 0x00 SNT[7] SNT[6] SNT[5] SNT[4] SNT[3] SNT[2] SNT[1] SNT[0]

0x10 0x00 BRT[7] BRT[6] BRT[5] BRT[4] BRT[3] BRT[2] BRT[1] BRT[0]

0x11 0x05 ATH_PeakTime[1] ATH_PeakTime[0] ATH_Filter[1] ATH_Filter[0]

0x12 0x19 ATH_MinInput[7] ATH_MinInput[6] ATH_MinInput[5] ATH_MinInput[4] ATH_MinInput[3] ATH_MinInput[2] ATH_MinInput[1] ATH_MinInput[0]

0x13 0xFF ATH_MaxInput[7] ATH_MaxInput[6] ATH_MaxInput[5] ATH_MaxInput[4] ATH_MaxInput[3] ATH_MaxInput[2] ATH_MaxInput[1] ATH_MaxInput[0]

0x14 0x19 ATH_MinDrive[7] ATH_MinDrive[6] ATH_MinDrive[5] ATH_MinDrive[4] ATH_MinDrive[3] ATH_MinDrive[2] ATH_MinDrive[1] ATH_MinDrive[0]

0x15 0xFF ATH_MaxDrive[7] ATH_MaxDrive[6] ATH_MaxDrive[5] ATH_MaxDrive[4] ATH_MaxDrive[3] ATH_MaxDrive[2] ATH_MaxDrive[1] ATH_MaxDrive[0]

0x16 0x3F RatedVoltage[7] RatedVoltage[6] RatedVoltage[5] RatedVoltage[4] RatedVoltage[3] RatedVoltage[2] RatedVoltage[1] RatedVoltage[0]

0x17 0x89 ODClamp[7] ODClamp[6] ODClamp[5] ODClamp[4] ODClamp[3] ODClamp[2] ODClamp[1] ODClamp[0]

0x18 0x0D ACalComp[7] ACalComp[6] ACalComp[5] ACalComp[4] ACalComp[3] ACalComp[2] ACalComp[1] ACalComp[0]

0x19 0x6D ACalBEMF[7] ACalBEMF[6] ACalBEMF[5] ACalBEMF[4] ACalBEMF[3] ACalBEMF[2] ACalBEMF[1] ACalBEMF[0]

0x1A 0x36 nERM_LRA FBBrakeFactor[2] FBBrakeFactor[1] FBBrakeFactor[0] LoopGain[1] LoopGain[0] BEMFGain[1] BEMFGain[0]

0x1B 0x93 StartupBoost AC_Couple DriveTime[4] DriveTime[3] DriveTime[2] DriveTime[1] DriveTime[0]

0x1C 0xF5 BiDir_Input BrakeStabilizer SampleTime[1] SampleTime[0] BlankingTime[1] BlankingTime[0] IDissTime[1] IDissTime[0]

0x1D 0x80 NG_Thresh[1] NG_Thresh[0] ERM_OpenLoop SupplyCompDis DataFormat_RTP LRADriveMode nPWM_Analog LRA_OpenLoop

0x1E 0x20 AutoCalTime[1] AutoCalTime[0] OTP_Status OTP_Program

0x21 0x00 VBAT[7] VBAT[6] VBAT[5] VBAT[4] VBAT[3] VBAT[2] VBAT[1] VBAT[0]

0x22 0x00 LRA_Period[7] LRA_Period[6] LRA_Period[5] LRA_Period[4] LRA_Period[3] LRA_Period[2] LRA_Period[1] LRA_Period[0]




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DRV2605


Status (Address: 0x00)

Bit 7 6 5 4 3 2 1 0

Function DeviceID[2] DeviceID[1] DeviceID[0] Diag_Result Watchdog_Status OverTemp OC_Detect

Type RO RO RO RO RO RO RO

Default 1 0 1 0 0 0 0

DeviceID[2:0] Device identifier. This indicates the part number to the user. The user software canascertain the device capabilities by reading this register.

4: DRV2604 (does not contain licensed ROM library)3: DRV2605 (contains licensed ROM library)

Diag_Result This flag stores the result of the auto calibration routine and the diagnostic routine. The flagcontains the result for whichever routine was executed last. The flag clears upon read. Testresult is not valid until the GO bit self-clears at the end of the routine.Auto Calibration

0: Auto-Calibration Passed (Optimum result converged)1: Auto-Calibration Failed (Result did not converge)

Diagnostic0: Actuator is functioning normally1: Actuator is not present, shorted, timing out, or giving out-of-range back-EMF

Feedback_Status Contains status for the feedback controller. This indicates when the ERM back-EMF hasbeen zero for > ~10 ms for ERM mode, and indicates when the LRA frequency trackinghas lost frequency lock in LRA mode. This bit is for debug purposes only, and maysometimes be set under normal operation when extensive braking periods are used. Thisbit will clear upon read.

0: Feedback controller has not timed out1: Feedback controller has timed out

OverTemp Latching over-temperature detection flag. The device will shut itself down if it becomes toohot. Clears upon read.

0: Device is functioning normally1: Device has exceeded the temperature threshold

OC_Detect Latching over-current detection flag. The device will shut itself down if the load impedanceis below the load impedance threshold, and will periodically try to restart itself until theimpedance is above the threshold.

0: No over-current event has been detected1: Over-current even has been detected




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DRV2605


Mode (Address: 0x01)

Bit 7 6 5 4 3 2 1 0Function Dev_Reset STANDBY Mode[2] Mode[1] Mode[0]Type R/W R/W R/W R/W R/WDefault 0 1 0 0 0

Dev_Reset Device Reset. Setting this bit performs the equivalent operation of power cycling the device.Any playback operations are immediately interrupted, and all registers are reset to theirdefault values. The Dev_Reset bit self-clears after the reset operation is complete.

STANDBY Software Standby Mode0: Device Ready1: Device in Software Standby (default)

Mode[2:0] 0: Internal Trigger (default)Waveforms fired by setting the GO bit

1: External Trigger (Edge Mode)A rising edge on the IN/TRIG pin sets the GO Bit. A 2nd rising edge on the IN/TRIG pinwill cancel the waveform if it occurs before the GO bit has cleared.

2: External Trigger (Level Mode)GO bit follows the state of the external trigger. A rising edge on the IN/TRIG pin sets theGO bit, and a falling edge sends a cancel. If the GO bit is already in the appropriatestate, no change is effected.

3: PWM Input/Analog InputA PWM signal is accepted at the IN/TRIG pin and used as the driving source. Thedevice actively drives the actuator while in this mode. The user may elect to setnPWM_Analog to drive an analog signal directly into the IN/TRIG pin.

4: Audio To HapticsAn AC Coupled audio signal is accepted at the IN/TRIG pin. The device converts theaudio signal into meaningful haptic vibration. The AC_Couple and nPWM_Analog bitsshould also be set.

5: Real-Time Playback (RTP Mode)The device actively drives the actuator with the contents of the RTP_Data register.

6: DiagnosticsSet the device in this mode to perform a diagnostic test on the actuator. User must setthe GO bit to start the test. Test is complete when the GO bit self-clears. Results arestored in the Diag_Result bit.

7: Auto CalibrationSet the device in this mode to auto calibrate for the device for the actuator. Beforestarting the calibration, the user must set the Rated_Voltage and ODClamp registers(0x16 and 0x17) appropriately. User must set the GO bit to start the calibration.Calibration is complete when the GO bit self-clears. Auto calibration results are stored inregisters 0x18, 0x19, and 0x1A. See “Auto Calibration Procedure” for further details.




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DRV2605


Real-Time Playback Input (Address: 0x02)

Bit 7 6 5 4 3 2 1 0Function RTP_Input[7] RTP_Input[6] RTP_Input[5] RTP_Input[4] RTP_Input[3] RTP_Input[2] RTP_Input[1] RTP_Input[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

RTP_Input[7:0] This is the entry point for Real-Time Playback (RTP) data. The DRV2605 playback engine willdrive the RTP_Input value to the load when Mode = 5 (RTP Mode). The RTP_Input value maybe updated on the fly by the host controller to create haptic waveforms. The RTP_Input valueis interpreted as signed by default, but may be set to unsigned by DataFormat_RTP. When thehaptic waveform is complete, the user may park the device by setting Mode = 0, oralternatively by setting STANDBY = 1.

spacer

Library Selection (Address: 0x03)

Bit 7 6 5 4 3 2 1 0Function HiZ LibrarySel[2] LibrarySel[1] LibrarySel[0]Type R/W R/W R/W R/WDefault 0 0 0 0

HiZ HiZ This bit sets the output driver into a true high-impedance state. The device must beenabled to go into the high-impedance state. When in hardware shutdown or standby mode,the output drivers have 15 kΩ to ground. When HiZ is asserted, it takes effect immediately,even if a transaction is taking place.

LibrarySel[2:0] Waveform library selection value. This determines which library the playback engine goes towhen the GO bit is set.

0: Empty (default)

1: TS2200 Library A – With overdriveDesigned with 3V overdrive for a 1.3V rated ERM. Open loop mode required.Rise Time: 40 ms to 60 ms

2: TS2200 Library B – For fast, light actuatorsRise Time: 40 ms to 60 ms

3: TS2200 Library CRise Time: 60 ms to 80 ms

4: TS2200 Library DRise Time: 100 ms to 140 ms

5: TS2200 Library ERise Time: > 140 ms

6: LRA Library7: Reserved




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DRV2605


Waveform Sequencer (Address: 0x04 to 0x0B)

Bit 7 6 5 4 3 2 1 0

Function Wait WavfrmSeq[6] WavfrmSeq[5] WavfrmSeq[4] WavfrmSeq[3] WavfrmSeq[2] WavfrmSeq[1] WavfrmSeq[0]

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

Wait When this bit [7] is set, bits [6:0] are interpreted as a “wait time” in which the playbackengine will idle. This is used to insert timed delays between sequentially played waveforms.Delay time is 10 ms * WavefrmSeq[6:0]. If Wait = 0, then WavfrmSeq[6:0] is interpreted asa waveform identifier for sequence playback.

WavfrmSeq[6:0] Waveform Sequence value. Holds the waveform identifier of the waveform to be played. Awaveform identifier is an integer value referring to the index position of a waveform in aROM library. Playback begins at register address 0x04 when the user asserts the GO bit(Register 0x0C). When playback of that waveform ends, the waveform sequencer plays thenext waveform identifier held in register 0x05, if it is non-zero. The waveform sequencercontinues in this fashion until it reaches an identifier value of zero, or all eight identifiers areplayed (register addresses 0x04 through 0x0B), whichever comes first.

GO (Address: 0x0C)

Bit 7 6 5 4 3 2 1 0Function GOType R/WDefault 0

GO Used to fire processes in the DRV2605. The process the GO bit fires is selected by the Mode[2:0] value(Register 0x01). Its primary function is to fire playback of the waveform identifiers in the waveformsequencer (Registers 0x04 to 0x0B), in which case, it can be thought of a “software trigger” for hapticwaveforms. The GO bit remains high until the playback of the haptic waveform sequence is complete.Clearing the GO bit during waveform playback cancels the waveform sequence. Using one of theexternal trigger modes can cause the GO bit to be set or cleared by the external trigger pin. It can alsobe used to fire the auto calibration process or the diagnostic process.

OverDrive Time Offset (Address: 0x0D)

Bit 7 6 5 4 3 2 1 0Function ODT[7] ODT[6] ODT[5] ODT[4] ODT[3] ODT[2] ODT[1] ODT[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

ODT[7:0] Adds a time offset to the overdrive portion of the library waveforms. Some motors require moreoverdrive time than others, so this register allows the user to add or take away overdrive time fromthe library waveforms. The maximum voltage value in the library waveform is automaticallydetermined to be the overdrive portion. This register will only be useful in open loop mode.Overdrive is automatic for closed loop mode. The offset is interpreted as two’s complement, so thetime offset may be positive or negative. OverDrive Time Offset (ms) = ODT[7:0] × 5




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DRV2605


Sustain Time Offset, Positive (Address: 0x0E)

Bit 7 6 5 4 3 2 1 0Function SPT[7] SPT[6] SPT[5] SPT[4] SPT[3] SPT[2] SPT[1] SPT[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

SPT[7:0] Adds a time offset to the positive sustain portion of the library waveforms. Some motors havefaster/slower response time than others, so this register allows the user to add or take awaypositive sustain time from the library waveforms. Any positive voltage value other than theoverdrive portion will be considered a sustain positive value. The offset is interpreted as two’scomplement, so the time offset may be positive or negative.Sustain Time Positive Offset (ms) = SPT[7:0] × 5

Sustain Time Offset, Negative (Address: 0x0F)

Bit 7 6 5 4 3 2 1 0Function SNT[7] SNT[6] SNT[5] SNT[4] SNT[3] SNT[2] SNT[1] SNT[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

SNT[7:0] Adds a time offset to the negative sustain portion of the library waveforms. Some motors havefaster/slower response time than others, so this register allows the user to add or take awaynegative sustain time from the library waveforms. Any negative voltage value other than theoverdrive portion will be considered a sustain negative value. The offset is interpreted as two’scomplement, so the time offset may be positive or negative.Sustain Time Negative Offset (ms) = SNT[7:0] × 5

Brake Time Offset (Address: 0x10)

Bit 7 6 5 4 3 2 1 0Function BRT[7] BRT[6] BRT[5] BRT[4] BRT[3] BRT[2] BRT[1] BRT[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

BRT[7:0] Adds a time offset to the braking portion of the library waveforms. Some motors require morebraking time than others, so this register allows the user to add or take away brake time from thelibrary waveforms. The most negative voltage value in the library waveform is automaticallydetermined to be the braking portion. This register will only be useful in open loop mode. Braking isautomatic for closed loop mode. The offset is interpreted as two’s complement, so the time offsetmay be positive or negative.




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DRV2605


Audio To Haptics Control (Address: 0x11)

Bit 7 6 5 4 3 2 1 0

Function ATH_PeakTime[1] ATH_PeakTime[0] ATH_Filter[1] ATH_Filter[0]

Type R/W R/W R/W R/W

Default 0 1 0 1

Audio To Haptics Minimum Input Level (Address: 0x12)

Bit 7 6 5 4 3 2 1 0

Function ATH_MinInput[7] ATH_MinInput[6] ATH_MinInput[5] ATH_MinInput[4] ATH_MinInput[3] ATH_MinInput[2] ATH_MinInput[1] ATH_MinInput[0]


Default 0 0 0 1 1 0 0 1

Audio To Haptics Maximum Input Level (Address: 0x13)

Bit 7 6 5 4 3 2 1 0

Function ATH_MaxInput[7] ATH_MaxInput[6] ATH_MaxInput[5] ATH_MaxInput[4] ATH_MaxInput[3] ATH_MaxInput[2] ATH_MaxInput[1] ATH_MaxInput[0]


Default 1 1 1 1 1 1 1 1




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DRV2605


Audio To Haptics Minimum Output Drive (Address: 0x14)

Bit 7 6 5 4 3 2 1 0

Function ATH_MinDrive[7] ATH_MinDrive[6] ATH_MinDrive[5] ATH_MinDrive[4] ATH_MinDrive[3] ATH_MinDrive[2] ATH_MinDrive[1] ATH_MinDrive[0]


Default 0 0 0 1 1 0 0 1

Audio To Haptics Maximum Output Drive (Address: 0x15)

Bit 7 6 5 4 3 2 1 0

Function ATH_MaxDrive[7] ATH_MaxDrive[6] ATH_MaxDrive[5] ATH_MaxDrive[4] ATH_MaxDrive[3] ATH_MaxDrive[2] ATH_MaxDrive[1] ATH_MaxDrive[0]


Default 1 1 1 1 1 1 1 1

Rated Voltage (Address: 0x16)

Bit 7 6 5 4 3 2 1 0

Function RatedVoltage[7] RatedVoltage[6] RatedVoltage[5] RatedVoltage[4] RatedVoltage[3] RatedVoltage[2] RatedVoltage[1] RatedVoltage[0]


Default 0 0 1 1 1 1 1 1

RatedVoltage[7:0] Sets the reference voltage for full-scale output during closed loop operation. The autocalibration routine uses this register as an input, so this register must be written with themotor’s rated voltage value before calibration is performed. This register is ignored foropen-loop operation, since the overdrive voltage sets the reference for that case. Anymodification of this register value should be followed by calibration to set ACalBEMFappropriately.See "Programming the Rated Voltage" for calculating the correct register value.

Overdrive Clamp Voltage (Address: 0x17)

Bit 7 6 5 4 3 2 1 0Function ODClamp[7] ODClamp[6] ODClamp[5] ODClamp[4] ODClamp[3] ODClamp[2] ODClamp[1] ODClamp[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 1 0 0 0 1 0 0 1

ODClamp[7:0] During closed loop operation, the actuator feedback lets the output voltage go above the ratedvoltage during the automatic overdrive and automatic braking periods. This register sets aclamp so that the automatic overdrive is bounded. This also serves as the full scale referencevoltage for open loop operation.See "Programming the Overdrive Clamp Voltage" for calculating the correct register value.




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DRV2605


Auto Calibration Compensation Result (Address: 0x18)

Bit 7 6 5 4 3 2 1 0

Function ACalComp[7] ACalComp[6] ACalComp[5] ACalComp[4] ACalComp[3] ACalComp[2] ACalComp[1] ACalComp[0]


Default 0 0 0 0 1 1 0 1

ACalComp[7:0] Contains the voltage compensation result after execution of auto calibration. This valuecompensates for any resistive losses in the driver. The calibration routine checks theimpedance of the actuator to automatically determine an appropriate value. The autocalibration compensation result value is multiplied by the drive gain during playback.Auto Calibration Compensation Coefficient = 1 + ACalComp[7:0] / 255

Auto Calibration Back-EMF Result (Address: 0x19)

Bit 7 6 5 4 3 2 1 0

Function ACalBEMF[7] ACalBEMF[6] ACalBEMF[5] ACalBEMF[4] ACalBEMF[3] ACalBEMF[2] ACalBEMF[1] ACalBEMF[0]


Default 0 1 1 0 1 1 0 1

ACalBEMF[7:0] Contains the rated back-EMF result after execution of auto calibration. This is the level ofback-EMF voltage that the actuator gives when it is driven at its rated voltage. TheDRV2605 playback engine uses this value to automatically determine the appropriatefeedback gain for closed loop operation.Auto Calibration Back-EMF (V) = (ACalBEMF[7:0] / 255) × 4.88 V / BEMFGain




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DRV2605


Feedback Control (Address: 0x1A)

Bit 7 6 5 4 3 2 1 0

Function nERM_LRA FBBrakeFactor[2] FBBrakeFactor[1] FBBrakeFactor[0] LoopResponse[1] LoopResponse[0] BEMFGain[1] BEMFGain[0]


Default 0 0 1 1 0 1 1 0

nERM_LRA Sets the DRV2605 in ERM or LRA mode. This bit should be set prior to running autocalibration.

0: ERM Mode (default)1: LRA Mode

FBBrakeFactor[2:0] Selects the feedback gain ratio between braking gain and driving gain. In general, it isdesirable to add additional feedback gain while braking, so that the actuator will brake asquickly as possible. Large ratios give less stable operation than lower ones. Theadvanced user may choose to optimize this register. Otherwise, the default value shouldgive good performance for most actuators. This value should be set prior to running autocalibration.

0: 1x1: 2x2: 3x3: 4x (default)4: 6x5: 8x6: 16x7: Braking disabled

LoopGain[1:0] Selects a loop gain for the feedback control. This sets how fast the loop tries to make theback-EMF (and thus motor velocity) match the input signal level. Higher loop gain (fastersettling) options will give less stable operation than lower loop gain (slower settling). Theadvanced user may choose to optimize this register. Otherwise, the default value shouldgive good performance for most actuators. This value should be set prior to running autocalibration.

0: Low1: Medium (default)2: High3: Very High

BEMFGain[1:0] Sets the analog gain of the back-EMF amplifier. This value is interpreted differentlybetween ERM mode and LRA mode. Auto calibration will automatically populateBEMFGain with the most appropriate value for the actuator.ERM Mode

0: 0.33x1: 1.0x2: 1.8x (default)3: 4.0x

LRA Mode0: 5x1:10x2: 20x (default)3: 30x




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DRV2605


Control1 (Address: 0x1B)

Bit 7 6 5 4 3 2 1 0

Function StartupBoost AC_Couple DriveTime[4] DriveTime[3] DriveTime[2] DriveTime[1] DriveTime[0]

Type R/W R/W R/W R/W R/W R/W R/W

Default 1 0 1 0 0 1 1

StartupBoost Applies higher loop gain during overdrive to enhance actuator transient response.

AC_Couple Applies a 0.9V common mode voltage to the IN/TRIG pin when an AC coupling capacitor isused. This is only useful for analog input mode. This should not be asserted for PWM modeor external trigger mode.

0: Common-mode drive disabled for DC coupling or digital inputs modes1: Common-mode drive enabled for AC coupling

DriveTime[4:0] LRA Mode: Sets initial “guess” for LRA drive time in LRA mode. Drive time is automaticallyadjusted for optimum drive on the fly; however, this register should be optimized for theapproximate LRA frequence. If it is set too low, it may affect the actuator startup time. If it isset too high, it may cause instability. Optimum Drive Time (ms) ≈ 0.5 × LRA PeriodDrive Time (ms) = DriveTime[4:0] × 0.1 ms + 0.5 ms

ERM Mode: Sets the sample rate for the back-EMF detection. Lower drive times causehigher peak-to-average ratios in the output signal, requiring more supply headroom. Higherdrive times cause the feedback to react at a slower rate.Drive Time (ms) = DriveTime[4:0] × 0.2 ms + 1 ms




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DRV2605


Control2 (Address: 0x1C)

Bit 7 6 5 4 3 2 1 0

Function BiDir_Input BrakeStabilizer SampleTime[1] SampleTime[0] BlankingTime[1] BlankingTime[0] IDissTime[1] IDissTime[0]


Default 1 1 1 1 0 1 0 1

BiDir_Input Selects the input scaling the playback engine expects.0: Uni-directional Input Mode

Braking is automatically determined by the feedback conditions, and applied when needed. Use of thismode also recovers an additional bit of vertical resolution. This mode should only be used for closed-loop operation.Examples0% Input → No output signal50% Input → Half-scale output signal100% Input → Full-scale output signal

1: Bi-directional Input Mode (default)This mode is compatible with traditional open-loop signaling, and also works well with closed-loop mode.When operating closed-loop, braking is automatically determined by the feedback conditions, andapplied when needed. When operating open-loop modes, braking is only applied when the input signalis less than 50%.Open Loop Mode (ERM and LRA) Examples0% Input → Negative full-scale output signal (braking)25% Input → Negative half-scale output signal (braking)50% Input → No output signal75% Input → Positive half-scale output signal100% Input → Positive full-scale output signalClosed Loop Mode (ERM and LRA) Examples0% to 50% Input → No output signal50% Input → No output signal75% Input → Half-scale output signal100% Input → Full-scale output signal

BrakeStabilizer Reduces loop gain when braking is near completion to improve loop stability

SampleTime[1:0] LRA Auto Resonance Sampling Time. (Advanced use only)0: 150 µs 2: 250 µs1: 200 µs 3: 300 µs (default)

BlankingTime[1:0] Blanking time before the back-EMF A/D makes a conversion. (Advanced use only)0: 15 µs (LRA), 45 µs (ERM) 2: 50 µs (LRA), 150 µs (ERM)1: 25 µs (LRA), 75 µs (ERM), default 3: 75 µs (LRA), 225 µs (ERM)

IDissTime[1:0] Current Dissipation Time. This is the time allowed for the current to dissipate from the actuator between PWMcycles for flyback mitigation. (Advanced use only)

0: 15 µs (LRA), 45 µs (ERM) 2: 50 µs (LRA), 150 µs (ERM)1: 25 µs (LRA), 75 µs (ERM), default 3: 75 µs (LRA), 225 µs (ERM)




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DRV2605


Control3 (Address: 0x1D)

Bit 7 6 5 4 3 2 1 0

Function NG_Thresh[1] NG_Thresh[0] ERM_OpenLoop SupplyCompDis DataFormat_RTP LRADriveMode nPWM_Analog LRA_OpenLoop


Default 1 0 0 0 0 0 0 0

NG_Thresh[1:0] Noise gate threshold for PWM and analog inputs.0: Disabled1: 2%2: 4% (Default)3: 8%

ERM_OpenLoop Selects mode of operation while in ERM mode. Closed loop operation is usually desired forits automatic overdrive and braking properties. However, many existing waveform librarieswere designed for open loop operation, so open-loop operation may be required forcompatibility.

0: Closed Loop (Default)1: Open Loop

SupplyCompDis Disables supply compensation. The DRV2605 normally gives constant drive output overvariation in the power supply input (VDD). In some systems supply compensation mayhave already been implemented upstream, so it may be useful to disable the DRV2605supply compensation.

0: Supply Compensation Enabled (Default)1: Supply Compensation Disabled

DataFormat_RTP Selects the input data interpretation for RTP (Real-Time Playback) mode.0: Signed (Default)1: Unsigned

LRADriveMode Selects the drive mode for the LRA algorithm. This determines how often the driveamplitude is updated. Updating once per cycle gives a symmetrical output signal, whileupdating twice per cycle gives more precise control.

0: Once per cycle (Default)1: Twice per cycle

nPWM_Analog Selects input mode for the IN/TRIG pin when Mode[2:0] = 3.0: PWM Input (Default)1: Analog Input

LRA_OpenLoop Selects an Open Loop drive option for LRA Mode. When asserted, the playback enginerecovers the LRA commutation frequency from the PWM input, dividing it by 128; therefore,this mode is only compatible with PWM input mode, and does not work with any othermode. The PWM input frequency must be equal to 128 times the resonant frequency of theLRA.

0: Auto Resonance Mode (Default)1: Divide-by-128x Mode




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DRV2605


Auto Calibration Memory Interface (Address: 0x1E)

Bit 7 6 5 4 3 2 1 0Function AutoCalTime[1] AutoCalTime[0] OTP_Status OTP_ProgramType R/W R/W RO R/WDefault 1 0 0 0

AutoCalTime [1:0] Sets the length of the auto calibration time. This should be enough time for the motoracceleration to settle when driven at the RatedVoltage[7:0] value.

0: 150 ms (min), 350 ms (max)1: 250 ms (min), 450 ms (max)2: 500 ms (min), 700 ms (max), Default3: 1000 ms (min), 1200 ms (max)

OTP_Status OTP Memory has been programmed

OTP_Program Launches the One-Time Programmable (OTP) Memory programming process, whichprograms the contents of register 0x16 through 0x1A into non-volatile memory. Thisprocess can only be executed one time per device. See “Auto Calibration Memory”section for further details.

VBAT Voltage Monitor (Address: 0x21)

Bit 7 6 5 4 3 2 1 0Function VBAT[7] VBAT[6] VBAT[5] VBAT[4] VBAT[3] VBAT[2] VBAT[1] VBAT[0]Type R/W R/W R/W R/W R/W R/W R/W R/WDefault 0 0 0 0 0 0 0 0

VBAT[7:0] Gives a real time reading of the supply voltage at the VDD terminal. Device must be activelysending a waveform to take a reading.VDD (V) = VBAT[7:0] × 5.6V / 255

LRA Resonance Period (Address: 0x22)

Bit 7 6 5 4 3 2 1 0

Function LRA_Period[7] LRA_Period[6] LRA_Period[5] LRA_Period[4] LRA_Period[3] LRA_Period[2] LRA_Period[1] LRA_Period[0]


Default 0 0 0 0 0 0 0 0

LRA_Period[7:0] Reports the measurement of the LRA resonance period. Device must be actively sending awaveform to take a reading.LRA Period (us) = LRA_Period[7:0] × 98.46 µs




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( )AVG _ ABS

LRA

1RMSV V

1- 4SampleTime 300 f=

+ sm

AVG _ ABS

5.28 VV Rated Voltage [7 : 0]

255=

AVG

5.36 VV Rated Voltage [7 : 0]

255=

DRV2605


DEVICE PROGRAMMING

PROGRAMMING THE RATED VOLTAGEThe RatedVoltage[7:0] value (Register 0x16) is used to set the full scale voltage for the closed-loop drive modes.The auto calibration routine uses this register as an input, so this register must be written with the motor’s ratedvoltage value before calibration is performed. This register is ignored for open-loop operation, since theoverdrive voltage sets the reference for that case. Any modification of this register value should be followed bycalibration to set ACalBEMF appropriately. See "Modes Of Operation" for more details on how this value is used.

ERM Mode (Closed Loop)Equation 1 gives the average steady-state voltage when a full-scale input signal is provided.

(1)

LRA Mode (Closed Loop)Equation 2 gives the average of the absolute value of the LRA drive voltage when driven to steady state with afull-scale input signal.

(2)

And Equation 3 converts the average of the absolute value obtained in Equation 2 to the steady-state RMSvoltage.

(3)

Default Values:SampleTime = 300 µsfLRA = 175 HzVRMS = 1.16 VAVG_ABS (with default values)




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( )RMS PEAK LRAV V 1 800 s f= - m

PEAK

5.44VV ODClamp[7 : 0]

255=

AVG PEAK

(DriveTime - 300 s)V V

DriveTime IDissTime BlankingTime

m=

+ +

PEAK

5.44 VV ODClamp[7 : 0]

255=

OD

5.6 VV ODClamp[7 : 0]

255=

DRV2605


PROGRAMMING THE OVERDRIVE CLAMP VOLTAGEDuring closed loop operation, the actuator feedback lets the output voltage go above the rated voltage during theautomatic overdrive and automatic braking periods. The ODClamp[7:0] value (Register 0x17) sets a clamp sothat the automatic overdrive is bounded. This also serves as the full scale reference voltage for open loopoperation. The ODClamp[7:0] value always represents the peak voltage that is allowed, regardless of the mode.Note that if the supply voltage (VDD) is less than the overdrive clamp voltage, the output driver will not be able toreach the clamp voltage value because the output voltage cannot exceed the supply voltage. Also note that if therated voltage exceeds the overdrive clamp voltage, the overdrive clamp voltage will supercede.

LRA Mode (Closed Loop) and ERM Mode (Open Loop)Equation 4 is the peak voltage allowed during all modes of operation.

(4)

ERM Mode (Closed Loop)Although Equation 5 gives the peak voltage for the overdrive clamp, it is desirable in ERM mode to know theaverage voltage obtained when clamped. The closed loop mode periodically samples the actuator back EMF.During this time, the driver is not applying voltage to the actuator. To achieve equivalent performance betweenthe open loop and closed loop modes, it is useful to relate the peak clamp voltage to the average voltage. Thisrelationship is given by Equation 6.

(5)

(6)

Default Values:DriveTime = 4.8 msIDissTime = BlankingTime = 75 µsVAVG = 0.91 VPEAK (with default values)

LRA Mode (Open Loop)The ODClamp[7:0] value sets the peak value when open loop LRA mode is used. Please note that LRA OpenLoop Mode can only be used with PWM inputs.

(7)

The VRMS value can be calculated from the peak value using the following equation:

(8)




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DRV2605


AUTO CALIBRATION PROCEDURE1. Determine parameters for selected actuator

(a) Type: ERM or LRA(b) Rated voltage(c) Allowed overdrive voltage

2. Apply the supply voltage to the DRV2605. The supply voltage should allow adequate drive voltage for theselected actuator.

3. Write a value of 0x07 to register 0x01. This will take the DRV2605 out of STANDBY and place the Mode[2:0]bits in auto calibration mode.

4. Write the nERM_LRA, FBBrakeFactor and LoopResponse values to register 0x1A. The BEMFGain bits willbe populated automatically by the auto calibration algorithm. Default values for register 0x1A that work formost actuators are 0x24 for ERM and 0xA4 for LRA.

5. Write the actuator rated voltage to register 0x16 using the formula:See "Programming the Rated Voltage" for calculating the correct register value.

6. Write the actuator overdrive clamp voltage to register 0x17 using the formula:See "Programming the Overdrive Clamp Voltage" for calculating the correct register value.

7. Set the GO bit to start the auto calibration process (Write a value of 0x01 to register 0x0C). When autocalibration is complete, the GO bit will self-clear. The auto calibration duration can be adjusted withAutoCalTime[1:0]. The auto calibration results will be written to ACalComp[7:0], ACalBEMF[7:0], andBEMFGain[1:0].

8. Check the status of the Diag_Result bit to ensure that the auto calibration routine completed without faults.9. Evaluate system performance with the auto calibrated settings. Note that the evaluation should be done in

the final assembly of the product, as this can affect actuator performance/behavior. If any adjustment isneeded, steps 4 through 8 can be repeated. If the performance is satisfactory, the user may choose to doany of the following:(a) Repeat the calibration process upon subsequent power ups.(b) Store the auto calibration results in host processor memory and rewrite them to the DRV2605 upon

subsequent power ups. The DRV2605 remembers these settings when in STANDBY mode or when ENis low.

(c) Permanently program the results in non-volatile, on-chip auto calibration memory. Even when theDRV2605 is power cycled, it will remember the auto calibration settings. This procedure is described inthe following section.

AUTO CALIBRATION MEMORYThe DRV2605 contains non-volatile, on-chip, One-Time Programmable (OTP) auto calibration memory for theauto calibration specific parameters. Once written, the DRV2605 remembers the device settings in registers 0x16through 0x1A even after power cycling. This allows the user to account for small variations in actuatormanufacturability from unit to unit as well as shorten the device initialization process for product specificparameters such as actuator type, actuator rated voltage, etc. An additional benefit is that the DRV2605 memorycan be customized at the product test level without driving changes in the product software.

To permanently program the auto calibration memory, use the following steps:1. Complete the auto calibration process described in the “Auto Calibration Procedure”. Ensure that the

performance is satisfactory, since this procedure is permanent and can only be completed once.2. Ensure that the supply voltage (VDD) is between 4.0 V and 4.4 V. This voltage is required for the non-volatile

memory to program properly.3. Set the OTP_Launch bit by writing a value of 0x01 to register 0x1E. Once the OTP memory has been

written, the OTP_Status bit will read 1.4. Reset the device by power cycling or setting Dev_Reset. Read register 0x16 to 0x1A to ensure that the

programmed values were retained.




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DRV2605


TYPICAL USAGE EXAMPLESInitialization Procedure1. After power up, wait at least 250 µs before the DRV2605 will accept I2C commands.2. Assert the EN pin (logic high). The EN pin may be asserted any time during or after the 250 µs wait period.3. Write the MODE register (address 0x01) to value 0x00 to take the device out of STANDBY mode.4. If the non-volatile, auto-calibration memory has been programmed as described in the previous section, skip

to step 6.5. Perform the steps as described in "Auto Calibration Procedure". Alternatively, rewrite the results from a

previous calibration. Registers that should be written in this step are Rated Voltage (0x16), Overdrive ClampVoltage (0x17), Auto Calibration Compensation (0x18), Auto Calibration Back-EMF (0x19), and FeedbackControl (0x1A). Note: If only Open Loop operation is used, the Auto Calibration Back-EMF and FeedbackControl [6:0] need not be written. Feedback Control [7] should be written to select ERM or LRA mode.

6. If using the embedded ROM library, write the Library Selection register (address 0x03) to choose a library.7. The default setup is closed-loop, bi-directional mode. To use other modes and features, write Control1

(0x1B), Control2 (0x1C), and Control3 (0x1D) as necessary. Open Loop operation is recommended for ERMmode when using the ROM libraries. See Register Map and "Modes of Operation" in the applicationinformation for details.

8. Put the device in STANDBY or de-assert the EN pin, whichever is most convenient. Both are low powermodes. The user may select the desired MODE (address 0x01) at the same time the STANDBY bit is set.

Play a Waveform or Waveform Sequence from ROM Waveform Memory1. Initialize the device as shown in "Initialization Procedure".2. Assert the EN pin (active high) if it was previously de-asserted.3. Select the desired MODE value of 0 (internal trigger), 1 (external edge trigger), or 2 (external level trigger) in

the MODE register (address 0x01). If the STANDBY bit was previously asserted, it should be de-asserted(logic low) at this time. If register 0x01 already holds the desired value and the STANDBY bit is low, this stepmay be skipped.

4. Select the waveform index to be played and write it to address 0x04. Alternatively, a sequence of waveformindices may be written to register 0x04 through 0x0B. See "Waveform Sequencer" in the applicationinformation for details.

5. If using the internal trigger mode, set the GO bit (address 0x0C, bit 0) to fire the effect or sequence ofeffects. If using an external trigger mode, send an appropriate trigger pulse to the IN/TRIG pin. See "InputTrigger Options" in the application information for details.

6. If desired, the user may repeat step 5 to fire the effect or sequence again.7. Put the device in low power mode by de-asserting EN or setting the STANDBY bit.

Play a Real-Time Playback (RTP) Waveform1. Initialize the device as shown in "Initialization Procedure".2. Assert the EN pin (active high) if it was previously de-asserted.3. Set the MODE value to 5 (RTP Mode) at address 0x01. If the STANDBY bit was previously asserted, it

should be de-asserted (logic low) at this time. If register 0x01 already holds the desired value and theSTANDBY bit is low, this step may be skipped.

4. Write the desired drive amplitude to the Real Time Playback Input register (address 0x02). See "Modes ofOperation" for drive amplitude scaling.

5. Once the desired sequence of drive amplitudes is complete, put the device in low power mode by de-asserting EN or setting the STANDBY bit.




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DRV2605


Play a PWM or Analog Input Waveform1. Initialize the device as shown in "Initialization Procedure".2. Assert the EN pin (active high) if it was previously de-asserted.3. Set the MODE value to 3 (PWM/Analog Mode) at address 0x01. If the STANDBY bit was previously

asserted, it should be de-asserted (logic low) at this time. If register 0x01 already holds the desired value andthe STANDBY bit is low, this step may be skipped.

4. Select the input mode (PWM or Analog) in the Control3 register (address 0x1D). If this was chosen duringthe initialization procedure, this step may be skipped.

5. Send the desired PWM/Analog input waveform sequence from the external source. See "Modes ofOperation" for drive amplitude scaling.

6. Once the desired drive sequence is complete, put the device in low power mode by de-asserting EN orsetting the STANDBY bit.




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DRV2605


WAVEFORM LIBRARY EFFECTS LIST

Effect ID# Waveform Name Effect ID# Waveform Name Effect ID# Waveform Name

1 Strong Click - 100% 42 Long Double Sharp Click Medium 2 – 80% 83 Transition Ramp Up Long Smooth 2 – 0 to 100%

2 Strong Click - 60% 43 Long Double Sharp Click Medium 3 – 60% 84 Transition Ramp Up Medium Smooth 1 – 0 to 100%

3 Strong Click - 30% 44 Long Double Sharp Tick 1 – 100% 85 Transition Ramp Up Medium Smooth 2 – 0 to 100%

4 Sharp Click - 100% 45 Long Double Sharp Tick 2 – 80% 86 Transition Ramp Up Short Smooth 1 – 0 to 100%

5 Sharp Click - 60% 46 Long Double Sharp Tick 3 – 60% 87 Transition Ramp Up Short Smooth 2 – 0 to 100%

6 Sharp Click - 30% 47 Buzz 1 – 100% 88 Transition Ramp Up Long Sharp 1 – 0 to 100%

7 Soft Bump - 100% 48 Buzz 2 – 80% 89 Transition Ramp Up Long Sharp 2 – 0 to 100%

8 Soft Bump - 60% 49 Buzz 3 – 60% 90 Transition Ramp Up Medium Sharp 1 – 0 to 100%

9 Soft Bump - 30% 50 Buzz 4 – 40% 91 Transition Ramp Up Medium Sharp 2 – 0 to 100%

10 Double Click - 100% 51 Buzz 5 – 20% 92 Transition Ramp Up Short Sharp 1 – 0 to 100%

11 Double Click - 60% 52 Pulsing Strong 1 – 100% 93 Transition Ramp Up Short Sharp 2 – 0 to 100%

12 Triple Click - 100% 53 Pulsing Strong 2 – 60% 94 Transition Ramp Down Long Smooth 1 – 50 to 0%

13 Soft Fuzz - 60% 54 Pulsing Medium 1 – 100% 95 Transition Ramp Down Long Smooth 2 – 50 to 0%

Transition Ramp Down Medium Smooth 1 – 50 to14 Strong Buzz - 100% 55 Pulsing Medium 2 – 60% 96 0%

Transition Ramp Down Medium Smooth 2 – 50 to15 750 ms Alert 100% 56 Pulsing Sharp 1 – 100% 97 0%

16 1000 ms Alert 100% 57 Pulsing Sharp 2 – 60% 98 Transition Ramp Down Short Smooth 1 – 50 to 0%

17 Strong Click 1 - 100% 58 Transition Click 1 – 100% 99 Transition Ramp Down Short Smooth 2 – 50 to 0%

18 Strong Click 2 - 80% 59 Transition Click 2 – 80% 100 Transition Ramp Down Long Sharp 1 – 50 to 0%

19 Strong Click 3 - 60% 60 Transition Click 3 – 60% 101 Transition Ramp Down Long Sharp 2 – 50 to 0%

20 Strong Click 4 - 30% 61 Transition Click 4 – 40% 102 Transition Ramp Down Medium Sharp 1 – 50 to 0%

21 Medium Click 1 - 100% 62 Transition Click 5 – 20% 103 Transition Ramp Down Medium Sharp 2 – 50 to 0%

22 Medium Click 2 - 80% 63 Transition Click 6 – 10% 104 Transition Ramp Down Short Sharp 1 – 50 to 0%

23 Medium Click 3 - 60% 64 Transition Hum 1 – 100% 105 Transition Ramp Down Short Sharp 2 – 50 to 0%

24 Sharp Tick 1 - 100% 65 Transition Hum 2 – 80% 106 Transition Ramp Up Long Smooth 1 – 0 to 50%

25 Sharp Tick 2 - 80% 66 Transition Hum 3 – 60% 107 Transition Ramp Up Long Smooth 2 – 0 to 50%

26 Sharp Tick 3 – 60% 67 Transition Hum 4 – 40% 108 Transition Ramp Up Medium Smooth 1 – 0 to 50%

27 Short Double Click Strong 1 – 100% 68 Transition Hum 5 – 20% 109 Transition Ramp Up Medium Smooth 2 – 0 to 50%

28 Short Double Click Strong 2 – 80% 69 Transition Hum 6 – 10% 110 Transition Ramp Up Short Smooth 1 – 0 to 50%

Transition Ramp Down Long Smooth 1 –29 Short Double Click Strong 3 – 60% 70 111 Transition Ramp Up Short Smooth 2 – 0 to 50%100 to 0%

Transition Ramp Down Long Smooth 2 –30 Short Double Click Strong 4 – 30% 71 112 Transition Ramp Up Long Sharp 1 – 0 to 50%100 to 0%

Transition Ramp Down Medium Smooth 1 –31 Short Double Click Medium 1 – 100% 72 113 Transition Ramp Up Long Sharp 2 – 0 to 50%100 to 0%

Transition Ramp Down Medium Smooth 2 –32 Short Double Click Medium 2 – 80% 73 114 Transition Ramp Up Medium Sharp 1 – 0 to 50%100 to 0%

Transition Ramp Down Short Smooth 1 –33 Short Double Click Medium 3 – 60% 74 115 Transition Ramp Up Medium Sharp 2 – 0 to 50%100 to 0%

Transition Ramp Down Short Smooth 2 –34 Short Double Sharp Tick 1 – 100% 75 116 Transition Ramp Up Short Sharp 1 – 0 to 50%100 to 0%

Transition Ramp Down Long Sharp 1 – 10035 Short Double Sharp Tick 2 – 80% 76 117 Transition Ramp Up Short Sharp 2 – 0 to 50%to 0%

Transition Ramp Down Long Sharp 2 – 10036 Short Double Sharp Tick 3 – 60% 77 118 Long buzz for programmatic stopping – 100%to 0%

Long Double Sharp Click Strong 1 – Transition Ramp Down Medium Sharp 1 –37 78 119 Smooth Hum 1 (No kick or brake pulse) – 50%100% 100 to 0%

Long Double Sharp Click Strong 2 – Transition Ramp Down Medium Sharp 2 –38 79 120 Smooth Hum 2 (No kick or brake pulse) – 40%80% 100 to 0%

Long Double Sharp Click Strong 3 – Transition Ramp Down Short Sharp 1 – 10039 80 121 Smooth Hum 3 (No kick or brake pulse) – 30%60% to 0%

Long Double Sharp Click Strong 4 – Transition Ramp Down Short Sharp 2 – 10040 81 122 Smooth Hum 4 (No kick or brake pulse) – 20%30% to 0%

Long Double Sharp Click Medium 1 – Transition Ramp Up Long Smooth 1 – 0 to41 82 123 Smooth Hum 5 (No kick or brake pulse) – 10%100% 100%




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CopperTrace Width

Solder MaskThickness

SolderPad Width

Solder MaskOpening

Copper TraceThickness

DRV2605


PCB LAYOUT RECOMMENDATIONS

In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and theopening size is defined by the copper pad width. Figure 24 and Table 2 show the appropriate diameters for aWCSP layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layoutexample.

Figure 24. Land Pattern Dimensions

Table 2. Land Pattern DimensionsSOLDER PAD SOLDER MASK COPPER STENCIL STENCILCOPPER PADDEFINITIONS OPENING THICKNESS OPENING THICKNESS

Nonsolder mask 275 μm 375 μm 1 oz max (32 μm) 275 μm x 275 μm Sq. 125 μm thickdefined (NSMD) (+0.0, –25 μm) (+0.0, –25 μm) (rounded corners)

NOTES:1. Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside

the solder mask opening. Wider trace widths reduce device stand off and impact reliability.2. Recommend solder paste is Type 3 or Type 4.3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the

operating the range of the intended application.4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 μm to avoid a reduction in

thermal fatigue performance.5. Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically

etched stencils results in inferior solder paste volume control.7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional

component movement due to solder wetting forces.

Trace WidthRecommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCBtraces. Maintain this trace width until the ball pattern is escaped, then the trace width may be increased forimproved current flow. The width/length of the 75 μm to 100 μm traces should be as symmetrical as possiblearound the device to give even solder reflow on each of the balls.




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D 1.41 mm 1.47 mm

E 1.41 mm 1.47 mm

Min Max

DRV2605





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DRV2605


REVISION HISTORY

Changes from Revision A (March 2013) to Revision B Page

• Changed from 1 page data sheet to full data sheet in product folder .................................................................................. 1

Changes from Original (December 2012) to Revision A Page

• Changed |IIH| MAX value from 3 to 3.5µA per CMS #C1303020 .......................................................................................... 4




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PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

DRV2605YZFR ACTIVE DSBGA YZF 9 3000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 2605

DRV2605YZFT ACTIVE DSBGA YZF 9 250 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 2605

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

http://www.ti.com/product/DRV2605?CMP=conv-poasamples#samplebuy

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PACKAGE OPTION ADDENDUM

www.ti.com 31-Jan-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DRV2605YZFR DSBGA YZF 9 3000 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1

DRV2605YZFR DSBGA YZF 9 3000 178.0 9.2 1.65 1.65 0.81 4.0 8.0 Q1

DRV2605YZFT DSBGA YZF 9 250 178.0 9.2 1.65 1.65 0.81 4.0 8.0 Q1

DRV2605YZFT DSBGA YZF 9 250 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV2605YZFR DSBGA YZF 9 3000 182.0 182.0 17.0

DRV2605YZFR DSBGA YZF 9 3000 270.0 225.0 227.0

DRV2605YZFT DSBGA YZF 9 250 270.0 225.0 227.0

DRV2605YZFT DSBGA YZF 9 250 182.0 182.0 17.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

Pack Materials-Page 2

D: Max =

E: Max =

1.47 mm, Min =

1.47 mm, Min =

1.41 mm

1.41 mm

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio www.ti.com/audio Automotive and Transportation www.ti.com/automotiveAmplifiers amplifier.ti.com Communications and Telecom www.ti.com/communicationsData Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computersDLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-appsDSP dsp.ti.com Energy and Lighting www.ti.com/energyClocks and Timers www.ti.com/clocks Industrial www.ti.com/industrialInterface interface.ti.com Medical www.ti.com/medicalLogic logic.ti.com Security www.ti.com/securityPower Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defenseMicrocontrollers microcontroller.ti.com Video and Imaging www.ti.com/videoRFID www.ti-rfid.comOMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.comWireless Connectivity www.ti.com/wirelessconnectivity

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