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<p>1</p> <p>STANFORD UNIVERSITY Department of Electrical Engineering Prof. Boris Murmann</p> <p>EE214: Analog Integrated Circuit Design- Autumn 2007/08 http://eeclass.stanford.edu/ee214/</p> <p>Table of ContentsIntroduction CMOS Technology, Long Channel MOS Model Common Source Amplifier Technology Characterization: gm/ID Technology Characterization: fT, gm/gds gm/ID-based Design Extrinsic Capacitance Miller Approximation, ZV Time Constant Analysis Electronic Noise Electronic Noise (Continued) Backgate Effect, Common Gate Stage Common Drain Stage Differential Pair Current Mirrors, Offset Voltage Process Variations, Feedback Fully Differential Amplifiers, SC Circuits Stability, Analysis of Feedback Circuits Loop Gain Simulation Two-Stage OTA Compensation, Noise in Feedback OTAs OTA Design Considerations Step Response Slewing Feedback and Port Impedances, OTA Variants Single Ended OTAs, Output Stage Examples Supply Insensitive Biasing Bandgap Reference Bandgap Reference (Continued) Technology Scaling Class Summary 3 10 16 30 42 56 68 85 96 109 118 130 141 152 165 175 185 197 209 218 233 258 275 285 298 307 317 323 332 348</p> <p>Lecture 1 Lecture 2 Lecture 3 Lecture 4 Lecture 5 Lecture 6 Lecture 7 Lecture 8 Lecture 9 Lecture 10 Lecture 11 Lecture 12 Lecture 13 Lecture 14 Lecture 15 Lecture 16 Lecture 17 Lecture 18 Lecture 19 Lecture 20 Lecture 21 Lecture 22 Lecture 23 Lecture 24 Lecture 25 Lecture 26 Lecture 27 Lecture 28 Lecture 29</p> <p>2</p> <p>3</p> <p>EE214 Analog Integrated Circuit Design</p> <p>Boris Murmann Stanford University murmann@stanford.eduCopyright 2007 by Boris Murmann</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>1</p> <p>A Few Words About Your Instructor Assistant Professor in EE since 2004 PhD, UC Berkeley 2003 Digitally assisted A/D conversion Use "minimalistic" analog circuits (low power, fast) Correct errors using digital post-processor ~ 4 years work experience in IC industry Mixed signal IC design, low power, high voltage Current research Digital correction techniques for data converters Sensor interfaces Circuit design in new technologies Post-CMOS devices, organic devicesB. Murmann EE 214 Introduction 2</p> <p>4</p> <p>EE214 Basics (1) Teaching assistants Mohammad Hekmat, Bob Wiser, Ross Walker Administrative support Ann Guerra, CIS 207 Lectures are televised But please come to class to keep the discussion interactive! Web page: http://eeclass.stanford.edu/ee214 Check regularly, especially bulletin board Register for online access to grades and solutions Only enrolled students can register; we manually control the access list based on Axess data</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>3</p> <p>EE214 Basics (2) Required text Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001. (On reserve in Engineering Library) Course prerequisites EE101B or equivalent Basic device physics and models PN junctions, MOSFETs, BJTs</p> <p> Basic linear systems Frequency response, poles, zeros</p> <p> Some exposure to a circuit simulator, basic Unix commands May consider concurrent enrollment in EE114X to brush up on the above (primarily for undergraduates)B. Murmann EE 214 Introduction 4</p> <p>5</p> <p>Assignments Homework (20%) Handed out on Mondays, due following Monday in class Late policy Score drops 0.5 dB per hour after deadline</p> <p> Lowest HW score will be dropped Policy for off-campus students: Fax/email to SCPD before deadline stated on handout Midterm Exam (30%) Project (20%) Design of an amplifier using HSpice (no layout) Work in teams of two OK to discuss with other teams, but no file exchange!</p> <p>Final Exam (30%)EE 214 Introduction 5</p> <p>B. Murmann</p> <p>Honor Code Please remember you are bound by the honor code I will trust you not to cheat I will try not to tempt you But if you are found cheating it is very serious There is a formal hearing You can be thrown out of Stanford Save yourself and me a huge hassle and be honest For more info http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/ honorcode.pdf</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>6</p> <p>6</p> <p>Be Reasonable When Asking TAs</p> <p>The TAs will not give you "the answer times two" They will also NOT debug your Spice deck Figuring out what's wrong with your circuit is an essential component of this class</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>7</p> <p>Circuit Simulation We will HSpice for circuit simulation You can use other tools at "own risk" "CAD Basics" document and example simulation files are provided on course web site and in course directory</p> <p>Plot HSpice results using Matlab ("HSpice Toolbox") Toolbox is installed in course directory See "CAD Basics" document for setup info</p> <p> Can download toolbox from Mike Perrott's homepage (MIT)</p> <p>EE214 Technology 0.35m CMOS BSIM3v3 models provided on web site and in course directory</p> <p>First review session (this week) will focus on simulation basics</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>8</p> <p>7</p> <p>The Spice Monkey Problem (1) What most people know Even a very large number of monkeys randomly arranging characters will never manage to write an interesting book What some people tend to forget Even a very large number of "Spice Monkeys" randomly tweaking circuits will never manage to design a robust, optimized IC</p> <p>[Courtesy Isaac Martinez]</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>9</p> <p>The Spice Monkey Problem (2) Simply put Spice is nothing but a "calculator" that lets you evaluate and test your ideas There is no need to simulate anything unless you already know the (approximate) answer! Must always be aware of modeling limitations Especially in the integrated circuits arena, uneducated, purely simulator driven design can be costly Mask sets cost up to $2 Million (90 nm production) Turnaround time is on the order of months If your chip doesn't work, you cannot simply send the customer a "patch"</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>10</p> <p>8</p> <p>Analysis versus Design Unlike common perception, analog circuit analysis and design is not "black magic" Circuit analysis The art of decomposing a circuit into manageable pieces Based on the simple, but sufficiently accurate model "Just-in-time" modeling; do not use a complex model unless you know why it's needed</p> <p> One circuit one solution Circuit design The art of synthesizing circuits based on experience from extensive analysis One set of specifications Many solutions Design skills are best acquired through "learning by doing" This is why we'll have a design projectB. Murmann EE 214 Introduction 11</p> <p>Learning Goals Develop deeper understanding of MOS device behavior relevant to analog design Develop a feel for limits and tradeoffs in analog circuits (speed, noise, power dissipation) Learn to bridge the gap between complex device models/behavior and basic hand calculations Design using look-up tables, "gm/ID methodology" Develop a systematic, non-spice-monkey design style Solidify the above aspects in a hands-on design project Design and optimization of a high performance feedback amplifier used in many industrial circuits/applications</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>12</p> <p>9</p> <p>Preview - Design Example of Lecture 20Cf Cs Vsd + CsM4a,b</p> <p>CL Vid + Vod CL Cf</p> <p>M1a,b</p> <p>M3a,b</p> <p>M2a,b</p> <p>Specs: Loop bandwidth (fc) = 200MHz Phase margin = 75 degrees DR = 72dB Closed-loop gain =2 Static gain error &lt; 0.5%</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>13</p> <p>Course Topics CMOS technology and device models Electronic noise Single-stage amplifiers Current mirrors, active loads Differential pairs Operational transconductance amplifiers (OTAs) Feedback, stability and compensation Temperature and supply independent biasing</p> <p>B. Murmann</p> <p>EE 214 Introduction</p> <p>14</p> <p>10</p> <p>Lecture 1 CMOS Technology Long Channel MOS Model</p> <p>Boris Murmann Stanford University murmann@stanford.eduCopyright 2007 by Boris Murmann</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>1</p> <p>Overview Reading 2.8 (MOS fabrication), 2.9 (Active MOS devices) 2.10.1 (Resistors), 2.10.2 (Capacitors) 1.1, 1.5.0, 1.5.1, 1.5.2, 1.5.3 (Large signal MOS model)</p> <p> Introduction In this first lecture, we will cover some of the background that positions EE214 as an introductory course on circuit design using CMOS technology. In the lectures to come, we will focus on the problem of amplifier design as a vehicle to establish a set of considerations that apply to more complex circuits and also other technologies. At first, we will review the "long channel model" of a MOS transistor. Driven by circuit examples, we will later augment this simple model to include additional effects that are relevant in practice.</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>2</p> <p>11</p> <p>The Big Picture</p> <p>Most modern electronic information processing systems rely on amplification of "small" physical signals E.g. signal from RF antenna, disk drive head, microphone, </p> <p>EE214 uses amplifiers as a vehicle to teach you the basics of analog integrated circuit analysis and design Material forms basis for other and/or more complex circuits</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>3</p> <p>Technological ProgressVacuum Tube 1906 Transistor 1947 Modern Discrete Transistors</p> <p>Integrated Circuit 1958</p> <p>Modern CMOS</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>4</p> <p>12</p> <p>45nm CMOS (Intel)</p> <p>Steve Cowden THE ORGONIAN July 2007</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>5</p> <p>Economics</p> <p>[European Nanotechnology Roadmap]</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>6</p> <p>13</p> <p>Future Applications</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>7</p> <p>Discrete vs. Integrated CircuitsDiscrete Audio Amplifier Integrated CMOS Audio Amplifier</p> <p>Minimize transistor count Devices usually don't match Arbitrary resistor values Capacitors 1pF10mF</p> <p> EE 214 Lecture 1</p> <p>"Unlimited" number of transistors Devices match well Keep resistors &lt; 10100k Keep capacitors &lt; 1050pF8</p> <p>B. Murmann</p> <p>14</p> <p>Modern Integrated Circuit Technologies</p> <p>ParameterDevice Speed Noise Transconductance Intrinsic gain</p> <p>CMOSHigh Poor Poor Poor</p> <p>Si BJTHigh Good Good Better</p> <p>SiGe BJTHigh Good Good Best</p> <p>Why use CMOS for analog integrated circuits? Low cost, driven by high volume digital ICs Integration with high density digital circuits BiCMOS tends to be expensive</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>9</p> <p>Basic MOS Operation (1)0V 0V VD (&gt;0V)</p> <p>0V</p> <p>With zero voltage at the gate, device is "off" Back-to-back reverse biased pn junctionsEE 214 Lecture 1 10</p> <p>B. Murmann</p> <p>15</p> <p>Basic MOS Operation (2)&gt;0</p> <p>With a positive gate bias applied, electrons are pulled toward the positive gate electrode Given a large enough bias, the electrons start to "invert" the surface (pn); a conductive channel forms Magic "threshold voltage" Vt (more later)EE 214 Lecture 1 11</p> <p>B. Murmann</p> <p>Basic Operation (3)ID=?</p> <p>&gt;0</p> <p>VDS&gt;0</p> <p>If we now apply a positive drain voltage, current will flow How can we calculate this current as a function of VGS, VDS?</p> <p>B. Murmann</p> <p>EE 214 Lecture 1</p> <p>12</p> <p>16</p> <p>Lecture 2 Common Source Amplifier Small-Signal ModelBoris Murmann Stanford University murmann@stanford.eduCopyright 2007 by Boris Murmann</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>1</p> <p>Overview Reading 3.0 (Amplifier basics), 3.1 (Model selection) 3.3.2 (Common source amplifer) 1.6.0 - 1.6.5 (Small signal MOS model)</p> <p>Introduction Today we'll complete our derivation of the basic longchannel MOSFET I-V characteristics. As a next step, we'll use this simple model to construct our first amplifier a common source stage. Looking at its transfer function, we'll find that treating signals as "small" with respect to the bias conditions allows us to linearize the circuit. Next, we generalize this approach and develop a more universal "plug-and-play" small-signal model for MOS devices that are biased in the active region.EE 214 Lecture 2 2</p> <p>B. Murmann</p> <p>17</p> <p>Basic MOS OperationID=?</p> <p>&gt;0</p> <p>VDS&gt;0</p> <p>How can we calculate ID as a function of VGS, VDS?</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>3</p> <p>Assumptions&gt;0 VDS&gt;0</p> <p>1) Current is controlled by the mobile charge in the channel. This is a very good approximation. 2) "Gradual Channel Assumption" - The vertical field sets channel charge, so we can approximate the available mobile charge through the voltage difference between the gate and the channel 3) The last and worst assumption (we will fix it later) is that the carrier velocity is proportional to lateral field ( = E). This is equivalent to Ohm's law: velocity (current) is proportional to E-field (voltage)B. Murmann EE 214 Lecture 2 4</p> <p>18</p> <p>First Order IV Characteristics (1)</p> <p>What we know:</p> <p>Qn ( y ) = Cox [VGS V ( y ) Vt ]</p> <p>I D = Qn v Wv = E</p> <p> I D = Cox [VGS V ( y ) Vt ] E WB. Murmann EE 214 Lecture 2 5</p> <p>First Order IV Characteristics (2)I D = Cox [VGS V ( y ) Vt ] E W</p> <p>E=</p> <p>dV ( y ) dy</p> <p>I D dy = WCox [VGS V ( y ) Vt ] dVI D dy = WCox [VGS V ( y ) Vt ] dV0 0 L VDS</p> <p>I D = Cox </p> <p>W L</p> <p> V (VGS Vt ) DS VDS 2 </p> <p>For VDS/2 VGS-Vt? VGD = VGS-VDS becomes less than Vt, i.e. no more channel or "pinch off"</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>7</p> <p>Pinch-Off VGS + + VDS </p> <p>N</p> <p>Qn(y), V(y) y y=0</p> <p>N</p> <p>Voltage at the end of channel Is fixed at VGS-Vty=L</p> <p>Effective voltage across channel is VGS - Vt After channel charge goes to 0, there is a high lateral field that sweeps the carriers to the drain, and drops the extra voltage (this is a depletion region of the drain junction) To first order, current becomes independent of VDSEE 214 Lecture 2 8</p> <p>B. Murmann</p> <p>20</p> <p>Modified Plot and EquationsTriode Region Active Region</p> <p>ID</p> <p>VGS-Vt VDS</p> <p>Triode Region:</p> <p>I D = Cox</p> <p>W L</p> <p> V (VGS Vt ) DS VDS 2 </p> <p>Active Region:</p> <p>I D = Cox</p> <p>W L</p> <p>(VGS Vt ) 1 W 2 (VGS Vt ) (VGS Vt ) = 2 Cox L (VGS Vt ) 2 </p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>9</p> <p>First-Order MOS Model Summary</p> <p>VDSW 1 I D Cox (VGS Vt )2 2 L</p> <p>"VCCS"</p> <p>VGS-Vt</p> <p>ld ho es r .) r.. Th bate Su el or (m</p> <p>ACTIVE TRIODEI D Cox W L VDS (VGS Vt ) 2 VDS </p> <p>VGS</p> <p>Vt</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>10</p> <p>21</p> <p>Model Accuracy The above equations constitute the most basic MOS IV model "Long channel model", "quadratic model", "low field model" Unfortunately this model doesn't describe modern CMOS devices accurately Pushing towards extremely small geometries has resulted in very high electric fields Some of the assumptions on slide 4 become invalid Other second order dependencies arise</p> <p>Nevertheless, we will use this simple model in the first few lectures to develop some basic circuit intuition Will fix and refine as we go "Just-in-time" modeling</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>11</p> <p>Let's Build Our First Amplifier One way to amplify Convert input voltage to current using voltage controlled current source (VCCS) Convert back to voltage using a resistor (R) "Voltage gain" = Vout/Vin Product of the V-I and I-V conversion factors</p> <p>B. Murmann</p> <p>EE 214 Lecture 2</p> <p>12</p> <p>22</p> <p>Common Source Amplifier MOS device acts as VCCS</p> <p>W 1 I D = Cox (Vi Vt )2 2 L</p>...