Int J Parallel Prog (2012) 40:1–3DOI 10.1007/s10766-011-0188-z

Guest Editorial: Parallel Systems and Compilers

Valentina Salapura · Michael Gschwind ·Jens Knoop

Received: 24 August 2011 / Accepted: 24 August 2011 / Published online: 5 October 2011© Springer Science+Business Media, LLC 2011

The quest for using parallelism to enhance the performance of computing and com-puting devices is one of the most challenging but also rewarding fields of research incomputer science. With the advent and fast advancing adoption and dissemination ofmulticore technologies, research on parallelism in hardware and software has becomemainstream. The conference series on Parallel Architectures and Compilation Tech-niques (PACT) has been the premier forum and meeting point for researchers andpractitioners from academia and industry for presenting and discussing leading edgeparallel systems research at the intersection of computer architecture and compilationtechnology since its first edition in 1993. In 2010 the 19th edition of the PACT con-ference was held in Vienna, Austria from September 11 to September 15. Reflectingthe growing importance of exploiting parallelism, the conference received an all-timehigh of 266 submissions. Out of these 266 submissions, 46 papers were selected bythe international program committee after a rigorous and strict two-round reviewingprocess for presentation at the conference. Of these, we invited the authors of the verybest and most highly rated papers to submit a revised version of their paper to this spe-cial issue of the International Journal of Parallel Programming devoted to the PACT2010 conference. After a careful two-round reviewing process five papers, including 3which received a “PACT 2010 Best Paper Award,” were selected for inclusion in this

V. Salapura (B)IBM TJ Watson Research Center, Yorktown Heights, NY, USAe-mail: salapura@us.ibm.com

M. GschwindIBM Corp., Poughkeepsie, NY, USAe-mail: mkg@us.ibm.com

J. KnoopVienna University of Technology, Vienna, Austriae-mail: knoop@complang.tuwien.ac.at

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special issue. These papers as well as the contributed papers that were presented atthe conference illustrate the breadth and richness of research at the link of computerarchitecture and compilation techniques for parallel computing, and are impressiveshowcases of cutting edge research in these strands of research that illustrate both thedirection of impact and the state of research in their respective fields.

In “Data Layout Transformation Exploiting Memory-Level Parallelism in Struc-tured Grid Many-Core Applications,” I-Jui Sung, John A. Stratton, and Wen-Mei W.Hwu of the University of Illinois at Urbana-Champaign show that automatic datalayout transformations are an effective compiler performance optimization for mem-ory-bound structured grid applications. Representative of many important structuredgrid applications are fluid dynamics and heat distribution, which both solve partialdifferential equations on a discretized representation of space. The authors use infor-mation available through variable-length array syntax to enable automatic data layouttransformations for structured grid codes with dynamically allocated arrays. Perfor-mance improvements of up to 11.4× are reported over language-defined layouts.

In “Profiling and Optimizing Transactional Memory Applications,” Ferad Zyulkya-rov and Srdjan Stipic of BSC-Microsoft Research Centre and Universitat Politècnicade Catalunya, Tim Harris of Microsoft Research, Osman S. Unsal of BSC-MicrosoftResearch Centre, Adrián Cristal of BSC-Microsoft Research and IIIA - Artificial Intel-ligence Research Institute CSIC - Spanish National Research Council, Ibrahim Hurof BSC-Microsoft Research, and Mateo Valero of BSC-Microsoft Research Centreand Universitat Politècnica de Catalunya present a series of profiling techniques forapplications using transactional memory (TM) that provide comprehensive in-depthinformation on the performance behavior and bottlenecks of TM applications usingnew visualization techniques. They demonstrate the effectiveness of the profiling tech-niques on a set of benchmarks of the STAMP TM benchmark suite and the WormBenchworkload for optimizing the performance of TM applications.

In “Managing Data Placement in Memory Systems with Multiple Memory Control-lers,” Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, and AlDavis of the University of Utah propose new dynamic mechanisms that support dataplacement on modern processors with multiple on-chip memory controllers that stillmaintain a large, flat memory address space. The new mechanisms take into accountqueuing delays, on-chip latencies, and row-buffer hit-rates. The approach is validatedfor the adaptive first-touch page placement and a dynamic page-migration placementpolicy.

In “Efficient Sequential Consistency using Conditional Fences,” Changhui Lin ofthe University of California, Riverside, Vijay Nagarajan of the University of Edin-burgh, and Rajiv Gupta of the University of California, Riverside, analyze the use offences to ensure sequential consistency on architectures that support a weaker mem-ory model. They find that only about 8% of executed instances of memory fencesin parallel programs are actually needed to ensure sequential consistency. Based onthese findings they propose a new conditional fence mechanisms that utilizes compilerinformation to dynamically decide if a stall at each fence is needed. They report thatthe slowdown of introducing fence instructions to ensure sequential consistency canbe brought down to 12% from 43%, based on experiments with a set of SPLASH-2benchmarks.

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In “DAFT: Decoupled Acyclic Fault Tolerance,” Yun Zhang of Princeton Uni-versity, Jae W. Lee of Parakinetics Inc., Princeton, and Nick P. Johnson and David I.August of Princeton University deal with software transient fault detection and presenta new framework for commodity multicore systems that is fast, safe, and memory-efficient. Results collected on the SPEC CPU2000 and SPEC CPU2006 benchmarksshow that the new approach reduces the performance overhead of software redundantmultithreading by 2.17× with no degradation of fault coverage.

In closing we would like to thank all the authors of the above papers for their contri-bution to make this special issue of the International Journal of Parallel Programmingdevoted to the PACT 2010 conference possible. We would like to thank all the review-ers, without whose engagement and hard work this issue would not have been possible,for their detailed and meaningful reviews that helped the authors to further improvethe presentation of their papers. In addition to the authors and reviewers, we wouldlike to thank the editors of IJPP, Utpal Banerjee, Nick Carriero, and Alex Nicolau.Last but not least, we would like to thank the staff at Springer of the InternationalJournal of Parallel Programming, in particular, Melissa Fearon and S. Muthulakshmifor the smooth cooperation during the last year.

We hope that you will enjoy reading the articles of this special issue as much as weenjoyed preparing this issue, and that you will find them useful and inspiring for yourown work.

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