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GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL. PROMETEO workshop. November 17-18 2011, Valencia. Outlines. NEDA . Global Trigger and Synchronization Firmware Optical Gigabit Link (LINCO) Expected Activities. TRACE. FEE options Reduced output - PowerPoint PPT Presentation
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GTS, Optical Link andTRACE Front End Electronics
Andrea TriossiINFN - LNL
PROMETEO workshop November 17-18 2011, Valencia
Outlines
• FEE options• Reduced output• Sparse readout• RO and Trigger on FPGA
• Expected Activities
TRACE
• Global Trigger and Synchronization Firmware
• Optical Gigabit Link (LINCO)
• Expected Activities
NEDA
GTS: Functionalities
Trigger Request
Local Tag
Local Tag Generator
MGT
TX
RX
TriggerMatch MEM
Valid / Reject
Val/Rej Tag
Uplink
• Common clock • Global clock counter• Global event counter• Trigger requests• Error reports
• Trigger controls:• Throttling of the L1 validation signal • Fast commands (fast reset, initialization, etc.)• Fast monitoring feedback from the crystals• Calibration and test trigger sequence commands• Monitor of dead time
GTS: Current Limits
• Serves just one trigger requestInterface for 16
• Handles just one ID request16 ID per GTS core
• Single communication interfaceSplit into two?one towards V6 and one inside V5
GTS Interfaces
• Trigger Requests
• GTS Services• PPC running
• Hardware implemented ?
LinuxVxWorks
22 lines (request, validation/rejection)+ 16 due to requester ID (concurrent trigger requests)
= 38 lines between V5 and V6
Adapter to translate PCI Express signals to/from the optical physical layer suitable for legacy bus standards (PCI, cPCI, VME…)
What is LINCO?
localbus
remotebus
Already adopted by several experiments:
• AGATA (moving from V1 to V2)
• CMS @ CERN (since 2005 in harsh environmental conditions)
• ICARUS
• WARP@ LNGS
LINCO Flavors
1x4 PCIEx / 2x2 PCIEx / 4x1 PCIExMotherboard/Oscillator REF CLK
x4 PCIEx bus
Clock issues• Spread Spectrum Clock• Clock out of spec
PCIEx Switch GEN220 Gb/s aggregate
x1 PCIEx PCI1 REF CLK bus
x1 PCIEx x1 PCIEx1 REF CLK bus
LINCO V2
RAM
PCI-Ex DMA Transfer
DMA engine continuously write on PC RAM holding the processor bus.If we want to run concurrently online trigger algorithms or even analysis
programs that access the main memory, the DMA transfer will be stopped
CPU Root Complex
PCI-ExEndpoint
PCI-ExEndpoint
PCI-ExEndpoint
PCI-ExEndpoint
PCI-ExEndpoint
The higher the throughput the bigger the buffering
Expected Activities
• x2 (x4) PCI Express core deployment
• Communication test LINCO-Numexo carrier
• Check compatibility issues between LINCO and PC farm
LINCO
• New Firmware
• Test bench on a small tree (GTS mezzanine?)
• Test on a Numexo carrier
Global Trigger and Synchronization
TRACE FEE Requirements
• CMOS 180 nm
• Low consumption (1-10 mW)
• Fast switching
• High integration
• Spherical chamber Ø 26cm
• 10K channels
• PA inside the chamber
Integrated PAAnalog Memory for multiplexing
TRACE ASIC
Technology
TRACE FEE Requirements
• Rising time: 20-200 ns• Bandwidth: 0.35/20 ns = 17.5 MHz• Sampling rate: 200 MHz• Rising time 200 ns, 200 MHz sampling rate: 40 samples (2B each, 12bit ENOB)
• 128 ch per ASIC• Rate/ch 100 Hz• Throughput: 1MB/s per ASIC (~80)
• Digitizer out of the chamber• PA 2 mW/ch 200 mW/ASIC 20 W/array
(~the same from the analog memory)
Consumption
Throughput
PSA Feasibility
• Transient signal: 1/10 net charge (from simulation)
• Worst case: 5 MeV Alpha 50 mV
• Gain: 10 mV/MeV (which Ion set the gain? Li?)
• Bandwidth: 100MHz
• ENC 10e rms
• Dynamics: 150 MeV on 1.5 V
Pre Amplifier
Q Amp Shaper 128x128Memory cells
Inputchannels
. . . . .
. . . . .
. . . . .
M U X
200 MHz
ReducedOutput
. . . . .
TriggerComp
A
B
Q Amp Shaper
Inputchannels
. . . . .
. . . . .
. . . . .
M U X
200 MHz
SparseReadout
. . . . .
Encoder
Comp
LookupTable
Controller
128x128Memory cells
V/I Amp Memory cells128x128
. . . . .
. . . . .
A D C
200 MHz TriggerC
Inputchannels
F P G A
High speedSerial link
FPGA as ADCFPGA
D A C
V/I AMP
V/I AMP
V/I AMP
V/I AMP
TDC
TDC
TDC
TDC
T1
V1
T2
V2
T3
V3
T4
V4
• From PA directly to FPGA differential inputs
• External DAC used to produce a VREF linear ramp
• TDCs measure time differences further converted to voltage
Highest integration?
Dead Time
• MUX switching time: typ. ~ 50 ns
• Sampling Rate 200 MS/s per ch
• Samples: 40 signal + 20 baseline
• Memory depth: 128 samples
• Dead time per ch: 50 ns + 128x5 ns = 640 ns
• Dead time per ASIC: 128x350 ns ≈ 80 µs
• 80 µs ~12 KHz (Elastic Scattering)
• Simultaneous Read/Write ?
• ROI Read out (60 samples) ?
Solution A
Prototype channel
• Analog memory (DRS4): 5 GS/s, 1024 cells, 9 ch (4 in the EVB)• ADC (AD9245): 14 bit, 80 MS/s• FPGA Xilinx Spartan3• Microcontroller (CY2C68013A ) with USB connection
S. Ritt (PSI)
Conclusions
• PA ASIC development
• Analog memory prototype channel
• TDC feasibility study
• Global Trigger and DAQ: Compatibility Issues
TRACE
• Development of a New GTS Firmware
• Test on NUMEXO carrier
• Compatibility among PC-LINCO-NUMEXO
NEDA