Growth, processing and characterization of group IV materials for thermoelectric

applications

Mohammad Noroozi

Doctoral Thesis in Physics School of information and Communication Technology

KTH Royal institute of Technology

Stockholm, Sweden 2016

ii

KTH School of Information and

Communication Technology

SE-164 40 Kista

SWEDEN

TRITA-ICT 2016:20

ISBN 978-91-7729-076-6

Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges

till offentlig granskning för avläggande av doktorsexamen i fysik fredag den 30 September 2016 klockan 10:00 i Sal B, Electrum, Kungl Tekniska högskolan, Kistagången 16, Kista.

© Mohammad Noroozi, September 2016

Tryck: Universitetsservice US A

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Abstract

Discover of new energy sources and solutions are one of the important global issues nowadays, which has a big impact on economy as well as environment. One of the methods to help to mitigate this issue is to recover wasted heat, which is produced in large quantities by the industry, through vehicle exhausts and in many other situations where we consume energy. One way to do this would be using thermoelectric (TE) materials, which enable direct interconversion between heat and electrical energy. This thesis investigates how the novel material combinations and nanotechnology could be used for fabricating more efficient TE materials and devices.

The work presents synthesis, processing, and electrical characterization of group IV materials for TE applications. The starting point is epitaxial growth of alloys of group IV elements, silicon (Si), germanium (Ge) and tin (Sn), with a focus on SiGe and GeSn(Si) alloys. The material development is performed using chemical vapor deposition (CVD) technique. Strained and strain-relaxed Ge1-x Snx (0.01≤x≤0.15) has been successfully grown on Ge buffer and Si substrate, respectively. It is demonstrated that a precise control of temperature, growth rate, Sn flow and buffer layer quality is necessary to overcome Sn segregation and achieve a high quality GeSn layer. The incorporation of Si and n- and p-type dopant atoms is also investigated and it was found that the strain can be compensated in the presence of Si and dopant atoms.

Si1-xGex layers are grown on Si-on-insulator wafers and condensed by oxidation at 1050 ᵒC to manufacture SiGe-on-insulator (SGOI) wafers. SGOI wafers are n- or p-doped by diffusion of phosphorous (P), or boron (B) atoms into the SGOI wafers. Nanowires (NWs) are processed, either by sidewall transfer lithography (STL), or by using conventional lithography, and subsequently manufactured into nanoscale dimensions by focused ion beam (FIB) technique. The NWs are formed in an array, where one side is heated by a resistive heater made of Ti/Pt. The high contact resistance for NWs is tackled by the formation of a Ni silicide layer prior to the metallization. A very low contact resistivity for Ni-SiGe and Ni-GeSn phase is achieved at 450 ᵒC, using rapid thermal processing (RTP). The power factor of NWs is measured and the results are compared for NWs manufactured by different methods. It is found that the electrical properties of NWs fabricated with FIB technique can be influenced due to Ga doping during ion milling.

Finally, the carrier transport in SiGe NWs formed on SGOI samples is tailored by applying a back-gate voltage on the Si substrate. In this way, the power factor is improved by a factor of 4. This improvement is related to the presence of defects and/or small fluctuation of nanowire shape and Ge content along the NWs, generated during processing and condensation of SiGe layers. The SiGe results open a new window for operation of SiGe NWs-based TE devices in the new temperature range of 250 to 450 K.

Keywords: Thermoelectric, SiGe, GeSn(Si), Chemical vapor deposition, Nanowires

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Sammanfattning

Att spara energi är ett av de viktigaste målen för vår planet, eftersom energiförbrukningen har en direkt inverkan på den globala ekonomin samt miljön. En stor del av den energi vi förbrukar idag går dock till spillo som värme. En hittills ganska outnyttjad metod för återvinning av spillvärme kan vara användningen av termoelektriska (TE) material som möjliggör en direkt omvandling av värme till elektrisk energi. Genom att kombinera nya materialvarianter och nanoteknologi har mycket höga verkningsgrader hos termoelektriska komponenter uppnåtts. Denna avhandling presenterar syntes, bearbetning, och elektrisk karakterisering av legeringar av element från grupp IV i det periodiska systemet, kisel (Si), germanium (Ge) och tenn (Sn), för termoelektriska tillämpningar. Arbetet består i att utveckla framställningsmetoder för tunna skikt av legeringarna, i huvudsak SiGe- och GeSn(Si) genom epitaxiell tillväxt med s k ”chemical vapour deposition” (CVD).

Töjda och relaxerade skikt av Ge1-x Snx (0.01≤x≤0.15) har odlats på lager av Ge-buffert, respektive Si-substrat. Det visade sig att en exakt kontroll av temperatur, gasflöden och kvaliteten på Ge-buffertlager är nödvändigt för att övervinna segregation av Sn och uppnå tillräckligt hög kvalitet på GeSn skikten. Inkorporeringen av kisel och dopatomer i GeSn undersöktes också och man fann att kristalltöjningen kan kompenseras i närvaro av kisel eller dopatomer. Vidare har Si1-xGex-skikt odlats på skikt av kiseloxid, genom att använda s k ”Si-on-insulator” -skivor. Genom en efterföljande oxidation vid 1050 ᵒC har det varit möjligt att syntetisera ”SiGe-on-insulator” (SGOI) -skivor. Dessutom kunde dessa SGOI-skivor göras n- eller p-dopade genom att inkorporera fosfor (P) eller bor (B) atomer.

Ur dessa olika skikt framställdes sedan nanotrådar, antingen genom s k ”sidewall transfer lithography” (STL), eller genom att använda konventionell litografi, i kombination med bearbetning med hjälp av en fokuserad jonstråle (FIB). Nanotrådar tillverkades i matriser där en sida kunde upphettades med en resistiv värmare tillverkad av Ti/Pt. För elektrisk kontaktering av nanotrådarna utarbetades en teknik med nickel (Ni) –silicidering genom en snabb termisk behandling vid 450 ᵒC före metalliseringen. Detta resulterade i mycket låga kontaktresistanser, vilket förbättrar verkningsgraden hos de termoelektriska komponenterna. Verkningsgrad och effektfaktorn hos nanotrådar mättes och resultaten jämfördes för nanotrådar som tillverkats med olika metoder. Det visade sig bl a att de elektriska egenskaperna hos nanotrådar tillverkade med FIB-teknik kan påverkas av Ga-dopning under FIB behandling. Slutligen gjordes strukturer där laddnigstransporten i SiGe-nanotrådar av SGOI material kan optimeras genom att tillverka en baksideskontakt på Si-substratet. Genom att spänningssätta denna kontakt kunde en fyrfaldig förbättring av effektfaktorn uppnås. Denna förbättring var också relaterad till defekter och/eller små fluktuationer av nanotrådarnas form och Ge-halt, vilket genererats under fabriceringen. Resultaten öppnar för nya termoelektriska tillämpningar av SiGe nanotrådar i temperaturområdet 250 till 450 K.

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Table of Contents Abstract .......................................................................................................................................... iii

Sammanfattning ............................................................................................................................. iv

Acknowledgments........................................................................................................................ viii

Publications included in the thesis .................................................................................................. x

Author’s Contributions .................................................................................................................. xi

Other relevant publications ........................................................................................................... xii

List of conference contributions .................................................................................................. xiii

List of Acronyms and Symbols ................................................................................................... xiv

Chapter 1 Thermoelectric phenomena ............................................................................................ 1

1.1 Introduction ...................................................................................................................... 1

1.2 Thermoelectric efficiency ................................................................................................ 1

1.2.1 Motivation for Thermoelectrics ................................................................................ 1

1.2.2 Thermoelectric device ............................................................................................... 2

1.3 Thermoelectric parameters ............................................................................................... 4

1.3.1 Seebeck coefficient and electrical conductivity ........................................................ 4

1.3.2 Thermal Conductivity ............................................................................................... 4

1.4 State of the art thermoelectric materials ........................................................................... 5

1.5 Advances in ZT enhancement .......................................................................................... 6

1.5.1 Strategies for lowering thermal conductivity ............................................................ 6

1.5.2 Methods to increase the power factor ....................................................................... 7

1.6 Si-based materials for TE applications........................................................................... 10

1.6.1 SiGe......................................................................................................................... 10

1.6.2 GeSn (Si) ................................................................................................................. 11

1.7 Objectives ....................................................................................................................... 11

Chapter 2 Fabrication of low dimensional materials .................................................................... 12

2.1 Epitaxy ........................................................................................................................... 12

2.1.1 CVD process ........................................................................................................... 12

2.2 Condensation process ..................................................................................................... 13

2.3 Nanowire fabrication ...................................................................................................... 13

2.3.1 Optical Lithography ................................................................................................ 13

2.3.2 Focused ion beam (FIB) technique ......................................................................... 14

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2.3.3 Side wall transfer lithography (STL) ...................................................................... 14

2.4 Contact Resistance ......................................................................................................... 15

Chapter 3 Material development and processing .......................................................................... 16

3.1 Epitaxial growth ............................................................................................................. 16

3.1.1 GeSn (Si) epitaxy .................................................................................................... 16

3.1.2 SiGe epitaxy ............................................................................................................ 17

3.2 Condensed SGOI formation ........................................................................................... 17

3.3 Fabrication of NWs using FIB technique ....................................................................... 18

3.4 Fabrication of NWs using STL technique ...................................................................... 18

3.5 Ni-SiGe and Ni-GeSn formation .................................................................................... 19

3.6 Microchip Fabrication .................................................................................................... 20

3.7 Measurement techniques ................................................................................................ 21

3.7.1 The electrical conductivity ...................................................................................... 21

3.7.2 The Seebeck Coefficient ......................................................................................... 21

3.7.3 Back-gate biasing .................................................................................................... 23

3.8 Material characterization ................................................................................................ 23

3.8.1 Electron microscopy ............................................................................................... 23

3.8.2 X-ray diffraction (XRD) ......................................................................................... 24

3.8.3 Rutherford Backscattering (RBS) ........................................................................... 25

3.8.4 Atomic force microscopy (AFM) ........................................................................... 25

Chapter 4 Results and Discussions ............................................................................................... 26

4.1 Characterization of GeSn epitaxial layers (paper I&II) ................................................. 26

4.1.1 Compressive strained GeSn samples ...................................................................... 26

4.1.2 Optimized compressive strained GeSn samples ..................................................... 26

4.1.3 Strain-relaxed GeSn samples .................................................................................. 27

4.1.4 Incorporation of Si in GeSn .................................................................................... 29

4.1.5 P- and n-type doping of GeSn ................................................................................. 30

4.2 Ni-GeSn contact formation (paper III) ........................................................................... 31

4.3 Ni-SiGe contacts formation ............................................................................................ 32

4.4 Characterization of SGOI layer (paper IV and V) ......................................................... 34

4.5 Characterization of NWs formed with FIB technique (paper IV) .................................. 36

4.6 Characterization of NWs prepared with STL technique (paper V) ................................ 39

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4.7 Backgate biasing of SiGe NWs (paper VI) .................................................................... 41

Chapter 5 ....................................................................................................................................... 46

5.1 Conclusions .................................................................................................................... 46

5.2 Future work .................................................................................................................... 47

References ..................................................................................................................................... 48

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Acknowledgments

Pursuing a Ph.D project is both tedious and enjoyable experience and when you reach to the end, then you realize that it were many people who kindly helped you to get there. Though it will not be enough to express my gratitude in words to all those people who help me, but I write this page to thank all of them.

First of all, I would like to give my sincere thanks to my supervisors, Prof. Muhmmet Toprak and Henry Radamson who accepted me as Ph.D student. Prof. Toprak gave me many advices and patiently supervised me, and always guided me to the right direction. I have learned a lot from him and without his help; I could not have finished my dissertation successfully. Prof. Radamson was much more than a supervisor, but also a close friend. His encouragement and help made me feel confident to fulfill my desire and to overcome difficulties I encountered during my Ph.D work. In fact, it is not sufficient to express my gratitude with only few words.

I would like to thank Prof. Joydeep Dutta, Dr. Abdusalam Uheida and Docent Wubeshet Sahle for their support and fruitful discussions.

My sincere gratitude extends to my fellow colleagues in Functional Materials (FNM) Division, Dr. Nader Nikkam, Dr. Fei Ye, Dr. Mohsin Saleemi, Dr. Yichen Zhao, Ms. Adrine M. Khachatourian, Ms. Heba Asem, Mr. Bejan Hamawandi, Mr. Arash Hojabri, Ms. Katayoun Zahmatkesh and others.

Special thanks are also given to my perfect office mates and colleagues, Dr. Mohsen Y.Tafti and Mr. Venkatesh Doddapaneni. Thanks for wonderful time we had, nice scientific discussion and having enjoyable time and being generous and kind friends.

I would like to express my appreciation to our collaborative partners, Prof. Saulius Marcinkevičius, Dr. Mounir Mensi, Prof. Lars Hultman, Dr. Jun Lu, Ion technology center (Uppsala), Prof. Zoran Ikonic, Prof. Clivia M. Sotomayor Torres, Prof. Anand Srinivasan, Dr. Juliana Jaramillo Fernandez, Mr. Ahmad Abedin, Mr. Ganesh Jayakumar and Mr. Stephan Schröder.

I acknowledge all who have provided answers to my questions and have help me in the EKT department. To mention some : Prof. Mikael Östling, Assoc. Prof. Gunnar Malm, Assoc. Prof. Per-Erik Hellström, Prof. Mattias Hammar, Dr. Yong Bin Wang, Mr. Christian Ridder and Dr. Gabriel Roupillard. I would like to specially thank Prof. Anders Hallén for his great help on revision of my thesis.

I would like to thank all Electrum lab personal who have assisted me many times and of course, Mr. Reza Nikpars, Mr. Sven Valerio, Mr. Magnus Lindberg, Mr. Per Wehlin, Mr. Arman Sikiric.

I owe a special thanks to all my friends in ICT School, Dr. Sam Vaziri, Arash Salemi, Ahmad Abedin, Hossein Elahipanah, Ali (Pooria) Asadollahi, Babak Taghavi, Roodabeh Afrasiabi, Dr. Masoud Daneshtalab, Dr. Azin Ebrahimi, Milad Ghadami Yazdi, Raheleh Hedayati, Dr. Maziar

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A. M. Naiini, Dr. Sohrab Redjai Sani for providing a nice working atmosphere. You all made my working life much more pleasant.

I would like to acknowledge the funding from Swedish foundation for strategic research (SSF) to the project Scalable Thermoelectric Materials (Project No: EM11-0002). Also I would like to thank ÅF foundation and Knut and Alice Wallenberg’s foundation for their support for travel grants to international conferences during my Ph.D.

To the love of my life, my wife, Samaneh, thank you being unconditionally always next to me, you earned this Ph.D. as much as me! Parham and Pouyan, the most precious children in the world, thank you for always reminding me that there is a life beyond PhD.

Lastly, I am grateful to my parents who had given me endless affection and blessing.

Thank you

Mohammad Noroozi

Stockholm, September 2016

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Publications included in the thesis

1. M. Noroozi, A. Abedin, M. Moeen, M. Östling, H.H. Radamson, “CVD Growth of GeSnSiC Alloys Using Disilane, Digermane, Tin Tetrachloride and Methylsilane” ECS transactions, vol. 64, no. 6, pp.703-710, 2014, doi: 10.1149/06406.0703ecst

2. A. Abedin, M. Noroozi, D. Primetzhofer, M. Östling and H. H. Radamson, “GeSnSi CVD Epitaxy using Silane, Germane, Digermane, and Tin tetrachloride” manuscript

3. M. Noroozi, M. Moeen, A. Abedin, M.S. Toprak, H.H. Radamson, “Effect of strain on Ni-(GeSn) contact formation to GeSn nanowires”, MRS Proceedings, vol. 1707, mrss14-1707-uu06-03(6pages), 2014, doi: http://dx.doi.org/10.1557/opl.2014.559

4. B. Hamawandi, M. Noroozi, G. Jayakumar, A. Ergül, K. Zahmatkesh, M. S. Toprak, H. H. Radamson,“Electrical characterization of sub-100 nm SiGe nanowires”, Journal of Semiconductors, vol. 37, no. 10, 2016, doi: 10.1088/1674-4926/37/10

5. M. Noroozi, B. Hamawandi, G. Jayakumar, K. Zahmatkesh, M. S. Toprak, H. H. Radamson, “Comparison of power factor in n-type and p-type SiGe nanowires for thermoelectric application”, Journal of Nanoscience and Nanotechnology, vol. 16, 2016, doi:10.1166/jnn.2016.13728

6. M. Noroozi, G. Jayakumar, B. Hamawandi, , K. Zahmatkesh, M. S. Toprak, H. H. Radamson, et al. “Significant improvement of thermoelectric efficiency in SiGe nanowires”, submitted to Nature communication.

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Author’s Contributions

Paper 1 : Planning of experiments, performing the whole epitaxy work, performing part of characterization, interpretation of the results and writing the manuscript.

Paper 2 : Assisstance on planning and design of experiments, performing part of epitaxial process, performing part of characterization, providing scientific discussions, contribution to interpret the results, and contributing on writing the manuscript.

Paper 3: Planning and design of experiments, performing the whole epitaxy work, performing all fabrication processes, performing part of material characterization, interpretation of results and writing manuscript.

Paper 4 : Contribution to design and planning of experiments, performing the whole epitaxy work, performing major part of fabrication process, assistance in focused ion beam milling process, assistance in electrical characterization, providing scientific discussions and help on interpretation of data, contributing on writing the manuscript.

Paper 5: Planning and design of experiments, performing the whole epitaxy work, performing major part of fabrication process, performing major part of material and device characterization, interpretation of data and writing the manuscript.

Paper 6: Planning and design of experimentss, performing the whole epitaxy work, performing major part of fabrication process, performing part of material and device characterization, providing scientific discussion and interpretations of data and writing the manuscript.

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Other relevant publications

1. H.H. Radamson, M. Noroozi, A. Jamshidi, PE. Thompson, M. Östling, “Strain engineering in GeSnSi materials’’ ECS Transactions, vol 50, no 9, pp. 527-531, 2013

2. A. Jamshidi, M. Noroozi, M. Moeen, A. Hallen, B. Hamawandi, J. Lu, L. Hultman, M. Ostling, and H. Radamson, “Growth of GeSnSiC layers for photonic applications,” Surface Coatings Technology, vol. 230, pp. 106–110, 2013

3. M. Noroozi, A. Ergül, A. Abedin, M. Toprak, H.H. Radamson, “Fabrications of size-controlled SiGe nanowires using I-line lithography and focused ion beam technique’’, ECS Transactions vol. 64, no 6, pp. 167-174, 2014

4. M. Noroozi, B. Hamawandi, M. S. Toprak, and H. H. Radamson, “Fabrication and thermoelectric characterization of GeSn nanowires,” ULIS 2014, 15th International. Conference Ultimate Integration Silicon, pp. 125–128, 2014

5. C. Hu, P. Xu, C. Fu, Z. Zhu, X. Gao, A. Jamshidi, M. Noroozi, H. Radamson, D. Wu, S.L. Zhang, “Characterization of Ni (Si, Ge) films on epitaxial SiGe (100) formed by microwave annealing’’, Applied Physics Letters, vol. 101, p.092101, 2012

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List of conference contributions

1. M. Noroozi, G. Jayakumar, B. Hamawandi, A. Ergül, K. Saomatkesh, M.S. Toprak, H. H. Radamson, “P- and N-type doped SiGe nanowires for thermoelectric application”, Spring E-MRS, 11-15 May, 2015-Lille, France

2. B. Hamawandi, M. Noroozi, G. Jayakumar, A. Ergül, K. Saomatkesh, M. S. Toprak, H. H. Radamson, “Comparison of side wall lithography and focused ion beam techniques for fabrication of sub-100 nm SiGe nanowires”, Spring E-MRS, 11-15 May, 2015-Lille, France

3. B. Hamawandi, M. Noroozi, M. S. Toprak, T. Zabel, D. Primetzhofer, H. H. Radamson, “Characterization of SGOI fabricated by condensation and wafer bonding techniques”, Spring E-MRS, 11-15 May, 2015-Lille, France

4. A. Abedin, M. Noroozi, D. Primetzhofer, M. Östling and H. H. Radamson, “GeSnSi(C) CVD epitaxy using Silane, Germane, Digermane, and Tin tetrachloride”, Spring E-MRS, 11-15 May, 2015-Lille, France

5. M. Noroozi, B. Hamawandi, M. S. Toprak, H. H. Radamson, “Fabrication and thermoelectric characterization of GeSn nanowires”, 15th International Conference on Ultimate Integration on Silicon (ULIS) , 7-9 April, 2014- Stockholm, Sweden

6. M. Noroozi, M. Moeen, A. Abedin, M. S. Toprak, H. H. Radamson, “Effect of strain on Ni-(GeSn) contact formation to GeSn nanowires”, Spring MRS, 21-25 April, 2014-San Francisco, USA

7. M. Noroozi, M. Moeen, B. Hamavandi, M. S. Toprak, H. H. Radamson, “Electrical and material characterization of Ni (GeSn)nanowires for thermoelectric application”, 11th European Conference on Thermoelectrics, 18-20 November, 2013-Noordwijk, Netherlands

8. M. Noroozi, B. Hamawandi, A. Jamshidi, M. S. Toprak and H. H. Radamson, “Effect of strain on phase formation of Ni Sn-Germanide”, Spring E-MRS, 15-17 May, 2012-Strasbourg, France

9. M. Noroozi, A. Jamshidi, P. E. Thompson, M. Östling and H. H. Radamson, “Strain engineering in GeSnSi materials”, Electrochemical Society (ECS), October 7-12, 2012- Hawaii, USA

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List of Acronyms and Symbols

Si Silicon

SiGe Silicon-Germanium

GeSn Germanium-Tin

SiGeSn Silicon Germanium Tin

Ge Germanium

SOI Silicon on Insulator

SGOI SiGe on Insulator

Ni Nickel

NiGeSn Nickel Tin Germanide

EDX Energy Dispersive X ‐ray

TE / TEs Thermoelectric / Thermoelectrics

TEM Transmission Electron Microscope

SEM Scanning Electron Microscope

HRRLM High Resolution Reciprocal Lattice Map

XRD X-ray Diffraction

ZT Thermoelectric Figure of Merit

S Seebeck Coefficient

ρ Electrical Resistivity

σ Electrical Conductivity

κ Thermal Conductivity

κel Electronic Thermal Conductivity

κlatt Lattice Thermal Conductivity

S2σ Power Factor

I Current

ΔV Voltage Difference

ΔT Temperature Difference

SPM Scanning Probe Microscopy

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Chapter 1 Thermoelectric phenomena

1.1 Introduction

Thomas J. Seebeck did the first observation of thermoelectric (TE) phenomena at the beginning of 19th century. He discovered that when two different metals in contact with each other are kept at two different temperatures there is deflection in a magnetic compass needle[1]. A few years after this discovery, J. Peltier found a reverse effect when an electrical current is applied to the two metals forming a junction; it can cause a gradient in the temperature of the structure. Later on, these experimental findings were unified and a complete thermodynamic argument was presented for TE phenomena[1,2]. Although these observations did not receive a large attention in the beginning, the impact now appears in some applications in our daily life activities when new materials are discovered with high TE performance [3].

According to the specific definition the TE phenomenon can be explained as follows: when a temperature gradient (∆T) is applied to a TE material, an electrostatic potential (∆V) is generated. A characteristic parameter, S = ΔV/ΔT is defined as the Seebeck coefficient, which is the base of the TE effect for power generators. The inverse appearance of temperature gradient due to applied voltage is called Peltier effect. From a physical point of view, these effects can be explained by the fact that charge carriers in metals and semiconductors can carry charge as well as heat. As a temperature gradient is created in the material, the charge carriers at the hot side of the element start to diffuse to the cold side, building up an electrostatic potential or voltage. An equilibrium point is reached between the electrostatic repulsion and chemical potential[4].

Altenkirch introduced the TE performance of a material in terms of the Seebeck coefficient, electrical conductivity, and thermal conductivity[5]. He explained that this effect is very material dependent and a good TE material needs to have a large Seebeck coefficient (large potential difference), a low thermal conductivity (keep the temperature difference at junctions) and a high electrical conductivity or low electrical resistance (to avoid Joule heating)[2]. Altenkirch used the TE concept and characterized the “thermopile” as an imperfect thermodynamic device in comparison to efficiency of Carnot cycle[1]. This was the starting point for decades research and development for efficient TE materials and devices.

1.2 Thermoelectric efficiency

1.2.1 Motivation for Thermoelectrics

The global warming is one of the most serious problems in modern times. The main reason for this phenomenon is related to the release of greenhouse gases from burning fossil fuels. Although there are a series of agreements to reduce the greenhouse gases, technologically there is a long way to find a reliable and more energy efficient solutions to replace fossil fuels with clean energy sources. Today, all the traditional alternative clean energy sources like solar cells, wind generation, and geothermal heating can deliver only a small fraction of the energy consumed [6].

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Among the different solutions for energy problem[7], the TE solution has become very attractive to make contribution over a wide-range of applications , in reducing fossil fuel consumption and global warming[8]. The reason behind this attraction could be a large dissipation of heat from car engines, industrial activities and many other actions in daily process. Therefore, TE devices could bring up a solution on the table as they can convert dissipated heat to electrical energy.

1.2.2 Thermoelectric device

TE devices can be divided into two main categories: Those which operate through the Peltier effect for TE refrigeration modules and those which employ the Seebeck effect for electric power generation[2]. A schematic of both these devices is shown in Figure 1. A simple semiconductor TE device is composed of two legs, one of n-type (containing negative carriers with negative Seebeck coefficient) and one of p-type (positive carriers with positive Seebeck coefficient) materials, which are connected through metallic pads in the ends. The n- and p-type legs can be repeated in arrays arranged electrically in series and thermally in parallel. This structure is necessary since the TE legs need a high current density and low voltage to function properly. Using this array configuration increases the operating voltage while decreasing the overall current density and parasitic effect of multiple series of interconnects [6]. To look more closely, when a temperature gradient is applied, the device utilizes the Seebeck effect and generates a voltage which can drive a current through an external load. This is a direct conversion of heat to electricity through TE and such a device is called TE generator (TEG) (Figure 1a). On the other hand, when an electric current is imposed on a TE device, it creates a temperature difference across the device and heat can be absorbed on the cold side of the device which enables it to be used as a temperature controlling device (Figure 1b)[9].

Figure 1. Schematic of a TE device for a) power generation (Seebeck effect) or b) cooling (Peltier effect)

To discuss and compare the TE properties of materials, a dimensionless figure of merit (FOM) described by the ZT number (where Z is the figure of merit and T is absolute temperature) has been introduced. The ZT consists of three critical parameters: the Seebeck coefficient, S, electrical conductivity, σ, thermal conductivity, κ and temperature, T as follows:

3

𝑍𝑍𝑍𝑍 = 𝑆𝑆2𝜎𝜎𝜅𝜅𝑍𝑍 (1)

The efficiency of a TEG, η, is strongly associated with the FOM of the material (here we use ZT for FOM of material to distinguish from 𝑍𝑍′𝑍𝑍 for device FOM) and the temperature gradient (ΔT=Thot-Tcold). It is given by combining the Carnot efficiency (maximum theoretical efficiency one can get from heat engine operating in temperature difference of 𝛥𝛥𝑍𝑍 ) and 𝑍𝑍′𝑍𝑍 as shown in equation 2[10].

𝜂𝜂 =𝛥𝛥𝑍𝑍𝑍𝑍ℎ𝑜𝑜𝑜𝑜

.√1 + 𝑍𝑍′𝑍𝑍 − 1

√1 + 𝑍𝑍′𝑍𝑍 + 𝑍𝑍𝑐𝑐𝑜𝑜𝑐𝑐𝑐𝑐𝑍𝑍ℎ𝑜𝑜𝑜𝑜

(2)

where ΔT is the temperature difference, and Thot , Tcold are the temperature of hot side and the temperature of cold side, respectively.

To have an efficient TEG, the temperature difference should be large and ZT value should be high. Based on the overall performance, the Z′T value associated with equation 2 is lower than ZT of materials. For example, even the ZT of Bi2Te3 is 1.1, the best 𝑍𝑍′𝑍𝑍 for a TEG made of this material does not exceed 0.7. This is due to parasitic resistances at n and p-type legs which degrade the performance of the device[4].

Figure 2 TE power generation efficiency at different ZT and Carnot limit (Tcold=573K)(reproduced from ref.[6])

With such FOM, the efficiency of TE devices does not exceed 5 to 6% of the Carnot efficiency. This is lower than the efficiency of most other energy resources. Figure 2 compares TE power generation efficiency for different ZT and some other conventional engines. It shows that materials with high FOM are demanded in order to make them attractive for consideration in energy conversion/harvesting [6].

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1.3 Thermoelectric parameters

1.3.1 Seebeck coefficient and electrical conductivity

To achieve an improvement of the FOM of TE materials three physical parameters, Seebeck coefficient, thermal and electrical conductivity, need to be optimized. The problem associated with ZT improvement then becomes evident, as these parameters are strongly interconnected to each other. For example to have a high ZT, a high power factor (S2σ) which means large Seebeck coefficient and electrical conductivity and low thermal conductivity are essential.

Lowly doped Semiconductors and insulators have a high Seebeck coefficient, but they also have low electrical conductivity. Metals have low Seebeck coefficient but high electrical conductivity. For metals and degenerate semiconductors, the Seebeck coefficient depends inversely on the carrier concentration (n) and directly on the charge carrier effective mass (m*) as shown in equation 3 [4]:

𝑆𝑆 = 8𝜋𝜋2𝑘𝑘𝐵𝐵2

3𝑒𝑒ℎ2𝑚𝑚∗𝑍𝑍( 𝜋𝜋

3𝑛𝑛)2 3 � (3)

where 𝑘𝑘𝐵𝐵 is the Boltzmann constant, h is the Planck’s constant and e is the electron charge.

On the other hand, the electrical conductivity (σ) has a direct dependency on doping concentration and mobility (µ), which can be written as in equation 4:

1𝜌𝜌

= 𝜎𝜎 = 𝑛𝑛𝑛𝑛µ (4)

Equation (3) and (4) reveal example of materials conflict to achieve a high power factor in TE materials.

1.3.2 Thermal Conductivity

In a TE material, there are both free electrons and holes, which carry charge and heat. The term thermal conductivity (κ) in equation (1) refers to electronic contribution of thermal conductivity (κe) where electrons and holes carry heat as well as lattice thermal conductivity (𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜) where lattice vibrations transport the heat through the lattice as shown in equation 5:

𝜅𝜅 = 𝜅𝜅𝑒𝑒 + 𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜 (5)

Electronic thermal conductivity 1.3.2.1

The electronic source of the thermal conductivity is linked to the electrical conductivity through the Wiedemann-Franz law as shown in equation 6 [4]:

𝜅𝜅𝑒𝑒 = 𝐿𝐿𝜎𝜎𝑍𝑍 = 𝑛𝑛𝑛𝑛µ𝐿𝐿𝑍𝑍 (6)

where L is the Lorenz factor and T is the absolute temperature.

The Lorenz factor is 2.4 10-8 J2K-2C-2 for free electrons but it depends strongly on doping concentration[4].

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Lattice thermal conductivity 1.3.2.2

An efficient method to enhance ZT is to reduce the lattice thermal conductivity because it is the only parameter which is not determined only with electronic structure. Therefore it can be optimized independently without significantly affecting the electrical conductivity.

The classical kinetic theory gives an approximation for lattice thermal conductivity as shown in equation 7[10]:

𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜 =13𝐶𝐶𝑣𝑣𝑙𝑙𝑣𝑣𝑠𝑠 (7)

where 𝐶𝐶𝑣𝑣 is the specific heat, 𝑙𝑙R is the phonon mean free path and vs is the average sound velocity. For low temperatures (below 40K), the 𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜 is controlled by Debye’s law 𝐶𝐶𝑣𝑣 (T3) however for higher temperatures 𝐶𝐶𝑣𝑣 reaches the classical value 3R, which means 𝐾𝐾𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜 depends on 𝑙𝑙R which is determined by phonon-phonon scattering.

Therefore, attempts are being made on scattering of phonons in different wavelengths to achieve minimum thermal conductivity using different methods such as grain boundary or interface scattering or mass fluctuation scattering (alloying)[11].

1.4 State of the art thermoelectric materials

The state of art TE materials can be divided into three groups according to working temperatures. So far, the most commonly used TE material for low temperatures materials (near room temperature up to 473K) is n- and p-type Bi2Te3. This semiconductor was discovered in the beginning of 1950’s as a promising TE material[12]. Soon after, mixing with Sb2Te3 and Bi2Se3 revealed to be an effective method to enhance the ZT due to manipulation of carrier concentration and lattice thermal conductivity. This material demonstrated a ZT value in the range of 0.8 to 1.1, depending on the type of alloying [4].

For mid temperature (500 to 900K) applications, the most widely used materials belongs to other telluride family: PbTe, GeTe, and SnTe. More complex structures e.g. (GeTe) 0.85(AgSbTe2)0.15 commonly referred to as TAGS have shown ZT values larger than 1.2[4].

For high-temperature applications (>900K), silicon germanium (SiGe) alloy is excellent candidate. An early study on SiGe alloy as TE material was undertaken at 1950 by Iffoe[13]. SiGe alloy was used for long term to convert radio-isotopic heat to electricity for a space mission. The efficiency of SiGe at high temperatures is large and ZT has a peak around 1 at 1173K to 1223K for p-type and 1.5 for n-type [14,15].

Figure 3 shows the ZT of the state of the art of TE materials at different operating temperatures.

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Figure 3 ZT of the state-of-the-art bulk TE materials versus their operating temperatures (reproduced from ref.[4]).

1.5 Advances in ZT enhancement

In principle, ZT can be enhanced using some strategies to improve the power factor and/or reduce the thermal conductivity. This is a quite challenging task since these parameters are strongly correlated as mentioned previously. However there are few methods to separate these parameters and improve ZT as will be discussed in the following sections.

1.5.1 Strategies for lowering thermal conductivity

Alloying 1.5.1.1

An approach to reducing the lattice thermal conductivity via alloying was already proposed in the late 50’s. Alloy scattering, which is sometimes called mass-difference scattering, can be increased using atoms with different masses. The rate of scattering depends on the mass difference magnitude and composition of the elements in the alloy. It was shown that alloy scattering can reduce thermal conductivity one to two orders of magnitude. For example, different experimental studies reported the thermal conductivity of Si can be reduced from 150 W/m.K to 5-15 W/m.K for Si0.8Ge0.2 alloy[16–18]. The thermal conductivity of SiGe is less temperature dependent than for elemental Si unless the temperature reaches values where phonon-phonon interaction becomes dominant[19,20].

Nano-scaling 1.5.1.2

Low dimensional materials like quantum wells, nanowires (NWs) and quantum dots offer new approaches to alter the TE properties by governing the electron and phonon transport. In bulk materials, the internal scattering is a dominant factor in heat transfer while as the size shrinks the boundary-phonon scattering frequency increases. As a result, in nano-scaled materials, the interface scattering of phonons controls the heat conduction[19].

Figure 4 shows the accumulation of thermal conductivity versus phonon mean free path in Si. The graph shows that phonons with a mean free path of 100 nm to 10 µm which are a minority of the phonon states, contain 70% of thermal conductivity at room temperature[21].

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Figure 4 Thermal conductivity accumulation versus mean free path for Si at two different temperatures (reproduced from ref

[21]).

Figure 5 shows TE properties of Si NWs in terms of NW diameter from 22 nm to 115 nm as a function of temperature. For example, the thermal conductivity of Si NWs drops by downscaling the diameter from 40 W/m.K to 10 W/m.K at near room temperature [22]. The result shows the strong influence of nano-scaling on utilizing the phonon transportation and possibility of introducing interfaces and boundaries to reduce thermal conductivity.

Figure 5 variation of thermal conductivities of Si NWs with NW diameter(reproduced from ref.[22])

1.5.2 Methods to increase the power factor

Best electronic band structure 1.5.2.1

In addition to the reduction of thermal conductivity, the other alternative to increase ZT is the improvement of power factor. This can be realized by an increase of the electrical conductivity or the Seebeck coefficient or a simultaneous increase of both.

Boltzmann transport theory can be used to understand the mechanism of electronic and thermal transport in solids. According to the Mott equation which perhaps is the most frequently used formula for the Seebeck coefficient in metals and degenerate semiconductor, as expressed in

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equation 8, the Seebeck coefficient depends on temperature (T) and electronic conductivity σ (E) determined as a function of band filling or Fermi energy (EF).

𝑆𝑆 = 𝜋𝜋2

3𝑘𝑘𝐵𝐵2𝑇𝑇𝑒𝑒

𝑐𝑐𝑛𝑛𝜎𝜎(𝐸𝐸)𝑐𝑐𝐸𝐸

ǀ𝐸𝐸=𝐸𝐸𝐹𝐹 (8)

If we assume that electron scattering is not dependent on energy, then the σ(E) is proportional to the density of states (DOS) at E. Figure 6 compares two hypothetical DOS diagrams. In Figure 6a, the DOS is varied more rapidly than in Figure 6b. The more rapidly varying DOS is then expected to have a larger Seebeck coefficient according to the Motts equation[10].

Figure 6 Two different hypothetical DOS consideration showing the effect of complexity around Fermi level, Ef (reproduced

from ref.[10]).

In general, S in the Mott equation can be viewed as the change of variation in σ (E) near the Fermi level. This means that the Seebeck coefficient depends on a relation of electronic structure asymmetry and scattering rate around Fermi level. Therefore, the design or improvement of TE materials, one needs to consider the complexity either in electronic band structure or scattering rate around Fermi level in an interval of few kBT. Figure 7 shows the two hypothetical electronic band structures. It can be expected the electronic band diagram in Figure 7b with multiple extrema in conduction and valence bands has a higher power factor in comparison to simple band structure in Figure 7a.

Figure 7 Simple and complex hypothetical band diagrams (reproduced from ref. [10]).

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L. D. Hicks and M. S. Dresselhaus have shown that the ZT is proportional to the effective mass of carriers, mobility and lattice thermal conductivity using following equation [23]:

𝑍𝑍 ∝ 𝛾𝛾1

3𝜋𝜋2(2𝑍𝑍𝑘𝑘𝐵𝐵)

32�𝑚𝑚𝑥𝑥𝑚𝑚𝑦𝑦𝑚𝑚𝑧𝑧

𝑛𝑛. 𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜𝑘𝑘𝐵𝐵

2𝜇𝜇𝑥𝑥 (9)

where 𝛾𝛾 is the degeneracy of band extrema, 𝜇𝜇𝑥𝑥 is the mobility in transport direction, 𝜅𝜅𝑐𝑐𝑙𝑙𝑜𝑜𝑜𝑜 is the lattice thermal conductivity and mx, my and mz are the effective masses in different K- space directions.

This equation has several consequences, which might be considered for TE material selection and improvement. At first the band degeneracy, 𝛾𝛾, which is the number of valleys in conduction or peaks in valence band, should be high. This assumption is required since each band extremum contributes a certain to Seebeck coefficient and electrical conductivity when they are occupied by carriers (this is true if scattering between valleys is minimized). Secondly, large effective masses, high carrier mobility and low lattice thermal conductivity are necessary for high ZT.

In conclusion, the material parameters that determine the band structure especially near the Ef plays a key role in TE properties and should be considered for optimization of the design or selection of TE materials with high FOM[10].

Quantum confinement 1.5.2.2

The first idea about quantum confinement implication on the Seebeck coefficient enhancement was proposed by L. D. Hicks and M. S. Dresselhaus [23,24] at the beginning of 1990. According to the Mott equation, the electronic band structure with a sharp feature in the electron density of states results in a high Seebeck coefficient. Hick and Dresselhaus showed that when the structure dimension approaches nanometer size, a dramatic change in the density of states appeared which opened up for an independent alteration of the Seebeck coefficient.

Figure 8 shows the change in the density of states as the size of the structures reach to the nanoscale, demonstrating different sharp features in comparison to the continuous variation of bulk 3D crystal[24].

Figure 8 Change of DOS as the size/dimensions are reduced reaching to the nanoscale(reproduced from ref[24]).

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Electron energy filtering 1.5.2.3

The idea of enhancement of the Seebeck coefficient using energy filtering was introduced for the first time by Shakori et al. once they proposed the use of solid state thermionics for TE applications[25,26]. According to the Boltzmann transport theory for quasi-equilibrium and diffusive electron transport, the Seebeck coefficient is proportional to the mean excess energy (E-EF) as shown in equation 10 [27]:

𝑆𝑆 = −𝑘𝑘𝐵𝐵𝑒𝑒 ∫

(𝐸𝐸−𝐸𝐸𝐹𝐹)𝑘𝑘𝑏𝑏𝑇𝑇

𝜎𝜎(𝐸𝐸)𝜎𝜎𝑑𝑑𝑑𝑑 (10)

This means at a given carrier concentration; higher mean excess energy is equal to higher Seebeck coefficient. If a potential barrier is introduced to electronic band structures depending on the barriers energy level, the carriers with energy lower than mean excess energy are filtered from transport. This scheme will lead to overall improvement in the Seebeck coefficient. In the light of high Seebeck coefficient due to filtering, the carrier concentration tends to decrease, which leads to lower electrical conductivity. Therefore, the scheme should be applied in such a way that reduction in electrical conductivity can be compensated by the increase in the Seebeck coefficient for high power factor. The idea of energy filtering can be realized with the barriers with the energy of (1 to 10 kBT) in the conduction band for n-type materials or in the valence band for p-type ones[27,28]. These barriers can be introduced to the system using different techniques including embedded nano-inclusions, grain boundaries and/or defects.

1.6 Si-based materials for TE applications

So far, many materials with decent ZT values have been proposed for different temperature applications. However, most of these materials are either difficult to synthesize/fabricate or the constituents are environmentally hostile[2]. Si is a cheap and abundant material with a well-known fabrication process. This makes Si integration into nano-electronic devices smooth and mass manufacturing of reliable Si TE modules possible in near future.

The problem with Si integration in TE devices is the low efficiency/performance with a ZT less than 0.01. However, recent reports on Si NWs demonstrate ZT values over 1 due to the significant reduction of thermal conductivity[22]. It seems that further improvement in ZT for Si, requires concentrating on the power factor in association with reduction of thermal conductivity. In this case, one alternative is to use new categories of Si compatible materials e.g. SiGe, GeSn(Si) which can conduct electrons better than Si while thermal conductivity remains same or is even lower than Si[29].

1.6.1 SiGe

Silicon germanium alloys (SiGe) raised an enormous interest for TE application when their low thermal conductivity behavior was discovered. The carrier mobility in SiGe is slightly lower as compared to Si but the thermal conductivity can be decreased by 10 to 15 times. The reason behind this behavior is that the carriers are scattered in SiGe by neutral impurities and not charged impurities. In this case, phonons can be scattered by a combination of mass fluctuation and strain field of Si and Ge atoms[13].

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The efficiency of SiGe reaches a maximum at high temperatures. For example, ZT of n-type SiGe has a peak around 1 at 900-950 °C[30]. Nevertheless, for the p-type SiGe, the ZT values are lower and a peak ZT of 0.95 can be obtained in the temperature range of 800-900 °C [31] . Unfortunately, this TE efficiency becomes low at medium and low temperature application, but recent developments of nanostructured materials e.g. NWs have inaugurated the possibility to further enhance the efficiency of SiGe for medium temperature applications [32] .

1.6.2 GeSn (Si)

In recent years, GeSn has attracted a great attention in photonics and electronics due to its direct band gap behavior (for Sn content of 6-8%) as well as higher mobility performance for both holes and electrons[33–36].

The motivation of using this material for TE application originates from the expectation of higher conductivity of GeSn and lower thermal conductivity compared to Si. GeSn has larger exciton Bohr radius than Si, which makes it possible to observe quantum confinement in NWs with a large diameter. Furthermore, incorporation of Sn in Ge can enhance the carrier mobility and tune the band structure. In addition, Sn atoms have a large mass with a weaker bond to Ge atoms and this causes lower thermal conductivity for GeSn compared to Ge and Si(Ge)[29,37]. In addition to GeSn, a ternary compound of GeSnSi is of great interest to scientists for photonic, electronic as well as TE applications [29]. GeSnSi alloy has higher chemical compatibility in comparison to GeSn on Si substrates. Moreover, it can act as a lattice-matched template for growth of subsequent strained layers like Ge. To add to them, the main feature of GeSnSi alloy is independent control over lattice constant and bandgap alloying which let different bandgap for alloys at a fixed lattice constant. It is expected that the thermal conductivity of GeSnSi alloy is even lower than GeSn due to the higher mass and bond disorder[29].

1.7 Objectives

The primary objective of this thesis is to develop new compositions of group IV materials which can be integrated on Si platform for TE application that can also be used for a variety of other applications by applying chemical vapor deposition (CVD) technique. The considered compounds were GeSn, GeSnSi and SiGe alloys.

The key tasks for this objective include:

• Develop growth parameters and optimize the manufacturing process • Characterization of materials quality using different techniques

The secondary objective is to design and fabricate nanostructures preferably NWs, capable of integration in a TE generator. The main aim is to develop a process, which can be implemented in industrial application, easy to manufacture, CMOS compatible and to avoid expensive high resolution lithography.

The final objective of this project is to evaluate the TE properties of NWs based on aformentioned-alloys to identify the most promising materials compositions and architectures.

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Chapter 2 Fabrication of low dimensional materials

There are many fabrication techniques for low dimensional materials. In this chapter, the discussion will be limited to a brief survey of techniques used in this project.

2.1 Epitaxy

The term epitaxy refers to grow a single crystalline material on top of a crystalline substrate.

A challenge in epitaxy may occur during hetero-epitaxial growth when the lattice parameters of the film and the substrate are different. This lattice mismatch requires energy to the crystal atoms to be arranged to the substrate crystal structure. This mechanical energy is called strain energy and it is being stored during the growth. If grown layer exceeds a critical thickness, the crystal begins to release the strain energy and the strain relaxation occurs during the growth. This leads to interfacial defects in the hetero-structures which cause changes in performance of electronic, optoelectronic and TE devices[38–40].

Figure 9 shows different situations for lattice mismatch between the substrate and the epi-film.

Figure 9 Growth of film (epi layer) on substrate with different lattice mismatches resulting in different lattice strains

There are various techniques for epitaxial growth of thin films, which are distinguishable with respect to growth pressure and the nature of gas precursors. Most common growth techniques are metal organic vapor phase epitaxy (MOVPE), reduced pressure chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE) and ultra-high vacuum chemical vapor deposition (UHV-CVD)[41].

2.1.1 CVD process

Chemical vapor deposition (CVD) is a technique where a solid layer is deposited from vapor through chemical reactions on a heated substrate. By varying the deposition parameters, including e.g. temperature, gas flow and gas mixture, a wide range of materials with different physical and chemical properties can be grown[38,42].

The incoming molecules to the substrate surface will undergo a series of reactions until they get absorbed on dangling bonds on the surface as shown in Figure 10. The important reactions occur when the molecules are diffused downwards from the gas boundary and interact with each other in the gas phase or on the substrate surface (lateral diffusion, absorption, and desorption)

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Figure 10 Simplified reactions of molecules in a CVD process reproduced from [43]

2.2 Condensation process

SiGe on insulator (SGOI) is a straightforward material for implementation in semiconductor devices. SGOI wafers offer several benefits compared to SiGe in bulk when totally isolated devices can be processed[44]. For example, for TE devices in order to avoid thermal and electrical leakage through the substrate, the device layer is preferred to be on the insulator. In the case of Si or even Ge, there are SOI and Ge on insulator (GOI) wafers available in the market but the SGOI wafers are not easily accessible.

One possible method to form SiGe on insulator is applying high temperature oxidation of a single crystalline SiGe layer grown on SOI substrates [45–48]. The mechanism of this method is based on the higher reactivity of Si atoms with oxygen than Ge atoms due to the lower energy formation of SiO2 than GeO2. This results in the formation of thermal SiO2 on top of the SiGe layer. At the same time, Ge atoms diffuse downwards vertically until oxide layer underneath stops them. In the best case, it is possible to obtain a Ge layer on insulator if all Si atoms can be oxidized, although this is a very hard and time-consuming process.

2.3 Nanowire fabrication

The fabrication techniques to make NWs can be categorized in two main categories[49]

The bottom-up can be defined when structures are assembled from their subcomponents in an additive approach. In this respect, the vapor-liquid-solid method can be mentioned as the most common technique.[50].

The top-down, when NWs are mostly fabricated from a bulk material using a sequence of lithography and etching steps. There are many methods to mention including E-beam lithography (EBL), optical lithography, side wall transfer lithography (STL) and focused ion beam technique (FIB) [51–54].

2.3.1 Optical Lithography

Optical lithography technology has been one of the key enablers and drivers for the semiconductor industry for the past several decades. The technique is fast to pattern structures,

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however, the resolution is limited to the wavelength of the illumination source, which is mostly mercury. Such source generates 400 nm wavelength with spectral lines at 436 nm, 405 nm and 365 nm so called G-line, H-line and I-line. Many alternative technologies have been developed to improve the performance and resolution of optical lithography because it is economical to develop existing technology rather than a replacement[55].

2.3.2 Focused ion beam (FIB) technique

Focused ion beam recognized as FIB is a method used particularly for material analysis, deposition, and site specific sputtering or milling. FIB system resembles SEM while the SEM uses electrons to image the sample, a FIB uses ions instead for manipulation and imaging [54,56–58].

The FIB system possess both electron and ion beam columns, which allows the same structure to be examined using either electron or ion beam. The column for electrons usually positioned vertically and for ions placed with 45 to 52 degrees. Typically for milling, the samples should be tilted 52 degrees [56].

There are different sources for ions for example He+, Ga+ and Xe+, which lead to different ion-solid interaction. In this study, we are using one of the liquid-metal ion sources, gallium. The FIB with Ga+ source is a conventional method for material treatment because Ga has low melting point, high stability, long life time and enough mass for rapid ion milling[54]. Figure 11 demonstrates the ions interaction with samples, which generates different scattered or secondary ions and electrons.

Figure 11 Interaction of ions with samples during FIB process( reproduced from [54])

2.3.3 Side wall transfer lithography (STL)

Due to the difficulties of bottom-up fabrication processes like synthesis, making ohmic contact to electrodes, transferring and integration, planar top down NWs fabrication process is more favorable. The STL process is one of the options due to CMOS compatibility, simplicity and the realization of high density, which can be carried out without expensive high-resolution lithography. This technology only uses common optical lithography to define NWs. The technique is based on anisotropic etching of support material and conformal deposition which

15

leaves spacers to act as a mask to define NWs[53,59–61]. A detailed description of STL is provided in the next chapter.

2.4 Contact Resistance

Contact resistance is not an important issue in bulk materials as it is only a minor fraction of the total resistance. However, for low dimensional materials like NWs, the contact resistance can make a significant role of the total resistance. This problem comes from the large aspect ratio in NWs, which magnifies the Schottky barrier formation at the metal-semiconductor interface. To overcome this parasitic effect, formation of silicide layer at the contact region is necessary.

Among silicides, NiSi is commonly used for Si in CMOS technology[62]. NiSi has a low resistivity, high thermal stability, low silicon consumption and excellent formability for low dimensional structures like NWs. There have been extensive studies on silicide phase formation of Si with Ni[63–67] but there is a lack of detailed study on phase formation of Ni with other Si compatible material like SiGe and GeSn.

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Chapter 3 Material development and processing

3.1 Epitaxial growth

In this study, the samples were grown in a single wafer RPCVD reactor (ASM Epsilon 2000). The Si or SOI wafers are chemically cleaned and loaded in a load-lock, which is purged by N2 gas for 30 minutes to avoid any O2 contamination. Then the wafers are transferred by wafer handling system to the main reactor chamber and are placed on the susceptor. Halogen lamps heat the susceptor and wafer to temperatures ranging from 200 to 1100 ᵒC. Different reactant gasses are connected to the reactor ranging from Si2Cl2H2, Si2H6 and SiH4 as Si precursors, GeH4 and Ge2H6 as Ge precursor, 1% PH3 in H2 for n-type doping, 1% B2H6 in H2 for p-type doping and SnCl4 as Sn source. The mass flow controllers (MFCs) provide the required flux for the growth. Hydrogen is a pilot gas as well as dilution gas for the dopant gasses. HCl is used for etching the reactor before epitaxy. The exhaust gases will be neutralized in a scrubber and then extinguished in a burner system.

3.1.1 GeSn (Si) epitaxy

Although many theoretical studies have predicted that the GeSn alloys have excellent material properties, but the epitaxy of GeSn material has a significant problem, which originates from the large lattice mismatch between Ge and Sn (14.7%) as well as low solid solubility between Sn and Ge (<1%)[68].

The main problem with GeSn epitaxy is the tendency of Sn to segregate on the surface. To overcome this issue, low temperature epitaxy below 350 ᵒC was applied[29,69–72].

Furthermore, the GeSn has a poor thermal stability which makes its integration difficult into devices. Despite such problems and difficulties, huge efforts have been made on epitaxial growth of GeSn for electronic and photonic devices[73–75].

In this study, GeSn layers with different Sn concentrations were deposited in an RPCVD reactor. A Ge layer with a thickness of 200 nm to 2 µm was grown on a Si wafer to act as a buffer layer. The growth temperature was kept around 270 °C to 400 °C to avoid Sn precipitation.

This temperature range gives the possibility of different Sn incorporation tuned with regulating SnCl4 flow rate. Furthermore, the type and quantity of strain in epi-layers were tailored by the choice of the buffer layer, layer thickness, and composition of the alloy.

A GeSn layer with compressive strain can be grown on strain-relaxed Ge buffer layer whereas relaxed GeSn layers can be deposited on Si substrate directly. Tensile strained GeSn was realized by growth on relaxed GeSn layers with higher Sn content. Figure 12 demonstrates how strain was engineered in GeSn layers.

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Figure 12 Different structures to grow strained and non-strained GeSn layers (paper III)

The interest on the incorporation of Si in GeSn arises from possibility to adjust bandgap and lattice constant independently. This significant feature gives the opportunity to grow lattice mismatched layers with different bandgaps which gives different properties[29,76]. Extending to ternary GeSnSi layer was realized by using SiH4 or Si2H6 gasses as Si precursors. In this respect, different GeSnSi layer with different Si and Sn contents were developed.

3.1.2 SiGe epitaxy

In this work, the SiGe layer (Ge content of 26%) was grown on Si-on-insulator (SOI) substrate. The layer was grown using SiH4 and GeH4 precursors at temperature 560ᵒC. The final aim was to fabricate SiGe-on- insulator (SGOI) with almost 50% Ge content using thermal oxidation. This Ge content was chosen because of lowest thermal conductivity according to the literature for SiGe[32].

3.2 Condensed SGOI formation

The experimental work was started by epitaxial growth of 100 nm Si0.74 Ge0.26 layer on SOI wafers. The SOI wafers at the beginning had a 200 nm thick Si on top of SiO2. By repeated thermal oxidation and HF etching of formed SiO2 layer, the top Si layer was thinned to 50 nm. To avoid the formation of GeO2 on top, a cap layer of Si with thickness of 10 nm was also deposited. The one- step or two-step oxidation process was applied to condense the SiGe layers. All the samples were first dry oxidized at temperature 1050 ˚C or 1150 ˚C for a certain time and eventually followed by few hours at 850 ˚C. The thickness and Ge content were controlled using different temperatures and process times. The process continued by annealing for 1 hour in N2 ambient at 1150 ᵒC to minimize defects in the layer. Figure 13 shows the schematic of condensation process.

Figure 13 Schematic view of condensation process steps (paper IV)

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3.3 Fabrication of NWs using FIB technique

FIB is an alternative method to make NWs using milling option. In this study, at the first stage, SiGe wires with width of 1000 nm width were processed by using conventional I-line 365 nm optical lithography. In the next step, we used FIB technique to decrease the width of wires to sub-100 nm with current of 0.5 nA.

FIB is a destructive method for the surface due to high energy ions bombarding. There are different ways to prevent or decrease this damage like using low current ion source, the tilted incident beam to sample or using a protective SiO2 layer. In this study, we used SiO2 as a protective layer to prevent subsequent eventual damage. Figure 14 shows the wires before and after milling down to 20 nm width. In this work, milling of samples was undertaken in a FIB emission scanning electron microscope (QUANTA 3D FEG) at an accelerating voltage of 30 kV.

Figure 14 Thinning of SiGe NWs using Focused ion beam technique[56]

3.4 Fabrication of NWs using STL technique

The second group of sub-100 nm SiGe NWs was fabricated by using STL technique. Figure 15 depicts a schematic view of STL process. The method is based on the sequence of plasma enhanced chemical vapor deposition (PECVD) and reactive ion etching (RIE) of SiO2, SiN, and a-Si materials.

STL process starts with PECVD of 40 nm SiO2, 100 nm a-Si and 40 nm SiN as a hard mask as it was presented in Figure 15a. In the second step, NWs pattern is stepped using I-line lithography.

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The process continued with RIE etching of SiN (Figure 15b) and a-Si to form vertical sidewall which is depicted in Figure 15c. A 60 nm SiN layer was deposited and then etched selectively to form the spacers (Figure 15d and e). The a-Si support material is later removed selectively on SiN spacer and underlying SiO2 hard mask. Using the defined 60 nm SiN spacers as a mask, the underlying SiO2 layer is etched and finally the spacer pattern is transferred to the underlying SiGe device layer by etching the SiGe (Figure 15(f-h)).

Figure 15 Schematic image of STL process to fabricate sub-100 nm SiGe NWs

The STL technique provides the opportunity to define the high volume of NWs per wafer in a time efficient manner.

3.5 Ni-SiGe and Ni-GeSn formation

In order to investigate the reaction of Ni with SiGe, two different techniques were applied to make Ni-SiGe phase. The p-type Si substrate was chosen and standard surface cleaning including the removal of native oxide was applied before CVD deposition of 52 nm Si0.81Ge0.19 epi-layer followed by deposition of 10 nm Ni. The wafer then was sliced to square-shape pieces and samples divided into two different groups. The first group followed common rapid thermal annealing (RTP) process for the 30s in N2 ambient. The second group was placed in microwave chamber to experience microwave annealing (MWA) under N2 ambient for maximum 30s for the whole annealing process.

On the other hand, in order to investigate the reaction of Ni with GeSn, in the first step, strained and relaxed Ge1−xSnx (0.01≤x≤ 0.03) were deposited on Si wafer by RPCVD technique. All samples before Ni deposition were cleaned in HF: H2O 1:100 to strip the native oxide. A metal

20

evaporation tool was used to deposit 15 nm Ni on the wafers. The samples were then rapidly thermally annealed at 360 ᵒC to 550 ᵒC for 30 s in nitrogen ambient. Finally, the unreacted Ni was removed by 96% H2SO4.

3.6 Microchip Fabrication

The TE measurement of nanostructured bulk materials have been extensively developed and different apparatus with suitable accuracy and reliability are available in the market [77–84]. In the case of 1D structure the TE measurement is a complicated matter. The common technique is to fabricate microchip and measure transport properties of NWs simultaneously[85–87]. The main benefit of this technique is the capability to measure not only one transport property at a time but all of them at the same time.

In this study, a standard microchip was designed and fabricated. A schematic view of the fabrication steps has been shown in Figure 16.

Figure 16 Schematic view of fabrication process of TE devices

In the first step, the NWs were made either by STL or optical lithography technique followed by dry etching on SGOI wafer (Figure 16a-b). In the next step, optical lithography was applied to pattern and open contacts areas on NWs. In this step, evaporation tool was used for the deposition of 15 nm Ni on the whole wafer. The first lift-off process was done in 1165 developer to strip the Ni from rest of wafer. The samples went through annealing to form Ni-Silicide. The next lithography was done to pattern the electrodes (Figure 16c). The 15Ti/160 nm Pt was deposited by evaporation tool (Figure 16d). The second lift-off was done in this step to finalize the electrodes (Figure 16e). A similar process was done to deposit 15/180 nm Ti/Pt as heaters followed by a final lift-off process (Figure 16f-h).

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3.7 Measurement techniques

3.7.1 The electrical conductivity

All electrical characterizations were performed by using a Keithley parameter 4200-SCS, which enables to characterize semiconductor devices from basic I-V and C-V measurements to advanced forms of electrical measurements. The electrical conductivity of NWs was determined by measuring the resistance at a particular temperature. This realized by injecting a low current to avoid Joule-heating in NWs and plot the I-V curves. Once the resistance of NWs was determined the electrical conductivity can be obtained using the geometry of NWs. In order to improve the accuracy and remove the effect of contact resistance, a four–terminal contact was applied instead of two-contact measurement. The difference of this method with simple I-V obtained from two-contacts is the current passed through the two probes and voltages measured in two other probes. The design of a four-contact measurement is demonstrated in Figure 17.

Figure 17 Four probe measurement of electrical conductivity using different electrode configuration

3.7.2 The Seebeck Coefficient

To define Seebeck coefficient (∆𝑉𝑉∆𝑇𝑇

), requires measurement of the voltage generated (∆V) across NWs due to the temperature difference (∆T). The temperature difference was created using one of the heaters by applying a DC current (Joule heating). The voltages then measured across NWs using inner electrodes. In order to verify the voltage generated is because of NWs, the measurement repeated using the heater on the other side.

The other step to define the Seebeck coefficient is measuring ∆T. We used two different techniques to measure ∆T.

Resistor thermometer 3.7.2.1

We used inner electrodes to measure the temperature across NWs, which was shown in Figure 18. In this respect, the electrodes act as resistor thermometer as temperature change is proportional to the resistance change. We used Pt because it has the most stable temperature-resistance relationship over a broad range of temperature. The resistance of electrodes in cold and hot sides monitored one time with heater-on and one time with heater-off. The resistance difference was converted to the temperature difference using the equation 10.

𝑅𝑅 = 𝑅𝑅0(1 + 𝛼𝛼∆𝑍𝑍) [10]

22

where R and R0 are resistance of electrodes when the heater is on and off, ∆𝑍𝑍 is a temperature difference and 𝛼𝛼 is a thermal expansion coefficient of Pt.

Figure 18 Top view of TE device obtained by optical microscopy showing the measurement method (paper V)

Scanning probe microscopy (SPM) 3.7.2.2

SPM is a family of microscopy which is used to make images from surface of samples using a probe that can scans the surface of sample forth and back. In this study, in order to evaluate the temperature profile along the NWs, a scanning probe microscope (Multiview 4000, Nanonics) equipped with a platinum-gold junction thermocouple probe (Nanonics) was used.

Figure 19 Schematic view of SThM with thermocouple probe

The resulting Scanning Thermal Microscope, SThM, allows for the simultaneous measurement of the sample’s morphology and local temperature with a submicron spatial resolution and an estimated relative temperature resolution about 0.1 K. Figure 19 shows the schematic view of SThM was used in this study.

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3.7.3 Back-gate biasing

A fabricated microchip was used in another configuration to modify charge carriers in the NW arrays[88,89]. To do this, the contacts on sides of NWs serve as source and drain as indicated in Figure 20. The number of charge carriers flowing through the NWs was tuned by the applied back-gate voltage (VG).

Figure 20 Microchip configuration for back gate biasing

Using this technique, the electrical conductivity was modified in a system without physical change of doping concentration. This method avoided scattering, which can decrease mobility in a system due to high doping concentration. The electrical conductivity and Seebeck coefficient were characterized for different back-gate biasing in the range of 0 to 20V.

3.8 Material characterization

3.8.1 Electron microscopy

Using scanning electron microscopy (SEM) the high-resolution image of samples surface was provided. The Energy Dispersive spectroscopy X-Ray (EDS, EDX) was used to measure the abundance of elements in the samples. The SEM used for these measurements was a Zeiss Ultra 55 with additional attached OXFORD X-Mass Energy Dispersive X-Ray spectroscopy detector.

Furthermore, transmission electron microscopy (TEM) was used to examine the layer and interfaces morphology, defects types and density combined with EDS to estimate local film stoichiometry. The TEM used for the characterization was a FEI Tecnai G2 TF20 UT with a field-emission gun operated at 200 kV and a point resolution of 1.9 Å. TEM specimens were prepared by conventional way including grinding cross-sectional to 50 um followed by ion milling to electron transparent. TEM characterization has been performed through collaboration with department of Physics, Linköping University, Sweden, by Dr. Jun Lu.

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3.8.2 X-ray diffraction (XRD)

XRD data measures the scattered X-ray intensity as omega (ω) or/and 2 theta (θ) as defined in Figure 21 and can give structural information like composition, thickness and defects of crystalline structures.

Figure 21 X-ray diffraction technique (the incident angle, w, is defined between the X-ray source and the sample and

the diffracted angle, 2θ, is defined between the incident beam and detector angle)

The most common scan is a coupled scan (here we called rocking curve) which is a plot of scattered x-ray intensity versus 2θ while ω is also changed in a way that ω= (1/2) × 2θ + offset (tilt). The thickness of epi-layers, crystal quality and phase formation was examined using XRD rocking curves (XRD RCs).

On the other hand, reciprocal space maps offer the most complete amount of information for the analysis of strained films. The Reciprocal Space Map collects several omega-2Theta coupled scans, but each scan is collected with a slightly different tilt (offset) in the omega direction. In this study, the high-resolution reciprocal lattice mapping (HRRLM) helped to evaluate defect generation and strain relaxation in thin film layers. It is also used to calculate the atomic percentage of elements [90,91].

For example, to determine the amount of Sn in GeSn alloy, the misfit parameters both perpendicular and parallel to growth direction obtained using key equation listed below:

𝑓𝑓⫠ =𝑠𝑠𝑠𝑠𝑛𝑛𝜃𝜃𝑠𝑠cos (𝜔𝜔𝑠𝑠 − 𝜃𝜃𝑠𝑠)𝑠𝑠𝑠𝑠𝑛𝑛𝜃𝜃𝑐𝑐 cos(𝜔𝜔𝑐𝑐 − 𝜃𝜃𝑐𝑐)

− 1 [11]

𝑓𝑓// =𝑠𝑠𝑠𝑠𝑛𝑛𝜃𝜃𝑠𝑠cos (𝜔𝜔𝑠𝑠 − 𝜃𝜃𝑠𝑠)𝑠𝑠𝑠𝑠𝑛𝑛𝜃𝜃𝑐𝑐 cos(𝜔𝜔𝑐𝑐 − 𝜃𝜃𝑐𝑐)

− 1 [12]

in which ω is an incident beam angle, θ stands for reflection angle, s for substrate and l for the layer.

The total mismatch can be then obtained using equation

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𝑓𝑓 = �𝑓𝑓⫠ − 𝑓𝑓⁄⁄�1−𝜗𝜗1+𝜗𝜗

+𝑓𝑓⁄⁄ [13]

𝜗𝜗 is the Poisson ratio which can be calculated for GeSn using elastic parameters :

𝜗𝜗 = 𝐶𝐶12(𝐶𝐶11+𝐶𝐶12)

[14]

The elastic parameters are provided in table 1.

Table 1 Elastic constants of Ge, Sn and Si material[35]

Elastic constant Ge Sn Si C11 132 69 167 C12 49.4 29 65

A Cij for a certain composition can be estimated using linear equation

𝐶𝐶𝑖𝑖𝑖𝑖(𝐺𝐺𝑛𝑛𝑆𝑆𝑛𝑛) = (1 − 𝑥𝑥)𝐶𝐶𝑖𝑖𝑖𝑖(𝐺𝐺𝑛𝑛) + 𝑥𝑥𝐶𝐶𝑖𝑖𝑖𝑖(𝑆𝑆𝑛𝑛) [15] And finally, the Sn content was extracted from lattice constant using the following equation.

𝑎𝑎𝐺𝐺𝑒𝑒𝑆𝑆𝑛𝑛(𝑥𝑥) = (𝑥𝑥)𝑎𝑎𝑆𝑆𝑛𝑛 + (1 − 𝑥𝑥)𝑎𝑎𝐺𝐺𝑒𝑒 + 𝜃𝜃𝑆𝑆𝑛𝑛𝐺𝐺𝑒𝑒𝑥𝑥(1 − 𝑥𝑥) [16] 𝜃𝜃𝑆𝑆𝑛𝑛𝐺𝐺𝑒𝑒 is a constant which relates to GeSn and is 0.166 Å for x ≤ 0.20[35]. 3.8.3 Rutherford Backscattering (RBS)

This technique relies on the bombardment of the sample with high energy He2+ ions. As a result, the backscattering energy of particles is measured. Since this energy is related to the mass of incident and target atoms, the energy spectra of He ions backscattered from sample give information about quantitative compositional of the sample, uniformity and film thickness. In this study composition and thickness of the alloys were obtained using RBS technique. The RBS analysis has been performed in the Ion Technology Center (ITC), at Uppsala University.

3.8.4 Atomic force microscopy (AFM)

AFM is one of the types of scanning probe microscope (SPM), which is very effective to evaluate surface morphology and topology of samples. This tool includes a tip mounted on a cantilever. When a tip scans a surface, displacement generated due to interatomic forces between the tip and the surface. In order to measure the cantilever orientation a laser beam is transmitted and reflected from the cantilever, where reflected beam is detected with a sensitive detector. The output is sent to a computer for processing data to provide a topographical image of surface with atomic resolution. In this study, AFM was used to measure surface roughness of Ge, SiGe and GeSn samples.

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Chapter 4 Results and Discussions

4.1 Characterization of GeSn epitaxial layers (paper I&II)

4.1.1 Compressive strained GeSn samples

In order to grow high quality GeSn, an intermediate Ge layer was grown. The quality of Ge layer is crucial as the defects in Ge buffer can propagate into the GeSn cap layer. The high quality Ge layer was grown with a two-step thermal profile: low temperature epitaxy at 400 ᵒC with a thickness of 50 nm to avoid three dimensional islands and then high temperature epitaxy at 720 ᵒC to improve the surface roughness from the initial nucleation layer. In this way, Ge layers with good epitaxial quality on Si can be grown. Three different GeSn samples were grown on this Ge buffer at 290, 300 and 320 with SnCl4 flux of 0.6 to 1.3 g/h and Ge2H6 partial pressure of 4.9 mtorr.

In this category, the growth of GeSn layers with higher amount of Sn leads to Sn segregation to the surface. Figure 22 shows top view SEM image of GeSn layers with different Sn concentration. The Sn segregation appears as dots on the surface for Ge0.975Sn0.025 and Ge0.965Sn0.035 samples.

Figure 22 SEM images of Ge1-xSnx layers grown on Ge virtual layers: a) x=0.035, b) x= 0.025, c) x=0.02 [92]

4.1.2 Optimized compressive strained GeSn samples

Further effort was made on optimization of GeSn quality. The high GeH4 or Ge2H4/SnCl4 ratio with accurate control, low growth temperatures, the growth of high quality Ge buffer leads to deposition of segregation free GeSn layers up to maximum 9.5 percent Sn content for strained GeSn layers in CVD chamber at atmospheric pressure using GeH4 as Ge precursor.

The second category of high quality GeSn samples was deposited on 2 µm Ge buffer. Similarly, this Ge buffer was grown in two steps; low temperature and high temperature epitaxy on Si substrate. The low defect density as low as 107 cm-2 were detected on this Ge buffer layer using etch-pit density (EPD) technique. In the next step, 50 nm GeSn with different Sn composition were grown at a temperature of 270 ᵒC to 400 ᵒC under different SnCl4 flow rate up to 2 g/h and Ge2H6 partial pressure of 80 mtorr.

Figure 23a shows the high resolution XRD (HR-XRD) RCs of GeSn with different Sn composition. The presence of sharp peaks followed by fringes indicates high quality crystalline GeSn layer.

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Figure 23 HR-XRD RCs of compressive GeSn samples and HRRLM of GeSn with 9.5% Sn content (paper II)

The HRRLM of GeSn with 9.5 percent Sn was presented in Figure 23b. The GeSn and Ge peaks are aligned along the vertical direction showing the highly compressive strained GeSn layer with respect to Ge buffer.

4.1.3 Strain-relaxed GeSn samples

The relaxed GeSn layers were grown directly on Si substrate using a thin layer of Ge seed at 290–380 ᵒC in an RPCVD reactor.

The HRXRD RCs and HRRLMs of relaxed GeSn samples are displayed in Figure 24a. The GeSn peaks shift to the left as the Sn content increased to 15 percent. The HRLLM of 15% GeSn layer was presented in Figure 24b showing how GeSn placed on a relaxed line with respect to Si and Ge seed layer. As it was revealed in the map, the GeSn peak was broadened in ω-direction, which confirms the presence of defects in the layers. Indeed, this broadening is expected as there is a large lattice mismatch between GeSn and Si substrates.

Figure 24 a) HRXRD RCs of relaxed GeSn samples b) HRRLM of GeSn with 15% Sn content (paper II)

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To investigate the surface morphology of strained and relaxed GeSn samples, the AFM analysis were done on both samples. Figure 25 shows the RMS of samples, which indicated smooth and segregation free samples.

Figure 25 AFM morphology analysis of GeSn sample for strain and relaxed samples (paper II)

One relaxed GeSn sample with 2.61% Sn was used to act as a buffer layer to grow high quality tensile Ge which can be used as direct band gap materials for photonic application.

Figure 26 shows the cross sectional TEM image of GeSn/Ge which was grown on Si substrate. The figure indicates the high density of misfit dislocation is present in GeSn layer but the cap Ge layer has remarkably higher epitaxial quality. The strain in Ge cap layer was measured using HRRLM in Figure 27. It has been seen that the Ge peak is placed above GeSn layer vertically aligned, which shows the layer is strained. The amount of strain is calculated to be 0.52%, which corresponds to a band gap of 0.65 eV.

Figure 26 Cross section TEM image of GeSn/Ge layer[35]

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Figure 27 HRRLM of GeSn/Ge layer grown on Si[35]

4.1.4 Incorporation of Si in GeSn

A series of GeSnSi layers were grown using Si2H6 as Si gas source. The XRD RCs of GeSnSi samples with different Si2H6 partial pressures and constant SnCl4 are shown in Figure 28.

When Si content in the alloy is increased, then the GeSn peak becomes broadened and shifted slightly to the left. This means higher strain has been generated and due to strain compensation between Sn and Si atoms (Sn atom in larger than Ge while Si is smaller than Ge) in the germanium matrix higher Sn incorporation is favorable in GeSnSi alloy. The Sn content in this sample is simulated to be 3% in GeSn and increased to 6% in the presence of Si (Si2H6=80 mtorr) in GeSnSi sample.

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Figure 28 HRXRD rocking curves of GeSnSi layers[92]

The incorporation of Si in GeSn samples was investigated using SiH4 as a precursor at 300 ᵒC as well. It is very interesting to note that SiH4 can dissociate properly in the presence of SnCl4 at low temperature as 300 ᵒC. To do this experiment, a GeSn samples with 6% Sn were selected. The Sn flow was kept constant for all samples while the partial pressure of SiH4 increased from 0 to 20 mtorr. Figure 29 shows the HRRLMs of GeSnSi samples with different Si content. As can be seen, by increasing SiH4 flow, the GeSn peak shifted toward Ge peak and almost disappeared for the sample with highest SiH4 flow due to compensation of strain in Ge matrix.

Figure 29 HRRLM of GeSnSi samples grown using SiH4 at 300 ᵒC (paper II)

4.1.5 P- and n-type doping of GeSn

GeSn layers were in-situ doped to obtain n- and p- type samples using PH3 and B2H6 gases. The SIMS result shows the maximum phosphorus (P) and boron (B) concentrations of 1x1020 and 5x1018 cm-3, in GeSn layers, respectively. Due to strain compensation, higher Sn content in P and B-doped samples (Sn content changed from 3.5% to 5.4% for P-doped sample) was detected.

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Figure 30 presents how Sn content increases by adding dopant atoms, compared with the GeSn sample in the presence of Si (Figure 30c).

Figure 30 Sn content dependency to dopants and Si (paper I)

Figure 31 shows surface SEM images of intrinsic Ge0.965Sn0.035 and P-doped samples. It is clearly visible, the Sn dots get started to consume and become smaller after doping with P due to strain compensation.

Figure 31 SEM image of Sn dots on surfaces of GeSn and GeSn:P

4.2 Ni-GeSn contact formation (paper III)

In order to investigate the formation of ternary Ni-GeSn compound, strained and strained-relaxed GeSn samples were grown on Si wafers. After deposition of 15 nm Nickel, the samples went through RTA at 360, 450 and 550 ᵒC for 30 s. Figure 32a shows the sheet resistivity of samples after annealing and removing unreacted Ni. Independent of strain types; lowest resistivity was obtained at 450 ᵒC for Ni-GeSn alloy.

Figure 32b shows the theta-2theta scan of samples thermally treated at 450 ᵒC which confirms the formation of Ni-GeSn in all three types of samples. The blue symbols show the formation of Sn segregation.

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Figure 32 a) Sheet resistivity b) Theta -2theta scan of GeSn samples where theta is the incident angle (paper III).

The thermal stability and amount of specific phases in the GeSn crystal were strain dependent and the reaction was eased in the absence of strain in GeSn matrix (relaxed layers). Figure 33 shows the cross section SEM images of relaxed and compressive GeSn samples. The thickness of Ni-GeSn phase is larger in the relaxed sample compared to the strained one (70 nm in comparison to 40 nm) showing the easier reaction of Ni-with GeSn in the absence of strain.

Figure 33 cross section SEM images of compressive and relaxed Ni-GeSn

4.3 Ni-SiGe contacts formation

Figure 34 demonstrates the sheet resistivity of Ni-SiGe formed either with MWA or RTP process. The figure clearly reveals the temperature at which the sheet resistance is minimum was obtained 100 ᵒC lower in MWA samples compared to RTP ones. This result is promising since the lower thermal budget for Ni-SiGe is a critical criterion for annealing process in microelectronic device fabrication.

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Figure 34 Sheet resistance versus temperature for SiGe processed with MWA (open squares) RTP ( filled squares)[67]

The XRD and Raman analysis confirmed the monocrystalline Ni-SiGe phase formed at 285 ᵒC for MWA samples although did not appear until 400 ᵒC for RTP samples. The higher resistance with increasing temperature is attributed to grain coarsening and agglomeration of Ni-SiGe phase. The first two cross section TEM images in Figure 35(a-b) show the formation of a uniform layer of Ni-SiGe either with RTP or MWA at 400 ᵒC.

On the other hand, Figure 35(c-d) show the agglomeration of Ni-SiGe at 515 ᵒC, which is more evidenced in MWA samples.

Figure 35 Cross section TEM images of Ni-SiGe a)MWA at 400ᵒC b)RTP at 400ᵒC)MWA at 515ᵒC d)RTP 515ᵒC[67]

The HRRLM analysis was performed to investigate the strain relaxation and defect generation in MWA and RTP samples. Figure 36 shows the HRRLM around [113] for MWA and RTP samples at 284 and 515 ᵒC. The mapping in Figure 36a shows the sharp and well-defined Si and SiGe peaks for RTP sample at 284 ᵒC, which are identical to as-grown samples. On the contrary, MWA sample at 284 ᵒC shows the broad peaks for Si and SiGe which is evidence of defects and strain relaxation in the sample. This situation is similar to the condition of RTP sample at 515

34

ᵒC. Meanwhile, at the similar annealing temperature, the SiGe peak at 515 ᵒC for MWA sample almost disappeared and Si peak became quite broadened. This result shows despite the same annealing temperature, the variation in the processing of samples give rather different results.

Figure 36 HRRLM around 113 for a)RTP sample at 284 ᵒC b)MWA at 284 ᵒC c)RTP at 515 ᵒC d) MWA at 515 ᵒC[67]

4.4 Characterization of SGOI layer (paper IV and V)

The Ge content in a condensed SiGe layer can be tuned through oxidation time and temperature. Figure 37 shows the XRD-RCs of condensed SiGe layers, which were formed

Figure 37 XRD rocking curves of SiGe before and after condensation

at different annealing time and temperatures from an initial Si0.74Ge0.26 epi-layer. In this figure, there is a shift of SiGe peak to lower angles for the condensed samples compared to as-grown sample demonstrating higher Ge content in the layers.

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In this study, the intended Ge content in SGOI layer was 47%. This level of Ge content is crucial as the lowest thermal conductivity for SiGe NWs was measured at this Ge concentration[32]. The oxidation of Si0.74Ge0.26 for 2 hours followed by annealing for 1h 30 min in N2 to improve the quality leads to condensed Si0.53Ge0.47 alloy.

Figure 38 shows XRD RCs and HRRLM around (113) reflection, which is the most sensitive reflection to defects in epi-layers. The reason for this high acquisition for (113) reflection is the incident angle at 2.8ᵒ, which provides the opportunity to cover a large area of the sample to detect defects. Before the condensation process, the Si and SiGe peaks are aligned vertically indicating high quality strained SiGe layer. Nevertheless, after condensation, the SiGe peak is shifted out from its position and become broader. This observation indicates that the defect density in the condensed SiGe is considerably larger than in the as-grown SiGe. Using the HRRLM, the lattice constants in directions parallel or perpendicular to the growth direction in condensed SiGe were determined, and the Ge content and strain relaxation was calculated to be 47%, and 90% in the condensed SiGe layer, respectively.

Figure 38 a) rocking curves b) HRRLM of SiGe before and after condensation (paper V [93] and VI)

The Ge content was also confirmed by the RBS technique. Figure 39 shows the RBS of condensed SiGe, which matches with the simulated curve of Si0.53Ge0.47 sample with 52 nm thickness.

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Figure 39 RBS spectra with simulated curve to verify thickness and composition of condensed SiGe layer (paper V[93])

The quality of condensed SiGe layer was also investigated using TEM. Figure 40 shows the cross section TEM image of thin layer condensed SGOI. TEM observations clearly reveal the presence of defects mostly in form of twins in the layer.

Figure 40 Cross section TEM image of condensed SiGe layer (paper VI)

4.5 Characterization of NWs formed with FIB technique (paper IV)

The width of SiGe wires could be decreased by FIB cutting. In order to protect the wires from the ion damages of FIB a 20 nm SiO2 was deposited prior to the process. The speed of cutting is dependent on the ion beam current. High current can speed-up the milling, however, it can strongly damage the sample. Usually, the FIB operates at 20 kV and current of 4 nA for SEM and 30 kV with different currents for ion milling part. In this study, a current of 0.5 nA was chosen to avoid ion damage, while still achieving a satisfactory speed.

In general, the resistance(R) of NWs increases with decreasing the size of NWs according to.

37

𝑅𝑅 = 𝜌𝜌𝑐𝑐 𝐴𝐴

[17]

where ρ is the resistivity of the material, l is a length and A is the cross section of NW.

Figure 41 show the resistivity versus width for NWs milled by FIB technique for the lightly doped (1017 cm-3) SiGe sample. The equation (17) is not valid as the resistance start to decrease since the NWs thinned down from 1000 nm.

Figure 41 Resistance of NWs milled by FIB for lightly B-doped samples (paper IV)

A sensible explanation for such behavior could be Ga doping of NWs during milling, which decreases the resistance of NWs during extensive milling.

To confirm this statement, energy dispersive x-ray (EDX) analysis was done on SiGe NWs before and after milling to show the existence of Ga atoms. Figure 42 shows the Ge has an x-ray emission line at 1.2 keV while that of Ga is located around 1.1 keV, which indicates a significant shift towards Ga during milling implantation. Meanwhile, the line scan along the NW shows a clear signal of Ga atoms (see Figure 42b).

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Figure 42 EDX spectra of a) Ge and Ga Lα1 position in NWs b) along scan of NWs (Paper IV)

The Ga implantation affects the electronic transport properties of SiGe NWs. This is observed when the NWs were fabricated by an ion-free process such as STL where the resistance of 60 nm width SiGe fabricated with STL shows at least 10 times higher resistance compared to similar NWs prepared by FIB technique. This result revealed the possible dependency of transport properties of NWs to the fabrication method.

The Seebeck coefficient of NWs milled by FIB was measured at room temperature. Figure 43a shows the Seebeck coefficient and electrical conductivity of wire. The Seebeck value decreased from 2577 to 171 µV/K as NWs width decreased from 1000 nm to 60 nm. This significant reduction in the Seebeck values can be explained by increasing in electrical conductivity when Ga atoms were implanted into NWs.

Figure 43 a) Seebeck coefficient and electrical conductivity b) power factor of SiGe NWs prepared with FIB

Figure 43b shows the power factor values for SiGe wires with different widths. Although the maximum Seebeck value was obtained for NWs with 1000 nm width, the maximum power factor was obtained for NWs with 60 nm width as 182 µW/mK2 due to significant improvement in electrical conductivity.

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4.6 Characterization of NWs prepared with STL technique (paper V)

Two SGOI wafers with 47% Ge content were lightly B- or P- doped by using diffusion method when B2H6 or PH3 was flown over wafers at 700 ᵒC for 10 minutes in CVD chamber. The doping concentration was estimated using four probe technique and confirmed with Hall measurement technique in a Van der Pauw configuration. The doping level was determined as 81016 and 1017 cm-3 for P-doped and B-doped samples, respectively. These doped samples were used to fabricate 60 nm width NWs using STL technique. Figure 44 depicts a SEM image of 60 nm wide SiGe NWs fabricated with STL technique.

Figure 44 SEM image of 60 nm wide SiGe nanowire (paper IV)

The TE microchip was fabricated using metallization and lift-off process, and Ni-SiGe phase was formed in the contact area to ensure ohmic behavior. The SEM image of the final device is shown in Figure 45.

Figure 45 SEM top image of a fabricated TE device.

Previous study has reported that SiGe NWs with dimension close to 60 nm with Ge content in range of 40 to 50% can have a thermal conductivity as low as ∼1 W/m.K near room temperature[32]. Even with such low thermal conductivity, the maximum reported ZT for SiGe NWs is only 0.46 at 450 K[32]. This reported ZT confirms that further improvement in

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efficiency of material can be followed by improvement of power factor. The power factor usually improved through increasing doping to enhance electrical conductivity and not through Seebeck improvement. In our SiGe NWs both n and p- types, high Seebeck values were observed. Figure 46 shows the power factor parameters for n and p-type SiGe NWs.

Figure 46 Power factor parameters analysis for SiGe NWs for a,b) n-type c,d) p-type (paper V)

As it is plotted in Figure 46a, the value of the Seebeck coefficient for n-type SiGe has a peak with the value of 8 mV/K which even with low electrical conductivity obtained at this temperature gives a power factor value of 1000 µW/m.K2. It is obvious that the most important reason behind high Seebeck coefficient is related to the large difference between the E-EF (energy states in which transport takes place - fermi energy level) in lowly doped semiconductor, which can lead to high Seebeck values. Nevertheless, another explanation for Seebeck coefficient enhancement is related to the presence of defects created during condensation technique which can act as potential barriers[28,94–97].

Figure 46c shows the maximum Seebeck coefficient value as large as 1.8 mV/K for p-doped SiGe NWs was obtained at 315 K. At first, the Seebeck coefficient in p-type semiconductors is lower than n-type semiconductor due to different effective masses of holes in comparison to the electrons. At second, doping in p-type SiGe NWs is higher than n-type ones and this makes a

41

significant difference in the electrical conductivity. Even though the maximum values of Seebeck coefficient appeared for both samples at 315 K the maximum power factor of n and p-type samples was observed at different temperatures due to the sharp increase of electrical conductivity in the p-type sample.

4.7 Backgate biasing of SiGe NWs (paper VI)

Lightly B-doped (1017cm-3) SiGe NWs were processed in a microchip configuration by using STL technique and these samples were characterized for TE characteristics. In this regard, the back-gate voltage of -20V to 20V was applied to increase the number of carriers by electrostatically doping of SiGe NWs in temperature range of 273K to 450K [98].

Figure 47 shows the TEM images of SiGe NWs. The NWs are single crystalline with well-defined shape after processing.

Figure 47 TEM image of a) TEM diffraction of SiGe NW b) atomic resolution of NWs structure c) periodicity of NWs d) plan

view of NW and e) cross section of NW

Typical current-voltage of NWs at different back-gate biasing (VG) was plotted in Figure 48. The plot demonstrated that increasing the VG at negative region resulted in higher conductivity, therefore, in this study the TE power factor in negative part of VG -20 to 0 V was investigated.

42

Figure 48 I-V curves of SiGe NWs under different VG

Using SThM, the thermal maps were recorded for several heating power ranging sequentially from 0 mW to 1290 mW. Figure 49 shows the thermal maps of NW and the substrate. Using thermal maps, the temperature gradient can be obtained for different heating power.

Figure 49 Topography (top left) and thermal maps of a single NW heated-up with heating power ranging from 0 to 1290 mW. The heating element is situated on the bottom of the maps. For clarity, the color range of the maps is kept constant.

43

For example, a temperature gradient of -0.12 K/µm was measured for the heating power of 1290 mW which implies a temperature difference of 0.84 K across the 7 µm length of the NW between two inner electrodes. This value was in a perfect agreement with the result was extracted from resistor thermometer technique to measure temperature difference along NWs.

The widths of SiGe NWs were 60 nm where no quantum effect is expected. Therefore through this study, the experimental results were compared with the theoretical calculations for bulk SiGe, which was provided using 8-band k.p method[99].

In the first evaluation, the TE power factor parameters of SiGe NWs at 400 K was plotted and compared with the theoretical calculation for bulk SiGe. Figure 50 shows how electrical conductivity increases with VG from 0.4 to 4.2 Ω/cm. Meanwhile, VG has a modest influence on the Seebeck coefficient as it changes only from 2533 µV/K to 2164 µV/K.

Figure 50 transport parameters a) experimental results for SiGe NWs b) theoretical calculation for bulk SiGe (paper VI)

To explain the origin of high Seebeck coefficient in the SiGe NWs, more investigations were performed on the SiGe material. As it was indicated in HRRLM of condensed SiGe (Figure 38b) and was shown by TEM images (Figure 40), the defects were introduced through condensation of SiGe layers. These defects can act as potential barriers to change carrier transportation. Depending on the energy of barrier (barrier height) these defects can avoid transport of low energy carriers and only allow high energy ones. This will increase overall energy of participated carriers in transport, which directly is proportional to Seebeck coefficient[96,100–102].

At this stage, the NWs chip was analyzed by HRTEM to ensure the crystallinity in SiGe has not changed during thermal treatments in processing step. Figure 51 demonstrates the top-view of NWs. Two points attracts the attention for NWs in these micrographs. At first, the NWs have rough and wavy shape but they are crystalline. The characterization of the condensed SiGe layer showed that the SiGe layer contains certain amount of SFs with a density > 1 st/μm. Figure 51

44

Figure 51 TEM images of a NW in a) low magnification and b) high resolution of a selected area in the NW.

doesn’t show SFs because of the SFs out of contrast in [001] zone axis. Secondly, there is a change in brightness along NWs which is diffraction contrast due to slight deviation of crystal orientation. The composition variation was checked with energy dispersive X-ray (EDX) measurements tracing for Ge, Si and SiGe elements. The results indicate a slight composition variation in the SiGe layer.

The TE measurement was performed for the temperature range of 273 to 450 K. Figure 52 shows the conductivity and the Seebeck coefficient behavior for SiGe NWs under different VG. The Seebeck coefficient increases in the beginning and then slightly decreases which leaves a peak at 400K with the maximum value of 2522 µV/K for VG=0. The electrical conductivity is increased but with slower slope than the Seebeck coefficient plot.

Figure 52 a) conductivity b) Seebeck coefficient of SiGe NWs versus temperature (paper VI)

Similarly, as it is shown in Figure 53a the power factor followed the increasing trend with temperature due to both increase in Seebeck coefficient and electrical conductivity. The power factor in the SiGe NWs in this study is considerably higher values in comparison to the earlier reports[32]. For example at T=450K, the value showed at least two-fold enhancement compared to our best value calculated for bulk SiGe at similar temperature with the optimal dopant concentration of 1019 cm-3. In order to estimate ZT using such a high power factor, a thermal conductivity value of 1.2 W/m.K was extracted from a previous report[32] on SiGe NWs with similar composition and diameter. The ZT of SiGe NWs was plotted using this value in Figure 53b, which shows the ZT can exceed 1 at 450 K.

45

Figure 53 a) Power factor analysis b) ZT with thermal conductivity from ref. [32] for SiGe NWs (paper VI)

In final, all these results can be correlated separately or together to explain the high TEP values in this study. Simply, any change in shape and composition and defect density of NWs will create energy barrier within the bandgap which can affect TEP of material.

46

Chapter 5

5.1 Conclusions

Using chemical vapor deposition technique, two alloys from group IV have been successfully developed as potential TE materials.

It was demonstrated high quality compressively strained and relaxed GeSn alloy with different Sn contents up to 15%. The compressive GeSn layers realized by growing a high quality Ge buffer on Si substrate in two different steps: an initial layer grown at low temperature (400 ᵒC) which is highly defected and a cap layer grown at high temperature epitaxy (680 ᵒC) with high epitaxial quality. The AFM analysis proved that Ge buffer has high smooth surface (<1nm), which can serve as buffer layer for growing high quality GeSn layer. The GeSn layer was grown at 270-400 ᵒC when the segregation of Sn was controlled mainly by Ge partial pressure for any specific Sn partial pressure.

The incorporation of Si in GeSn alloy resulted in the higher incorporation of Sn in GeSn layer. This was explained with the smaller atomic size of Si, which can compensate strain in GeSn alloy. The Ni-GeSn was formed on strained and un-strained GeSn to realize ohmic contacts to NWs. The result shows the reaction was eased in the presence of no strain in GeSn layers. The thermal stability of Ni-GeSn phase is sensitive to temperature up to 500 ᵒC and Sn will diffuse-out slightly from the film at a higher temperatures.

Si0.53Ge0.47 on insulator (SGOI) was formed by condensation of an epi-Si0.74Ge0.26 layer on SOI wafer. SiGe NWs have been successfully fabricated using STL or by conventional I-line lithography followed by FIB technique to cut the NWs to smaller size. The power factor of NWs fabricated by FIB increased as the width of NWs shrunk, due to maintaining high electrical conductivity of NWs despite a dramatic decrease in Seebeck coefficient. The conductivity behavior of NWs was monitored by implanted Ga ions from the sides during FIB cutting. However, NWs fabricated by STL showed promising TE properties. The value of power factor for n-type SiGe NWs reached to 1000 µW/m.K2 due to high Seebeck values which were higher than p-types ones in the temperature range of 280 to 380 K. The high Seebeck coefficient values are associated with the presence of defects created during condensation process and STL fabrication, which can act as potential barriers. The back gate biasing was applied on p-type SiGe NWs to further improve the conductivity which resulted to an order of magnitude enhancement of electrical conductivity while has a modest influence on the reduction of Seebeck coefficient. This excellent behavior leads to the power factor of 3500 µW/m.K2 at 450 K which with the expectation of low thermal conductivity in 60 nm SiGe NWs, results in a ZT of than 1 for p-type SiGe NWs. Finally, the results in this work demonstrate that group IV materials provide an outstanding platform which is cost effective and environment friendly for thermoelectric mass production in near future.

47

5.2 Future work

To measure accurately the thermal distribution along NWs is a tedious task. There is a special interest to measure the thermal conductivity of NWs in order to calculate the ZT. Hence, new methods have to be developed to tackle this task. The novel alloys of GeSn(Si) have been applied for photonic applications however these materials should demonstrate high performance TE properties as well. An obstacle to measure TE properties of NWs of GeSn(Si) alloys is to develop GeSn(Si) on insulator wafers. A more experimental work should be done on wafer bonding manufacture GeSn(Si) on insulator wafers specially high temperature annealing should be omitted to avoid Sn out diffusion and precipitation. Finally, the results presented in this thesis should be used to manufacture a TE generator for industrial application in near future.

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