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Accuracy Management for Delay-oriented Control of Digital VLSI Simulation. Basic overview of Ph.D. thesis work at Columbia University under Professor Charles Zukowski.
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DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversity
Accuracy Management forMixed-Mode Digital VLSI Simulation
Gary L. Dare* & Charles A. Zukowski
Department of Electrical Engineering
Columbia University
New York, New York 10027-6699
* DigitalDNA Systems Architecture Lab
Motorola Labs
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityState of the Art/Motivation
VLSI DesignHigher levels of circuit integrationLarger scale systems
System-on-Chip
High Performance Applications computing, telecommunications
VLSI SimulationImprove cycle time – reduce/eliminate prototyping.Electrical simulation (SPICE) - accurate, costlyApproximate methods - efficient, limited feasibilitySwitch-level simulation - fast but simple; too little info
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityState of the Art/Motivation II
Mixed-Mode Digital VLSI SimulationCombines higher & lower accuracy analysis
Manual selection of accuracy (usually 2) Problems involve large # subcircuits
Waveform RelaxationPartitioned simulation of subcircuitsIterative refinementCompatible with Mixed-Mode Simulation
Solution RequirementsAutomate assignment of simulation accuracy
Higher accuracy on critical pathsLower accuracy off
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityProblems Addressed
Simulation AccuracyProvide guaranteed accuracy in timing simulation of
digital VLSI.
Computational EfficiencyDetermine efficient means of analyzing different parts of
circuit.Highest accuracy throughout not necessary.
Handling large circuitsData management for assigning accuracy to large
numbers of subcircuits.
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityUncertainty on Critical Paths
Critical path (B, C) determines delay at OutputFor 20% accuracy in simulated output signal delay
Simulate all at 20%, or …Simulate differently in mixed mode (A @ 40%)
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityUncertainty Redistribution
Computation increases with accuracyUncertainty xi decreases
Computation increases with “complexity”e.g., size, bi
Delay uncertainty on signal path constrained by output specification, e.
Required accuracy for block N on a signal path:xn = e sqrt(bn / dn) / sqrt(bi di)
10 20 15
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityApplication of Heuristics
UtilizationIterative simulation
Start with “rough”, low accuracy analysis Refine with heuristics Update simulation (iterative process) – until convergence
Refinement process: Apply heuristic to end block; calculate accuracy Redistribute remaining uncertainty among preceding blocks
Recursive levelized traversal of circuit: Output-to-input (post-simulation iteration) Level-by-level
Accuracy Management
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityMixed-Mode Testbed
A mixed-mode relaxation simulation frameworkInput, scheduling, waveform data managementV.1 “Algorithmic” – modeled AM behavior
“virtual” simulators
V.2 Ported some existing simulators Electrical – GSOLVER [Gristede] Piece-wise Approximate – SPECS [Visweswariah] Switch-level RC Delay – DIY [do-it-yourself]
Testbed shell: Accuracy Mgt & Scheduling
Sim 1 Sim 2 Sim 3
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityPredicted Simulation Costs
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversitySimulated Benchmarks
DigitalDNA Systems Architecture Laboratory
Great Lakes Symposium on VLSI 2000
ColumbiaUniversityConclusions, Future Research
ConclusionsAutomated the management of mixed-mode timing
simulation.Efficient heuristics & analysis to determine required
accuracy.Yield efficient computation for large # subcircuits
Future ResearchImplement in actual EDA frameworkComplement with analog for mixed-signal analysisMIMD parallel processing (e.g., virtual time)Other optimization bases?Re-simulation approaches – localized updates?
