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Glass Packaging R&Dfor 2.5D, RF, 5G, Photonics, Autonomous
Sensors and Power
Slide 1 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Georgia Tech Glass Packaging R&D� Pioneered Glass as a Package Platform in 2009� Enabled Supply chain commercialization� Pervasive Applications
Memory Logic
Glass 30 - 100μm
RF
Silicon like RDL on large panels
Ultra-Thin 30-100um
2-4x lower Die Shift & Warpage
4-8x Lower Cost from Large Panels
I/O Scaling to < 20-40um Pitch
Low InductanceAll Cu Interconnect
TPVs at <50um Pitch &>10K/sec
Design for AutomotiveReliability @ Board Level
2.5D Interposer RF LTE, WLAN
Signal/Power Design for DC – 100 GHz
3D Photonics Integrated RADAR & Camera 5G High Power
RFHigh Temp
Chip Last (2.5D, 3D) Chip First (GFO)
Slide 2 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Automotive Sensors - Camera
Applications Development of Glass Packaging in GT Industry Consortium
C&C - 5G, Glass Fanout C&C - 3D Glass Photonics
C&C – RF LTE & WLAN C&C - Low Power
PassivesPassives
Active IC Active IC
30 mm
10 mm
50 mm
C&C - 2.5D Interposer Package
Automotive Sensors - RADAR High Power – RF GaN
AutomotiveSensor Package
Slide 3
CONFIDENTIAL
IEEE-CPMT Workshop – Glass Packaging and 2.5D
Industry Partnerships in Glass PkgCompany Contribution Industry partners
End-UsersAMD Design Guidance Michael Su, Bryan BlackIntel Design Guidance Bob Sankman, Rahul Manepalli
Tools
Atotech Metallization Processes Robin Taylor, Several Business UnitsDisco Planarization, Dicing Cody Lee, Y. Chen, Frank WeiESI UV Laser vias Lamar McDonaldK&S High Speed TCB Horst Clauberg, Bob ChylakMKS Ozone Cleaning Atul Gupta, C. Gottshalk, Kevin Wenzel, Eric SnyderRudolph Litho Tool Rich RogoffSavansys Cost Modeling Amy Palesko LujanSuss Excimer Laser Patterning Habib HichriUshio Litho Tool S. Yabu
GlassSchott 50 microns glass, TPV Martin Letz, Matthias JotzAsahi 50 microns glass, TPV Tomonori Ogawa, Yoichiro SatoCorning Glass, TPV Aric Shorey, Ravi Katare, Jin Kim
Polymers
Ajinomoto Ultra-Thin ABF Ryo MiyamotoJSR Micro Dry Film Polymers H. Itou, K. HasegawaTOK Photosensitive Dry Films Atsushi Kubo, K. AndoPanasonic Low Stress Films M. Matsumoto, T. HasegawaHitachi Chemical Dry Film Resist M. Ose
SubstrateShinko Glass Substrates M. Tanaka, N. Koizumi, A. TakanoNGK-NTK Glass substrates Hiroyuki Matsuura, Takuya ToriiUnimicron Glass Substrates Y H Chen, C H Chien
Assembly Atotech UBM, Plating Gustavo RamosASE Wafer bumping, test chips Teck Lee, Mark Gerber, Rich RiceNamics Underfill and NCP S. KawomotoGlobal Foundries Test Chips Luke EnglandPacTech Assembly on Glass T. Teutsch, M. Sarkar, Jing LiWalts Test Chips, Substrates Makiko Nozaki
Slide 4 IEEE-CPMT Workshop – Glass Packaging and 2.5D
BASE TECHNOLOGY HIGHLIGHTSGLASS SUBSTRATES
Slide 5 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Progress in TPV Pitch & Cost
Year2010 2012 2014 2016
TPV Pitch
250um
150um
100um
50um<100 vias/s
Throughput1000 vias/s
5000 vias/s
10000 vias/s
Slide 6 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Silicon-Like RDL for the 1st Time on Panels
Glass – 140um
IF4605
Photo TrenchLaser Trench
Top view Cross section view
• Dry Film Polymers• Excimer Laser Or Photo Patterning• Fill Plating• Fly Cut Planarization• Via-in-Line (VIL) Structures
YUYA SUZUKI, HABIB HICHRI (SUSS)CODY LEE, Y. CHEN (DISCO)
ATSUSHI KUBO (TOK), CHANDRA NAIR, FUHAN LIUCODY LEE, Y. CHEN (DISCO)
1st Demo using Etching (May 16)
Optimized using Disco Planarization
IEEE-CPMT Workshop – Glass Packaging and 2.5D
HIGH-PERFORMANCE INTERCONNECTIONSUNIQUE GT APPROACHES BEYOND PRIOR ART
7
Cu pillar scaling
Innovations in materials, tools & processes for improved pitch scalability, performance & reliability: • Ni-free surface finish • Pre-applied underfills• High-speed bonding• Warpage mitigation
Metastable SLID
• Die-to-package at 20µm pitch • Void-free interface• <1min transition time• Power handling >105A/cm2
• Thermal stability >250°C• Superior shear strength &
reliability
All-Cu interconnections
Engineered nanoscale bonding interfaces for:• Pitch scalability to < 20µm• Manufacturable assembly at
T < 250°C & P < 40MPa• 3µm tolerance to non-
coplanarities & warpage
~35µm
High-density 2.5D glass interposer
Si die
~15µmCu pillar with nanocopper cap
Cu pillar with ultra-thin metallic finish
Enhanced pitch scalability, power handling capability and high-temperature stability
IEEE-CPMT Workshop – Glass Packaging and 2.5D
ADVANCES IN MATERIALS, TOOLS & PROCESSES FORCu PILLAR SCALING
8
TCB Process Modeling Thermal contact interface modeling
High-speed TC-NCP Process
Day 2: shot 528C-SAM analysis: no voiding
Evaluation of dispense stability 1st glass strip assembly with TC-NCP (K&S tool & Namics underfill)
TC-NCP at 50um pitch
Warpage mitigation in assembly: optimized thermal
profile for min warpage
EPAG Finish Evaluation
Die-to-NCP NCP-to-substrate
Wettability
Cu pillar scalable to 20um pitch using EPAG finish: reliable with
<10um solder height
Shear testHigh-temperature storage Thermal shock on FR-4
Advanced materials and tools for assembly on ultra-thin glass
IEEE-CPMT Workshop – Glass Packaging and 2.5D
RESEARCH HIGHLIGHTSHIGH-PERFORMANCE SOLDER-BASED INTERCONNECTIONS
• PRC’s roadmap to scaling of Cu pillars (2014 – now)
9
>35µm pitch / 25-35µm heightEM at <104A/cm2 – Top <100°C
Current Cu pillar
Metastable SLID
50µm pitch / 12µm heightEM at 105A/cm2
HTS at 200oCReliable on glass pkg
20µm pitch / 10µm height
Metastable SLID
Cu pillar / EPAG
100µm pitch / 17µm height
20mm?
Cu pillar / EPAG
50µm pitch / 32µm height<10mm solder height
• First demonstration of metastable CuSn SLID at 20um I/O pitch
IEEE-CPMT Workshop – Glass Packaging and 2.5D
RESEARCH HIGHLIGHTSMANUFACTURABLE C2S ALL-Cu INTERCONNECTIONS
10
IEEE-CPMT Workshop – Glass Packaging and 2.5D
RESEARCH HIGHLIGHTSBOARD-LEVEL RELIABILITY OF GLASS BGA PACKAGES
11
No collar With polymer collars
Board-level reliability of glass BGA packages
Polymer collars (Courtesy of Namics)
• Partial underfills • Doped solder alloys
Warpage measurements
Drop test (Courtesy of Qualcomm)
Thermal cycling test
Compliant interconnectionsLow-cost Cu microwire array
(MWA) fabrication
Cross-section of MWA interconnection
Low-cost manufacturable
processes
Warpage mitigation • In fabrication • In assembly
Assembly yield & system-level
reliabilityHigh-CTE glass: >5500 cy.
30% improvements in drop & TCT with polymer collars
IEEE-CPMT Workshop – Glass Packaging and 2.5D
BALANCED DESIGN FOR CHIP & BOARD LEVEL
CTE
Chip- and- board-level assembly
Chip-level Nf Board-level Nf
Coffin-Manson
Coffin-Manson
Engelmaier-Wild
3.3 6702 850 1267
5 5962 1045 1624
6 5083 1164 1848
8.3 4738 1450 2403
9.8 3063 1644 2794
0
1000
2000
3000
4000
5000
6000
7000
8000
3 5 7 9 11
Pred
icte
d Fa
tigue
Life
(no.
of
cycl
es)
Substrate CTE (ppm/K)Chip-level Board-level_Coffin-Manson
0
50
100
150
200
250
300
2 4 6 8 10 12
RT W
arpa
ge (µ
m)
Substrate CTE (ppm/K)
RT warpage after chip-level reflow assembly
160µmMaximum permissible warpage w/o open joints
Model Predicted Warpage
Example plastic strain in solder joint at chip-level (top) and board-
level BGA (bottom)
Example warpage at room temperature after chip-level assembly and BGA balling
Fatigue life at chip and board levels
• Warpage mitigation through optimization of TCB thermal profiles critical for board-level assembly yield
Slide 13 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Glass
Glass Test Chip
Cu BumpRDL
50 µm
70 µm 75 µm213.8 µm
Power of Co-Development PartnershipGlass Fanout: From Idea to 1st Prototype in 1 Year
� Die Shift across 150mm x 150mm area <5um (compared to 15-25um die shift across 50mm x 50mm area for FO-WLP)
• Already in Panels• No Grind/Polish• I/O Pitch Scalable• Ultra-Low Loss
Polymer
20um Cu Interconnect @ 65um Pitch
Slide 14 IEEE-CPMT Workshop – Glass Packaging and 2.5D
APPLICATION DEMONSTRATORS
Dr. Venky Sundaram, GT-PRC15 | IEEE-CPMT Workshop – Glass Packaging and 2.5D
FIRST Process of Record (POR) for Glass Interposer by GT PRC & Partners in 2013
100-150um Thin Glass
Slide 16 IEEE-CPMT Workshop – Glass Packaging and 2.5D
Georgia Tech Approach: 2.5D Glass Interposer Package vs. Si & Organic Interposer
Glass Interposer PackageIC
PWB
Glass CoreFine RDL
BETTER SI/PI, COST, RELIABILITY, THIN• Close to BW of Silicon interposer• Shortest Power Path from PWB• High speed channels on interposer• Embedded LC in glass (future)• Scalable to Large Panels
Challenges• High cost• Additional interfacesImpact Power Delivery• Thickness• Requires Org. Pkgfor board-level reliability
Challenges• Signal BW & I/Os
• Thickness & warpage
AddressChallenges
Dr. Venky Sundaram, GT-PRC17 | IEEE-CPMT Workshop – Glass Packaging and 2.5D
1st Demonstration of Fully Integrated 2.5D Glass Interposer in May 2016
� Partnership with 15+ supply chain companies and several end users
100 um
150um 40 um
130 um
Dr. Venky Sundaram, GT-PRC18 | IEEE-CPMT Workshop – Glass Packaging and 2.5D
Cross-section of Assembled RF Module on GlassIntegration of MEMS Filters
First 3D LTE Glass BGA Module Demonstration with TDK-Epcos
Switch High-band Filter
130 um Corning Glass
Solder dispensed for board-level assembly with LGA
Fabricated 6’’ x 6’’ 4ML Glass Substrate & Modules Assembled at Board Level
Corning Glass
High-band Filter
IEEE-CPMT Workshop – Glass Packaging and 2.5DSlide 19
Double-side LTE Module with TDK-Epcos
TV1: Double-side full-chain module with BGA for 3D assembly
LBF on the bottom
Switch and HBF on the top
Top Bottom
First demonstration of 3D RF module using BGA ball drop
IEEE-CPMT Workshop – Glass Packaging and 2.5DSlide 20
First Demonstration of 400GB 3D Glass Photonic Module
PIC DriverSMF
Driver
Amplifier
Rx
Tx
PIC
2 3
1Glass
Waveguide
Copper
IC
Underfill
PCB
Solder
Passivation
4
1. Optical Waveguides / Vias2. Out-of-Plane Turning3. Fiber Coupling4. Design and Demonstration
100 mm
100 mm
16 m
m
16 mm