Glass Interposer Substrates: Fabrication, Characterization ... Global Summot 3DIC... · Glass Interposer Substrates: Fabrication, Characterization and Modeling Aric B. Shorey, PhD

Glass Interposer Substrates: Fabrication,

Characterization and Modeling

Aric B. Shorey, PhD

Manager of Commercial Technology

Semiconductor Glass Wafers/Corning, Incorporated

5 September 2013

© 2013 Corning Incorporated

Outline

• Glass Substrates

• Strength

• Via Process

• Cu Filling and RDL Process

• Glass and Si Interposer Test Vehicle

Performance

• Summary


What is Needed for 3D-IC?

High Quality Substrates

• A substrate that can support a silicon

device wafer during the thinning and

stacking process as a carrier

• A substrate that can be used in

interposer applications

High Value Attributes

• Smooth & clean surface

• Low TTV

• Low warp / bow

• Strength & reliability

• CTE matching Si

• Good chemical durability

• Good electrical properties


Corning’s Strategic Intent in Semiconductor Glass

Advanced Optical Melting Fusion

Sheet Forming Process

Optimized

Expansion

Pristine Surface

Profoundly

Flat

Thin & Strong

Innovative Aluminosilicate

Glass Compositions


Corning® Willow™ Glass: Ultra-slim Flexible Substrates

• Ultra-slim flexible glass from the fusion

process makes an ideal substrate for TGV

– Pristine surface with low TTV

– Opportunity to provide materials that do not

require post-form finishing

– Glass is not susceptible to dislocations


Potential Methods for Creating TGV

• Product Requirements:

– Hole dimensions

– Hole quality (cracks)

– Substrate size

– Scaling

– Cost

Through or Blind Via

Wet Etching & DRIE

Photo-Sensitive

Glass

Mechanical Drilling

Laser Ablation

Electrical Discharge


Corning’s Process: Current Capabilities

• Through and blind holes

• Glass size

– Wafers 100mm → 300mm wafers

– Panels up to 500mm

• Thickness

– 100µm→700µm


Via Dimensions

Diameter > 20mm | Thickness > 100mm

20mm diameter 100mm diameter

Side B

Side A

100mm thick

60mm vias

100mm pitch

300mm thick

50mm vias

100mm pitch

700mm thick

25mm vias

100mm pitch


Varying Pitch and Pattern

15mm diameter

50mm pitch

30mm diameter

100mm pitch

30mm diameter

400mm pitch

Pitch down to 50 mm

Square Array

~ 6 holes/mm2 Square Array

~ 100 holes/mm2

HCP Array

~140 holes/mm2

Densities : <1 hole/mm2 >250 holes / mm2


Vias in High Quality Glass Substrates Full Characterization of

Hole Diameter, Circularity

Capabilities up to 300 mm wafers and panels up to 0.5M

30 µm Diameter Blind

Holes

Fully Patterned Wafers

With

100,000s of holes

Blind Via Diameter ~ 27 µm

2,500 holes 11,716 holes

Not just making holes in glass – fully patterned wafers/panels

with 100% inspection


Strength Performance

10010

95

80

50

20

5

2

1

Kgf

Pe

rce

nt

With Holes - A

With Holes - B

P lain Glass

V ariable

Weibull

0.923, 0.957, 0.956

C orrelation C oefficient

Glass Strength With and Without Holes

Weibull


Typical Breakage of a Via Sample

Break Origin

Picture of ROR broken glass sample with 5x5 via array.

Note that breakage did not originate at via array.


Filled Vias

• Demonstrated ability to fill vias with good adhesion properties (ITRI).

– Vias passed hatch test demonstrating good adhesion

• Development of additional downstream processes in progress

– Redistribution Layers (RDL)

– Thinning/finishing blind vias

Cu filling performance with TGV substrate based on

Corning fusion glass

(top diameter ~ 30 µm, total depth ~ 180 µm)


Glass and Silicon Interposer Test Vehicles

• Glass and Si test vehicles fabricated by Industrial Technology

Research Institute (ITRI) using Corning glass interposer

substrates.

Source: Industrial Technology Research Institute (ITRI)


Insertion Loss Measurement Comparison

• Si resulted in much insertion loss compared to glass based on surface (line) measurement.

• Signal lost ~50% if S21 = -3dB.

Microstrip Line CPW


Measurement of TSV and TGV combining microstrip line (L=570um)

Condition (line + via) Measurement

• Si resulted in much insertion loss compared to glass (based on line+via measurement)

• Signal lost ~50% if S21 = -3dB.


Corning Active Participation LGIP Program at Georgia Tech PRC

• Work will demonstrate:

– Decreased hole size and substrate thickness

– Ability to process/handle thin glass substrates (<100 µm)

– Performance/Reliability of glass interposers with different CTE

• Electrical and mechanical characterization


Model-to-Measurement Correlation

0 1 2 3 4 5 6 7 8 9 10

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

Frequency (GHz)

Insert

ion L

oss |S

21| (d

B)

2 Via Transition

Simulated

4 Via Transition

Simulated

6 Via Transition

Simulated

0 1 2 3 4 5 6 7 8 9 10

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

Frequency (GHz)

Insert

ion L

oss |S

21| (d

B)

2 Via Transition

Simulated

4 Via Transition

Simulated

6 Via Transition

Simulated

0 1 2 3 4 5 6 7 8 9 10

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

Frequency (GHz)In

sert

ion L

oss |S

21| (d

B)

2 Via Transition

Simulated

4 Via Transition

Simulated

6 Via Transition

Simulated

CPW Line

CPW Line

Glass TP

V

TP

V

CPW Line

Glass Glass

Glass Glass Glass 0 1 2 3 4 5 6 7 8 9 10

-0.5

-0.45

-0.4

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

Frequency (GHz)

Insert

ion L

oss |S

21| (d

B)

2 Via Transition

Simulated

4 Via Transition

Simulated

6 Via Transition

Simulated


Finite Element analysis on package warp

Material

Elastic Modulus

(MPa)

Poisson Ratio

CTE (ppm/C)

Silicon See Table 2 below NA 2.6

Interposer (Glass

A, B)

73600 (A), 71700

(B) 0.23 (A), 0.21 (B) 3.17 (A), 8.35 (B)

Substrate

x,z = 29647-

39.438T

y = 12962-17.168T

xy,zy = 0.39,

xz=0.11

16 (in-plane), 84

(out-of-plane)

Microbump and

Underfill Effective

Properties

20705 0.3 40

C4 joints and

Underfill Effective

Properties

8517.8 0.35 25

Constant C11=C22 C12 C13 C33 C44 C55 C66

Value [GPa] 194.5 35.7 64.1 165.7 79.6 79.6 50.9


FEA Results indicate the ability to adjust CTE important lever for reliability

• Example of the warpage from the

package

• Effect of interposer thickness and

CTE on warpage

0 100 200 300 400 500200

220

240

260

280

300

320

340

360

Warp

age (

Mic

rons)

Interposer Thickness (Microns)

Silicon Interposer

Glass with CTE of 3.17 ppm/C

Glass with CTE of 8.35 ppm/C


Substantial opportunities for glass interposers readiness

• Electrical properties provide substantial

opportunity in many applications (particularly RF)

10010

95

80

50

20

5

2

1

Kgf

Pe

rce

nt

With Holes - A

With Holes - B

P lain Glass

V ariable

Weibull

0.923, 0.957, 0.956

C orrelation C oefficient

Glass Strength With and Without Holes

Weibull

• Ability to manufacture glass interposers with

excellent performance demonstrated

• Ability to adjust properties such as CTE can have

significant impact in device reliability

• Substantial opportunities to leverage the ability to

form 1) at thickness and 2) in different form factors

(wafer/panel) can substantially impact cost


Conclusion

• Glass is a versatile and robust material with a long track record &

strong potential as an enabling material in electronics.

• The key attributes to be delivered are in the areas of flatness,

surface quality, thermal behavior, electrical behavior, thinness, and

strength.

• There is opportunity to adjust glass composition to tailor

properties.

• We can make high quality through and blind vias in a variety of

glass compositions. Via diameters down to 20 µm diameter have

been achieved, with glass thickness of 100µm → 700µm.

• Filled vias with good adhesion.

• Thermal, mechanical, electrical and overall process (cost)

performance continue to be demonstrated

Documents

Glass Interposer Substrates: Fabrication, Characterization ... Global Summot 3DIC... · Glass Interposer Substrates: Fabrication, Characterization and Modeling Aric B. Shorey, PhD