GigE Vision High-Speed Image Processing on FPGAs ... - DESY · Deutsches Elektronen-Synchrotron DESY A Research Centre of the Helmholtz Association Notkestr. 85, 22607 Hamburg, Germany

GigE Vision High-Speed Image Processing

on FPGAs for Science and Industry

Sven Stubbe and Jan Marjanovic

Jena, 06.03.2019

p. 2

GigE Vision High-Speed Image Processing on FPGAs for Science and Industry

Sven Stubbe, 06.03.2019

AGENDA

1. “The Story Behind“

2. About Standards

3. Technical System Concept

4. Details on Implementation

5. Image Processing Solutions

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Sven Stubbe, 06.03.2019 The Story Behind

The MicroTCA Technology Lab at DESY

Our Mission

• Transfer MicroTCA Technology to industry and research

• Support the community behind MicroTCA for enabling

space on innovative ideas and new business models

Starting Point

• Started hiring from Oct. 2016 → Official opening April 2018

• Funded by Helmholtz Innovation Lab (5 Mio EUR over 5

years) → Self-sustainability is a key goal

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→ Chemical Crystallography

→ Visual Inspection

GigE Vision Camera Interfacing

and Image Processing

→ Target Protection System

→ University of Oslo

→ Industrial visual inspection

→ Synchronous systems

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Sven Stubbe, 06.03.2019 Why to use MTCA Standard?

• High reliability

• Integrate into existing control system

• Outsource image processing to FPGA

• High flexibility and high performance

• Several hardware platforms

• High count of cameras possible

• Several chassis available

• Synchronization between systems

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Sven Stubbe, 06.03.2019 Why to use GigE Vision Standard?

• Simple cabling (up to 100 m, PoE)

• Use of Ethernet infrastructure

• High data rates

• High degree of standardization

• GenICam standard compliant

• ROI definition is possible

• Device precision time protocol

(IEEE1588)

Region of interest definition

Camera synchronization via PTP

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Sven Stubbe, 06.03.2019 Technical System Concept

Target Product: DIPC-7050 GigE Vision Stack

Software

• Controlling and application

• Modular and scalable

• Runs as a command server

• Can be reached from user as well as

from optional application

• Written in C++

FPGA Firmware

• Camera interfacing

• Modular and scalable

• IP-Cores for Vivado Design Suite

• AXI4 / AXI-Stream compliancy

• Support for Xilinx 7Series, Ultrascale,

Ultrascale+, SoC and MPSoC

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Sven Stubbe, 06.03.2019 Technical System Concept

FPGA Firmware

GigE Vision IP core

Controller SoftwareDIPC-1050UDP/IPv4

Engine

AXI Lite interfaceCamera Comm

StreamProcessing

XilinxDDR3/4

controller

Centroid mean & std calculation

XilinxVideo DMA

XilinxPCIe

interface

bro

adca

st

Demo Application(in Python)

TCP socket

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Sven Stubbe, 06.03.2019 Details on Implementation

to memory interface and ext. DDR3

(AXI Video Stream)

to PCIe transceiver

DMA to external

Memory

DMA for

PCIe

to network interface

• Software Interface (e.g. PCIe)

• Send/Receive GVCP packets

• Receive GVSP packets

• Parse to AXI Video Stream

FPGA Firmware

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Primitive Type Count

FLOP_LATCH 2307

LUT 1999

CARRY 286

BMEM 12

Resolution Frame Size Framerate FPGA

1920 x 1080 px 16.59 Mbit 50 fps

Performance GigE Vision Implementation

GigE Vision IP-Core

UDP IP-Core

AXI Video DMA

1GB Ethernet PMA

FPGA Firmware Resources

DIPC-7050 GigE Vision Stack (Xilinx Kintex7, XC7K420tffg901-2)

UDP IP-Core

Primitive Type Count

FLOP_LATCH 1311

LUT 1863

CARRY 233

BMEM 10

GigE Vision IP-Core

Tested with JAI-GO-2400-PGE

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Controller Software

User

/ A

pplic

ation

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1. Start server from host side

2. Telnet into server

(TCP/IP socket connection)

3. Run commands

(from command line or application code)

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Sven Stubbe, 06.03.2019 Image Processing Solutions

• Application code is written in C++

• Low latency

(dimension dependent)

• Convenient debugging and

analyzation tools

Synthesis

RTL export

Vivado High Level Synthesis

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Silicon Software Visual Applets

• Very short development time

• No FPGA knowledge needed

• convenient debugging

DIPC-7050

GigE Vision Stack Algorithm

Netlist

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DAMC-FMC2ZUP

• Xilinx Ultrascale+

MPSoC

• ARM Mali GPU

DFMC-SFP4

• 4x SFP/SFP+

from xilinx.com

Image Data

Processing

Controller Software

GigE Vision

IP-Core and logic

infrastructure

• Hardware and software

on single chip

• Standalone solution

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Sven Stubbe, 06.03.2019 Conclusion

Product:

• DIPC-7050 GigE Vision Stack

• Hardware dependent GigE Vision

camera support

• User friendly interface

Image processing solutions:

• Several concepts available

• Have their own advantages

• Demos available

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Sven Stubbe, 06.03.2019 Thank you!

Deutsches Elektronen-Synchrotron DESY

A Research Centre of the Helmholtz Association

Notkestr. 85, 22607 Hamburg, Germany

phone: +49 (0) 40 8998 1818

Web: [email protected]

MTCA Trainings

• Basic Course: 03th – 04th September 2019

• Advanced Course: 10th – 11th October 2019

MTCA Workshop

• 4th – 5th December 2019

• Pre-Workshop: 3rd December 2019

• Registration opens in September

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GigE Vision High-Speed Image Processing on FPGAs ... - DESY · Deutsches Elektronen-Synchrotron DESY A Research Centre of the Helmholtz Association Notkestr. 85, 22607 Hamburg, Germany