Gigabit Ethernet/PCI Network Interface Card Host/NIC ...wpaul/Alteon/pcinic.pdf · July 1999 Alteon WebSystems, Inc. 50 Great Oaks Blvd. San Jose, CA 95119 1-408-360-5500 Gigabit

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© 1996, 1997, 1998 by Alteon Networks, Inc. All rights reserved.

This document contains proprietary and confidential information of Alteon Networks, Inc. Thecontents of this document may not be disclosed to third parties, copied, or duplicated in any forwhole or in part, without the prior written permission of Alteon Networks, Inc.

Restricted Rights LegendUse, duplication, or disclosure of the technical data contained in this document by the Governis subject to restrictions as set forth in subdivision ©(1)(ii) of the Rights in Technical Data andComputer Software clause in DFARS 52.227-7013 and/or in similar or successor clauses in thFAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the CopyriLaws of the United States. Contractor/manufacturer is Alteon Networks, Inc. 50 Great Oaks BSan Jose, CA 95119.

Revision HistoryRev 01 6/3/96 Initial Alteon Networks version.

Rev 02 6/5/96 Added statistics, completely described commands and events, fixed many figur

Rev 03 6/10/96 Major re-write, added flow diagrams, added CONFIDENTIAL markings, lots ochanged based on feedback from Wayne and Ted, removed EEPROM layout.

Rev 04 6/19/96 Minor re-organization, removed FRAME_SENT and FRAME_RECEIVED eve

Rev 05 7/5/96 Updated data structures, statistics, removed START_FIRMWARE command, revbibliography

Rev 06 9/26/96 Converted to framemaker, updated statistics and shared data structures, editochanges.

Rev 07 11/8/96 Added SET_HOST_STATE command, rewrote initialization section, cleanupfigures, update and expand command and event descriptions, Remove GET_STATS commanupdate for address changes related to RR->TIGON ASIC change, general editorial changes.

Rev 08 1/9/97 Defined all undefined values.

Rev 09 6/1/97 Changed format to comply with Alteon documentation standards, removedGET_RCB_FLAGS and SET_RCB_FLAGS commands, updated flow diagrams to current desadded section on performance tuning, general editorial changes.

Rev 10 9/1/97 Update document to Revision 1.1 specifications

Rev 10.1 9/17/97 Fix documentation bugs, particularly field definition errors in several of the dstructure. Add new section on Serial EEPROM and new fields in the buffer descriptor.

Rev 10.2 10/21/97 Add documentation for new features, correct English and descriptions

Rev 11.0 11/19/97 Update document to Revision 2.1 specifications

Rev 11.1 12/15/97 Add documentation for checksum offload support

Rev 11.2 1/9/98 Documentation corrections and clarifications

Rev 11.3 2/123/98 Documentation corrections and clarifications. Tigon 2 checksum offload sup

Rev 12.0 4/15/98 Reorganized the shared memory areas. New VLAN assist functionality. Updaclock tick handling. Internal loopback available. Special monitoring capability.

Rev 12.0.1 - 12.0.5 5/19/98 - 6/23/98 Minor clarifications

Rev 12.0.6 6/26/98 Add DMA Errata for Tigon 2

Rev 12.1 - 7/29/98 Add BD Coal Now bit, RCB Coal update only bit.

Rev 12.1.1 - 8/4/98 Add SBUS bit to mode_status word

Rev 12.2 - 8/19/98 Add Host based Send Ring

Rev 12.2.1 - 8/24/98 Add mailbox receive ring replenish, extended multicast commands, new control bits, eliminate receive return consumer index.

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Rev 12.3 - 9/23/98 Add mini receive ring, extended receive buffer descriptors, transmit buffer and 802.3 checksum offload support documentation

Rev 12.3.3 - 1/15/99 Allow sizing of Receive Return Ring

Rev 12.3.9 - Better numbering scheme and fixed description of tcp_udp_cksum field in receivbuffer descriptor

Rev 12.3.11 - Indicate Min DMA field must be zero due to hardware bug.

Rev 12.4.0 - Add API for 1000BaseT card. Change company name. Long overdue spell check

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1 Introduction1.1 TIGON...................................................................................................................... 131.2 Feature Set ................................................................................................................ 131.3 Foundation Data Structures ...................................................................................... 1

1.3.1 Host Addresses..................................................................................................... 11.3.2 NIC Addresses ..................................................................................................... 11.3.3 MAC Addresses ................................................................................................... 11.3.4 Endianness............................................................................................................ 1

1.4 LED Meanings.......................................................................................................... 1

2 Architecture2.1 Memory Model ......................................................................................................... 17

2.1.1 Shared Configuration Block................................................................................. 172.1.1.1 PCI Configuration Region........................................................................... 18

2.1.1.1.1 PCI Configuration Region Setup for SBus Cards................................... 182.1.1.2 Tigon Configuration/Control Region .......................................................... 19

2.1.1.2.1 Tigon Miscellaneous Host Control Register ........................................... 202.1.1.2.2 Tigon Miscellaneous Local Control Register ......................................... 202.1.1.2.3 Tigon Miscellaneous Configuration Register ......................................... 212.1.1.2.4 Tigon PCI State Register......................................................................... 22.1.1.2.5 Tigon Window Base Address Register ................................................... 222.1.1.2.6 Tigon Window Data Register ................................................................. 232.1.1.2.7 Tigon DMA Assist State Register........................................................... 232.1.1.2.8 Tigon CPU State Register ....................................................................... 22.1.1.2.9 Tigon CPU Program Counter Register ................................................... 242.1.1.2.10 Tigon Internal SRAM Address Register ................................................. 242.1.1.2.11 Tigon Internal SRAM Data Register ...................................................... 242.1.1.2.12 Tigon General Purpose Registers............................................................ 22.1.1.2.13 Tigon MAC RX State Register ............................................................... 24

2.1.1.3 Mailboxes .................................................................................................... 242.1.1.3.1 Host In Interrupt Handler ........................................................................ 25

2.1.1.4 General Communications Region ............................................................... 252.1.1.4.1 MAC Address ......................................................................................... 262.1.1.4.2 General Information Pointer ................................................................... 262.1.1.4.3 Multicast MAC Address Transfer Buffer (OBSOLETE) ....................... 262.1.1.4.4 Operating Mode ...................................................................................... 272.1.1.4.5 DMA Read Configuration....................................................................... 272.1.1.4.6 DMA Write Configuration...................................................................... 282.1.1.4.7 Transmit Buffer Ratio ............................................................................. 282.1.1.4.8 Event Consumer Index............................................................................ 22.1.1.4.9 Command Consumer Index .................................................................... 22.1.1.4.10 Tuning Parameters .................................................................................. 22.1.1.4.11 NIC Trace Pointer ................................................................................... 322.1.1.4.12 NIC Trace Start ....................................................................................... 322.1.1.4.13 NIC Trace Length ................................................................................... 322.1.1.4.14 ifIndex ..................................................................................................... 332.1.1.4.15 ifMtu........................................................................................................ 332.1.1.4.16 Mask Interrupts ....................................................................................... 332.1.1.4.17 Gigabit Link State ................................................................................... 332.1.1.4.18 10/100 Link State .................................................................................... 332.1.1.4.19 Receive Return Consumer Index (OBSOLETE on Tigon 2).................. 332.1.1.4.20 Command Ring ....................................................................................... 3


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2.1.1.5 Local Memory Window .............................................................................. 332.1.2 General Information Block .................................................................................. 34

2.1.2.1 Statistics....................................................................................................... 32.1.2.1.1 MAC Statistics ........................................................................................ 342.1.2.1.2 Interface Statistics ................................................................................... 32.1.2.1.3 Alteon Networks Proprietary MIB Statistics for the NIC....................... 35

2.1.2.2 Ring Control Blocks.................................................................................... 412.1.2.3 Event Producer Pointer................................................................................ 42.1.2.4 Receive Return Ring Producer Pointer ....................................................... 42.1.2.5 Send Consumer Pointer ............................................................................... 42.1.2.6 Refresh Stats Pointer ................................................................................... 4

2.2 SBus Memory Model ............................................................................................... 442.3 Serial EEPROM........................................................................................................ 4

2.3.1 Reading and Writing the Serial EEPROM........................................................... 442.3.2 Data fields in the Serial EEPROM....................................................................... 44

2.3.2.1 MAC Address.............................................................................................. 442.3.2.2 Software Key............................................................................................... 442.3.2.3 Customer Data Area .................................................................................... 4

2.4 Shared Rings............................................................................................................. 42.4.1 Control Rings ....................................................................................................... 4

2.4.1.1 Command Ring............................................................................................ 42.4.1.2 Event Ring................................................................................................... 45

2.4.2 Data Rings............................................................................................................ 42.4.2.1 Send Ring .................................................................................................... 42.4.2.2 Extended Send Ring Handling .................................................................... 462.4.2.3 Receive Rings.............................................................................................. 4

2.5 Interrupts................................................................................................................... 482.5.1 Interrupt Generation ............................................................................................. 42.5.2 Interrupt Avoidance ............................................................................................. 482.5.3 Masking Interrupts ............................................................................................... 4

2.6 Checksum Offload.................................................................................................... 42.6.1 Preparing the NIC for Checksum Offload ........................................................... 492.6.2 Per Packet Settings When Using Checksum Offload .......................................... 4

2.6.2.1 The Send Case ............................................................................................. 42.6.2.2 The Send Case for IP Fragmented Packets.................................................. 42.6.2.3 Limitations................................................................................................... 49

2.6.3 The Receive Case................................................................................................. 52.7 VLAN Assist ............................................................................................................ 50

2.7.1 Tag Insertion for Outgoing Frames...................................................................... 52.7.2 Tag Deletion for Incoming Frames ...................................................................... 50

2.8 Transmit Flow Diagram ........................................................................................... 512.9 Receive Flow Diagram............................................................................................. 52.10 Error Processing ....................................................................................................... 52.11 Frame Filtering ......................................................................................................... 5

3 Data Structures3.1 Buffer Descriptors .................................................................................................... 5

3.1.1 Receive Buffer Descriptors .................................................................................. 53.1.2 Send Buffer Descriptors....................................................................................... 5

3.2 Commands................................................................................................................ 63.2.1 Extended Commands ........................................................................................... 6

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3.2.2 TG_CMD_HOST_STATE .................................................................................. 613.2.3 TG_CMD_FDR_FILTERING............................................................................. 613.2.4 TG_CMD_SET_RECV_PRODUCER_INDEX (OBSOLETE).......................... 623.2.5 TG_CMD_UPDATE_GENCOM_STATS.......................................................... 623.2.6 TG_CMD_RESET_JUMBO_RING.................................................................... 623.2.7 TG_CMD_SET_PARTIAL_RECV_COUNT..................................................... 623.2.8 TG_CMD_ADD_MULTICAST_ADDR (OBSOLETE) .................................... 633.2.9 TG_CMD_DEL_MULTICAST_ADDR (OBSOLETE) ..................................... 633.2.10 TG_CMD_SET_PROMISC_MODE................................................................... 633.2.11 TG_CMD_LINK_NEGOTIATION .................................................................... 643.2.12 TG_CMD_SET_MAC_ADDR............................................................................ 643.2.13 TG_CMD_CLEAR_PROFILE............................................................................ 643.2.14 TG_CMD_SET_MULTICAST_MODE.............................................................. 643.2.15 TG_CMD_CLEAR_STATS................................................................................ 653.2.16 TG_CMD_SET_RECV_JUMBO_PRODUCER_INDEX (OBSOLETE) .......... 653.2.17 TG_CMD_REFRESH_STATS............................................................................ 653.2.18 TG_CMD_EXT_ADD_MULTICAST_ADDR................................................... 663.2.19 TG_CMD_EXT_DEL_MULTICAST_ADDR.................................................... 66

3.3 Events ....................................................................................................................... 663.3.1 TG_EVENT_NIC_FIRMWARE_OPERATIONAL........................................... 673.3.2 TG_EVENT_STATS_UPDATED ...................................................................... 673.3.3 TG_EVENT_LINK_STATE_CHANGED.......................................................... 673.3.4 TG_EVENT_ERROR.......................................................................................... 673.3.5 TG_EVENT_MULTICAST_LIST_UPDATED ................................................. 683.3.6 TG_EVENT_RESET_JUMBO_RING................................................................ 68

4 PERFORMANCE TUNING4.1 Reducing the Host/NIC interaction .......................................................................... 69

4.1.1 Information Coalescing........................................................................................ 694.1.2 Interrupt Avoidance ............................................................................................. 704.1.3 Receive Ring ........................................................................................................ 74.1.4 Send Ring ............................................................................................................. 74.1.5 Transmitting Latencies and Buffer Descriptors ................................................... 704.1.6 NIC Data Buffer Sizes ......................................................................................... 714.1.7 PCI Command Memory Write and Invalidate ..................................................... 714.1.8 Memory Write and Invalidate on the Tigon ASIC............................................... 714.1.9 Memory Write and Invalidate on the Tigon 2 ASIC............................................ 714.1.10 PCI Command Memory Read Multiple ............................................................... 724.1.11 PCI Burst Length.................................................................................................. 7

4.2 Checksum Offload.................................................................................................... 74.3 DMA Read Errata on Tigon 2 ASICs....................................................................... 72

4.3.1 Problem Description............................................................................................. 74.3.2 Details .................................................................................................................. 724.3.3 Work-around Options........................................................................................... 74.3.4 Impact Observations............................................................................................. 7

5 Firmware Initialization5.1 Power-on Bootstrap Sequence.................................................................................. 75.2 Hard Reset ................................................................................................................ 75.3 Operation at System Reboot ..................................................................................... 75.4 Firmware Download................................................................................................. 765.5 Firmware Reload Operation ..................................................................................... 7


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5.5.1 Runtime Program File .......................................................................................... 75.6 Link Ready Operation .............................................................................................. 7

6 Bibliography

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Table of Figures

Figure 1 MAC Address Format....................................................................................1Figure 2 Ring Control Block........................................................................................41Figure 3 Event Producer...............................................................................................4Figure 4 Receive Return Ring Producer.......................................................................4Figure 5 Send Consumer ..............................................................................................Figure 6 Producer-Consumer model ............................................................................4Figure 7 Producer-Consumer Model with data ............................................................4Figure 8 Transmit Flow Diagram.................................................................................5Figure 9 Receive Flow Diagram ..................................................................................5Figure 10 Receive Buffer Descriptor .............................................................................5Figure 11 Extended Receive Buffer Descriptor .............................................................5Figure 12 Send Buffer Descriptor ..................................................................................5Figure 13 Command Definition .....................................................................................6Figure 14 Event Definition.............................................................................................6


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Table of Tables

Table 1. LED Usage ........................................................................................................... 1Table 2. Shared Configuration Block................................................................................. 1Table 3. PCI Configuration Registers for SBus Cards....................................................... 1Table 4. Shared Memory Base Register............................................................................. 1Table 5. Tigon Configuration/Control Region................................................................... 19Table 6. Tigon Miscellaneous Host Control Register ........................................................ 20Table 7. Tigon Miscellaneous Local Control Register ...................................................... 20Table 8. Tigon Miscellaneous Configuration Register ...................................................... 21Table 9. Tigon PCI State Register...................................................................................... 2Table 10. Tigon DMA Assist State Register........................................................................ 2Table 11. Tigon CPU State Register .................................................................................... 2Table 12. Tigon MAC RX State Register ............................................................................ 24Table 13. Mailbox Registers ................................................................................................ 2Table 14. General Communications Registers..................................................................... 2Table 15. Operating Mode and Status.................................................................................. 2Table 16. DMA Read Configuration Mode ......................................................................... 28Table 17. DMA Write Configuration Mode......................................................................... 28Table 18. Tuning Parameters ............................................................................................... 2Table 19. NIC Tracing definitions ....................................................................................... 30Table 20. Link Negotiation Bit Definitions ......................................................................... 31Table 21. Link Negotiation Bit Definitions ......................................................................... 32Table 22. General Information Block .................................................................................. 34Table 23. RCB Flags ............................................................................................................ 41Table 24. SBus Address Space.............................................................................................Table 25. Errored Frame Flags............................................................................................. 5Table 26. Buffer Descriptor Flags........................................................................................ 6Table 27. TG_CMD_HOST_STATE flags.......................................................................... 61Table 28. TG_CMD_FDR_FILTERING flags .................................................................... 61Table 29. TG_CMD_SET_PROMISCUOUS_MODE flags ............................................... 63Table 30. TG_CMD_SET_LINK_NEGOTIATION flags................................................... 64Table 31. TG_CMD_SET_MULTICAST_MODE flags..................................................... 65Table 32. TG_EVENT_LINK_STATE_CHANGED codes................................................ 67Table 33. ERROR codes ...................................................................................................... 6Table 34. TG_EVENT_MULTICAST_LIST_UPDATED codes ....................................... 68Table 35. Memory Read Command Usage .......................................................................... 7Table 36. Firmware Failure Locations ................................................................................. 7


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Gigabit Ethernet/PCI NIC Software Definition Introduction

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1 Introduction

The Alteon Networks Gigabit Ethernet/PCI Network Interface Card (NIC) provides a full or hduplex Gigabit Ethernet interface compliant with the proposed IEEE 802.3z standard. The Nimplemented for use in systems that support either the 32 or 64 bit wide PCI Local Bus opeat 33 MHz. The Tigon 2 equipped version of the NIC adds support for 66 MHz buses. This maalso includes documentation for a 32-bit or 64-bit SBus card using the same Tigon technolowith a special bridge chip.

The NIC acts as a bus master to DMA data between the Host and the NIC. Host access to this through a shared memory segment and control structures in Host memory. The NIC has eiMB or 512 KB of memory depending on the hardware configuration. The NIC has either a Sfiber connector or 10/100/1000 copper connector.

The NIC performs all the necessary Gigabit Ethernet MAC and PHY layer processing. The Hsoftware provides frames to be sent and accepts received frames. Data is managed using rbuffers. Interrupts are generated based on conditions in the Event, Send or Receive Rings anecessarily on a per frame basis.

1.1 TIGON

The Alteon Networks Gigabit Ethernet NIC is implemented by utilizing a proprietary customApplication Specific Integrated Circuit (ASIC). This ASIC, known as the Tigon ASIC or Tigon(for short), incorporates dual DMA channels, a Gigabit Ethernet MAC, the PCI Interface, anRISC based processor. The Tigon 2 ASIC adds a second RISC processor, higher memorythroughput, additional hardware offload features, and higher clock rates. Throughout thisdocument the original Tigon chip will be referred to as Tigon or as Version 4 Tigon. The newTigon 2 chip will be referred to as Tigon 2 or Version 5 or Version 6 Tigon.

Version 4 (original Tigon ASIC) and Version 5 or 6 (Tigon 2 ASIC) usage are defined in thisdocument. Different firmware for each version of the ASIC is provided in the Open Driver KiYou can write your driver to support either ASIC or both ASICs. To support only the originalversion 4 ASIC please ensure that TIGON_REV is defined to be 1 either through an include fithrough your C compiler and your Makefile. To support only Version 5 and 6 of the ASIC pleensure that TIGON_REV is defined to be 2. To support all of Version 4, Version 5, and Versplease ensure that TIGON_REV is defined to be 3.

1.2 Feature Set

The Alteon NIC and firmware allow a large number of host assistance features. One of theschecksum offload. The NIC can do complete checksum offload for both transmitted and recframes. This checksum offload feature allows full checksum calculation (includingpseudo-headers) for IP, TCP, and UDP packets. On the transmit side the host can even setbuffers in such a way that fragmented frames can have their UDP or TCP checksums calcuover the entire datagram. Detailed discussion of the checksum offload features can be founsection 2.6 of this document.

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1.3 Foundation Data Structures

1.3.1 Host AddressesThe Host/NIC interface views all Host addresses as 64 bit objects, even on 32 bit hosts. OnHosts, the upper 32 bits must be zero. These addresses are in big endian byte order.

1.3.2 NIC AddressesAll of the NIC address are 32 bits long and can only be addressed via 32 bit accesses with exception of PCI Configuration Space and PCI Configuration Registers which can be addres1, 2, 3, or 4 bytes.

1.3.3 MAC AddressesThe MAC addresses are 48 bit objects which are padded to 64 bits as shown in Figure 1. [3

Figure 1. MAC Address Format

1.3.4 EndiannessThe NIC is a big endian machine. The DMA engine can be configured to perform byte swapwhile transferring data, control information or both. All data DMAed to and from the NIC shobe in Host byte order on the Host; it is byte swapped to the proper endian during DMA. All datthe shared memory space must be big endian since the NIC is big endian. The endian configuof the control and data DMA transfers is set by the Host in the Operating Mode and Status re(See “Operating Mode”, section 2.1.1.4.4). In addition, all data that is placed into the NIC throPIOs needs to be in big endian format. This is controlled through the use of the MiscellaneoHost Control register (See “Tigon Miscellaneous Host Control Register”, section 2.1.1.2.1).

There is also the concept of “word endianness” in the NIC. Data is either dealt with as a 32 quantity or as a byte stream. In either case, since the memory subsystem of the NIC is a 64memory subsystem, the host must ensure that the words are reversed. This is done by settproper word swapping bits in the Miscellaneous Host Control register (See “Tigon MiscellanHost Control Register”, section 2.1.1.2.1) and the Operating Mode and Status register (See“Operating Mode”, section 2.1.1.4.4).

The following is a brief discussion to help you figure out how to set these bytes on your syst

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Rule 1: Since our basic unit of interaction is a 32 bit quantity the bits show up the same whethey are big-endian or little-endian.

Rule 2: PCI is defined as a little-endian bus.

Given these rules, lets look at what typically happens on little-endian hosts. Since the PCI bdefined as little-endian and the memory system is defined as little-endian most (all?) little-esystems pass the bytes through to the bus in the same order that they appear in memory. Sbit quantities (as everything in the data structures is treated) there is no need to byte swap (Misc Host Control register is set to not swap and the TG_CFG_MODE_SWAP_BD bit is not

For network data (which is defined as a byte stream) the data is presented in little-endian fo(byte swapped) so the data must be byte swapped (TG_CFG_MODE_SWAP_DATA).

Now, let's look at “most” big-endian hosts. Since the PCI bus is defined as little-endian, andmemory system is defined as big-endian, the host is often built to “pre-swap” all the data thatravels across the bus so it shows up in the “right order”. But this swapping is really “wrong”32 bit quantities (we noted in rule 1 that these are always the same). So in this case we havebyte swapping on for all data structures (the byte swapping bit in the Misc Host Control regiand the TG_CFG_MODE_SWAP_BD bit). Data is still byte oriented, but it is in big-endianformat. Since these hosts pre-swap the data we must also byte swap data in order to get it bathe right order (hence the TG_CFG_MODE_SWAP_DATA bit).

One more endian issue has to do with word swapping. This can effect both addresses in thememory region and those in the host. For little endian systems that have no way of doing a write to the shared memory put support 64 bit hardware address (e.g. some Intel x86 systemhigh order 32 bits will have to be swapped with the low order 32 bits. This is because the NIwants all 64 bits in big endian format and the host has them in little endian format. If a 64 bitransfer were done then the words would be swapped by the hardware, but if no 64 bit instrcan be used the host code must explicitly swap them. For little endian systems with 64 bitaddresses the two words of addresses in host memory will have to be swapped to create a endian look in the host.

1.4 LED Meanings

There are two LEDs on Gigabit NICs. A “Link” LED and a “Data” LED. In general, the link LEDindicates that the link is up and the data LED flashes when there is data movement on the NICNIC enabled means that a TG_CMD_HOST_STATE UP command has been issued to the N(See “TG_CMD_HOST_STATE”, section 3.2.2).

Table 1. LED Usage

Link LED solidData LED with Solid

Link LEDData LED by itself

Slow Flashing LinkLED

Link is active, NIC isenabled

Data activity on theNIC

Fault condition, firm-ware is halted

NIC is disabled, butfirmware is loadedand running




l

2 Architecture

2.1 Memory Model

The NIC manages data structures in Host memory using DMA and the following two controblocks:

• the Shared Configuration Block, and

• the General Information Block.

2.1.1 Shared Configuration BlockThis is a 16K byte shared memory region of Host mapped memory as shown in Table 2.

Host Data Space Shared Memory Space NIC Data Space

NIC registers

Shared Config Block

gen info pointer

Statistics

Event RCB

Command RCB

Send RCB

Std Recv RCB

Jumbo Recv RCB

Event Producer Ptr

Statistics

Event RCB

Command RCB

Send RCB

Std Recv RCB

Jumbo Recv RCB

Event Producer Ptr

DMA

Send Consumer Ptr

Recv Return Pro-ducer Ptr

Send Consumer Ptr

Recv Return Pro-ducer Ptr

Refresh Stats Ptr Refresh Stats Ptr

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Gigabit Ethernet/PCI NIC Software Definition Architecture

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All registers in this block can be shared between the Host and the NIC, however some are uoperationally by the Host while others are used operationally by the NIC. All registers are 32long.

2.1.1.1 PCI Configuration RegionPlease refer to the PCI Local Bus Specifications[1] for details. Vendor Subsystem IDs aresupported only in Tigon 2 (Version 5 or 6) ASICs

2.1.1.1.1 PCI Configuration Region Setup for SBus CardsSince the SBus card uses a bridge chip, the PCI bus configuration region will not be set up system’s BIOS. The following registers must be set correctly. The SBus bridge chip only alloaccesses in 4 byte quantities. All these registers should be set using the PCI Config region SBus address space (See “SBus Memory Model”, section 2.2).

2.1.1.1.1.1 Command/Status RegisterThis register is a pair of registers that indicate the Status and the Command registers of theConfiguration space. This should be set to the value 0x02000006 in big endian format.

2.1.1.1.1.2 Latency Timer, etc. RegisterThis register is really four PCI configuration registers. It should be set to 0xFFFFFFFF.

NOTE: This region contains registers and “holes”. There are addresses that cannot be read written.

NOTE: Bits and fields that are meaningful only for Tigon 2 are indicated with the words (Tigononly) and are lightly shaded if described in a Table.

Table 2. Shared Configuration Block

Shared Configuration Block Address

PCI Configuration Region 0x0000 - 0x003F

Tigon Configuration Region 0x0040 - 0x04FF

Mailboxes 0x0500 - 0x05FF

General Communications Region 0x0600 - 0x07FF

Local Memory Window 0x0800 - 0x0FFF

Reserved 0x1000 - 0x3FFF

Table 3. PCI Configuration Registers for SBus Cards

PCI Configuration Registers Address

Command/Status Register 0x04 - 0x07

Latency Timer, etc. 0x0C - 0x0F

Shared Memory Base 0x10 - 0x13



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2.1.1.1.1.3 Shared Memory Base RegisterThis register specifies the addresses that the SBus - PCI bus chip will generate when data isin the 16 KB shared memory region of the SBus address space. It also specifies to the PCI where it should respond to shared memory accesses. It is critical that this space not ever be ua DMA address or the PCI chip will respond to its own DMA requests.

2.1.1.2 Tigon Configuration/Control RegionThe Tigon Configuration/Control Region is composed of several 32 bit registers. See Tabledetails.

.

Table 4. Shared Memory Base Register

Bit Name Access Description

0x000000FF Reserved W/O These bits must be set to zero.

0x00000100 Chaining W/O If set the NIC will not perform SBus chaining.

0x00000600 Transfer Size W/O If ‘00’ do 16 word/dword transfers, if ‘01’ do 8 word/dword transfers, if ‘10’ do 4 word/dword transfers, if ‘11’do 1 word/dword transfers.

0x00000800 Reset W/O If set the bridge chip is held in reset.

0x00003000 Reserved W/O This bits must be set to zero.

0xFFFFC000 Base Address R/W These bits specify the base address used by the bridgechip and the Tigon chip for shared memory accesses.

Table 5. Tigon Configuration/Control Region

Tigon Configuration Region Address

Tigon Miscellaneous Host Control 0x040 - 0x043

Tigon Miscellaneous Local Control 0x044 - 0x047

Tigon Miscellaneous Configuration (Tigon 2 only) 0x050 - 0x053

Tigon PCI State 0x05C - 0x05F

Tigon Window Base Address 0x068 - 0x06B

Tigon Window Data 0x06C - 0x06F

Tigon DMA Assist State 0x11C - 0x11F

Tigon CPU State 0x140 - 0x143

Tigon CPU Program Counter 0x144 - 0x147

Tigon Internal SRAM Address 0x154 - 0x157

Tigon Internal SRAM Data 0x158 - 0x15B

Tigon General Purpose Registers 0x180 - 0x1FF

Tigon MAC RX State 0x220 - 0x223

Tigon CPU Control (CPU B) (Tigon 2 only) 0x240 - 0x243

Tigon CPU Program Counter (CPU B) (Tigon 2 only) 0x244 - 0x247

Tigon Internal SRAM Address (CPU B) (Tigon 2 only) 0x254 - 0x257

Tigon Internal SRAM Data (CPU B) (Tigon 2 only) 0x258 - 0x25B

Tigon General Purpose Registers (CPU B) (Tigon 2 only) 0x280 - 0x2FF



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2.1.1.2.1 Tigon Miscellaneous Host Control RegisterThe Miscellaneous Host Control register is used to control various functions within the Tigonnormally controlled from the host interface.

All bits of the Miscellaneous Host Control register not specified in Table 6 must be set to 0.

2.1.1.2.2 Tigon Miscellaneous Local Control RegisterThe Miscellaneous Local Control register is used to control various functions within the Tigonormally controlled from the internal processor. All bits are set to zero during reset.

Change only the Miscellaneous Local Control register bits specified in Table 7. All other bits mbe left unchanged.

Table 6. Tigon Miscellaneous Host Control Register


0x00000001 Interrupt State R/O This bit reflects the state of the PCI IntA Output pin

0x00000002 Clear Interrupt W/O This bit clears the host PCI Interrupt IntA

0x00000008 Reset R/W Force a complete hardware reset, except PCIConfiguration Registers (0x0 - 0x3F)

0x00000010 Enable Endian ByteSwap

R/W Enable endian byte swapping when accessing Tigonthrough target interface

0x00000020 Enable Endian WordSwap

R/W Enable endian word swapping when accessing Tigonthrough target interface.

0x00000040 Mask Interrupts R/W Mask interrupts while set. Pending interrupts will begenerated when the bit is cleared. If the interrupt line isasserted it will be deasserted when this bit is set. (Tigon2 Revision 6 only)

0xF0000000 Chip Version Mask R/O This is a 4-bit field which carries the Version of the TigonASIC. It can contain 4 (Tigon) or 5 or 6 (Tigon 2)

Table 7. Tigon Miscellaneous Local Control Register


0x00000010 Enable EEPROMWrite

R/W Enables writing to EEPROM Region

0x00000200 SRAM Bank 256K R/W Each bank of SRAM is 256K instead of 1M bytes (Tigon1 only)

0x00000300 SRAM Bank Size R/W A two bit field to indicate the size of the SRAM bank. 0is for a single bank. 1 is for a bank size of 1M. 2 is for abank size of 512KB. 3 is for a bank size of 256KB.PCINICs have 512KB per bank. (Tigon 2 only)

0x00004000 Local Address21 R/W Used for bank switching flash memory by directlycontrolling local address bit 21

0x00008000 Local Address22 R/W Used for bank switching flash memory by directlycontrolling local address bit 22

0x00080000 SBus Write Error R/O Indicates there was an SBus Write Error

0x00100000 Serial EEPROM clockOutput

R/W Directly controls the clock output pin

0x00200000 Serial EEPROM DataOutput Enable

R/W When Asserted, Tigon drives the value of SerialEEPROM data output.



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2.1.1.2.3 Tigon Miscellaneous Configuration RegisterThe Miscellaneous Configuration register is used to control various functions within the Tigonormally controlled from the internal processor at configuration time. All bits are set to zeroduring reset. This register is only available on the Tigon 2 ASIC.

Change only the Miscellaneous Configuration register bits specified in Table 7. All other bits mbe left unchanged.

2.1.1.2.4 Tigon PCI State RegisterThe PCI State register is used to control various functions within the Tigon associated with Interface. All bits are set to zero during reset.

All of the PCI State register bits not specified in Table 9 must be set to 0.

0x00400000 Serial EEPROM DataOutput

R/W Value of data to drive out when output enabled

0x00800000 Serial EEPROM DataInput

R/O Input from bi-directional serial EEPROM data pin.

NOTE: Writes to the Tigon Miscellaneous Local Control Register should only be performed wthe internal processor is halted.

Table 8. Tigon Miscellaneous Configuration Register


0x00100000 Set SynchronousSRAM timing

R/W Must be set for boards that contain synchronous SRAM(Tigon 2 only)

NOTE: Writes to the Tigon Miscellaneous Configuration Register should only be performed wthe internal processor is halted.

Table 9. Tigon PCI State Register

Bit(s) Name Access Description

0x00000001 Force Reset W/O Will force an immediate reset of the PCI Interface. All stateinformation within the PCI Configuration registers will belost. This bit is self clearing.

0x00000002 Provide Length R/W Use non-standard PCI interface which provides transferlength indication. On PCI cards there is never any reasonto set this bit.

0x0000001C Read Max DMA R/W This is a 3-bit field. Encoded bits which force terminationof PCI read operations at any of the following boundaries:Disable (000), 4 (001), 16 (010), 32 (011), 64 (100), 128(101), 256 (110), 1K (111). For SBus cards this should beset to 100.

Table 7. Tigon Miscellaneous Local Control Register




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2.1.1.2.5 Tigon Window Base Address RegisterThe Window Base Address register defines the local memory address (from the point of viethe NIC’s internal processor) which is the base for the 2 Kilobyte window provided by the Tig(See “Shared Configuration Block”, section Table 2. and See “Local Memory Window”, sect2.1.1.5.) This register may contain any valid local memory address, but the usage of the lea

0x000000E0 Write Max DMA R/W This is a 3-bit field. Encoded bits which force terminationof PCI write operations at any of the following boundaries:Disable (000), 4 (001), 16 (010), 32 (011), 64 (100), 128(101), 256 (110), 1K (111). For SBus cards this should beset to 100.

0x0000FF00 Minimum DMA R/W This 8 bit field contains the minimum number of PCI wordseach DMA channel is allowed to keep the PCI bus withoutallowing accesses by the other DMA channel. Thisguarantees a minimum PCI usage rather than the usualalternate per burst behavior. Due to hardware bugs thisfield MUST be set to zero.

0x00010000 FIFO Retry enable R/W Enable PCI retry response to PCI target accesses to FIFOwhen FIFO cannot complete operation. This bit is not usedfor normal operation.

0x00020000 UseMem_Read_MultiplePCI Command

R/W Use Memory Read Multiple command in place of MemoryRead Line for DMA reads.

0x00040000 No Word Swap (Read)DMA

R/W Disable word swapping for all read DMA Transactions. ForTigon 2 ASICs this controls both the read and the writeDMA channels.

0x00080000 No Word Swap WriteDMA

R/W Disable word swapping for all write DMA Transactions.Only for the original Tigon ASIC.

0x00080000 66 MHz Bus indication R/O Set if the card has negotiated for a 66 MHz bus clockspeed. Tigon 2 ASIC only.

0x00100000 32-bit PCI bus R/O or R/W Current Host is providing only a 32-bit PCI Bus. On Tigon2 ASICs can be written to override systems where 64 bitoperation has been negotiated incorrectly.

0x00800000 Enable all ByteEnables

R/W This bit must be used with Tigon 2 ASIC SBus cards andmust not be set on any other card. It causes all the PCIbyte enables to be set on every WRITE DMA.

0x0F000000 PCI Read Command R/W This is a 4-bit field. The NIC uses this command for all PCIread transactions of <3 words or half the cache line size ifset. This field should normally be set to 6 (Memory Read).

0xF0000000 PCI Write Command R/W This is a 4-bit field. The NIC uses this command for all PCIwrite transactions. This field should normally be set to 7(Memory Write). See “PCI Command Memory Write andInvalidate”, section 4.6 for information on using theMemory Write and Invalidate.

Table 9. Tigon PCI State Register

Bit(s) Name Access Description



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significant 11-bits varies depending on how the local memory is addressed. If the 2 Kilobytewindow is used, then the least significant 11-bits are ignored and are substituted with zerosWindow Data register is referenced, then the entire Window Address register is used to indithe local memory address of the operation.

The Window Base Address register (in conjunction with the local memory window) is used tdownload the firmware into the NIC (See “Firmware Download”, section 5.4). It is also usedaddress the Send Ring. (See “Send Ring”, section 2.4.2.1.)

2.1.1.2.6 Tigon Window Data RegisterThe Window Data register is normally used to access locations in the local memory when thactual 2k Byte local memory window provided by the Tigon is unavailable. Only 32-bit operatiare supported on this register.

The Window Data register (in conjunction with Window Base Address Register) provides anindirect method to access the entire local memory address space.

2.1.1.2.7 Tigon DMA Assist State RegisterThe DMA Assist State register is used to control the DMA assist logic within the Tigon. The DMassist logic allows the NIC to queue DMAs that will then be dequeued and executed by thehardware. Stopping the DMA Assist does not stop the current DMA it only prevents the nexqueued DMA from starting.

All of the DMA Assist State register bits not specified in Table 10 must be left unchanged.

2.1.1.2.8 Tigon CPU State RegisterThe CPU State register controls miscellaneous functions associated with the CPU in additioindicating the state of the processor. Alteon Networks uses these bits a great deal to implemfirmware debugger. In general, a driver writer should not need to adjust these bits directly. OTigon 2 ASIC there are two CPUs (CPU A and CPU B). There is a CPU State Register for eCPU.

NOTE: The Window Base Address register cannot be used by the host to access registers intto Tigon. It is only used to access memory internal to Tigon.

Table 10. Tigon DMA Assist State Register


0x00000001 Enable R/W Enable DMA Assist Logic

0x00000002 Pause R/W Stop DMA Assist Logic. Does not affect the DMATransfers which are active.

Table 11. Tigon CPU State Register


0x00000001 Reset CPU R/W Self clearing bit which resets the internal CPU.

0x00000002 Single Step CPU R/W Advances the CPU’s Program Counter one cycle. If thehalting condition (e.g. an invalid instruction at thelocation) still exists then the CPU will again halt,otherwise it will resume normal operation.



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2.1.1.2.9 Tigon CPU Program Counter RegisterThe CPU Program Counter register points to the instruction which is being fetched by the intprocessor. It normally changes every clock cycle during normal execution. This register canwritten by the host only when the processor has been halted. On the Tigon 2 ASIC there arCPUs (CPU A and CPU B). There is a CPU Program Counter for each CPU.

2.1.1.2.10 Tigon Internal SRAM Address RegisterThis register is analogous to the Tigon Window Base Register for the accessing the InternaSRAM. One difference is that the memory can only be accessed through the Tigon Internal SData Register. That is, there is no equivalent to the Local Memory Window. On the Tigon 2 Athere are two CPUs (CPU A and CPU B). There is a Tigon Internal SRAM Address Registeeach CPU. The size of the Internal SRAM is 2 KB on the original Tigon, 16 KB on CPU A ofTigon 2, and 8 KB on CPU B of Tigon 2. The local memory address of the Internal SRAM begat 0xC00000.

2.1.1.2.11 Tigon Internal SRAM Data RegisterThis register is analogous to the Tigon Window Data Register.

2.1.1.2.12 Tigon General Purpose RegistersYou can access the internal registers of the Tigon’s CPU via the register file. There are 32 regOn the Tigon 2 ASIC there are two CPUs (CPU A and CPU B). There is a CPU Register Fileach CPU.

2.1.1.2.13 Tigon MAC RX State RegisterThe MAC RX state register is used to control and monitor the Ethernet receive interface of tTigon.

All of the MAC RX state register bits not specified in Table 12 must be left unchanged.

2.1.1.3 MailboxesThis is a 256 byte region which contains 32 sixty-four bit registers. These registers are calleMailbox Registers (or Mailboxes). When a value is stored in the least significant 32 bits of thregisters, an event (known as Mailbox Event) is generated to the Tigon Internal Processor.

0x00000010 ROM Fail R/W Asserted on reset and cleared by ROM code aftersuccessfully loading code from serial EEPROM orFlash.

0x00010000 Halt CPU R/W Set by the external Host to halt the internal CPU.

Table 12. Tigon MAC RX State Register


0x00000004 Stop RX After NextPacket

R/W Setting this bit disables the Receive MAC gracefully atnext inter-packet gap.

Table 11. Tigon CPU State Register




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In the present version of the API, only the first six Mailboxes are used. Others are reserved future enhancements.

2.1.1.3.1 Host In Interrupt HandlerThe NIC firmware uses this register to determine if it should interrupt the Host. A value of 1 inregister means the Host is presently handling Events, and should not be interrupted. Every timHost enters the Interrupt Handler, this register must be set to 1. Once the Host is done procall the events, it must set this register to 0. This register must be initialized to 0.

2.1.1.3.1.1 Command Producer IndexThe Command Producer Index register (Mailbox 1), contains the index of the next command iCommand Ring that will be produced. Host software writes this register whenever the commring is updated. This register must be initialized to 0.

2.1.1.3.1.2 Send Producer IndexThe Send Producer Index register (Mailbox 2), contains the index of the next buffer descriptowill be produced. Host software writes this register whenever the send ring is updated. Thisregister must be initialized to 0.

2.1.1.4 General Communications RegionThese registers are active when the firmware is loaded and running. The registers are usedcommunication between the host and the processor internal to the Tigon chip. The area is 5bytes long. Data in this area must be accessed 32 bits at a time.

Table 14 shows the mapping of registers in this area.

Table 13. Mailbox Registers

Mailboxes Address

“Host In Interrupt Handler” (Mailbox 0) 0x500 - 0x507

Command Producer Index (Mailbox 1) 0x508 - 0x50F

Send Producer Index (Mailbox 2) 0x510 - 0x517

Standard Receive Producer Index (Mailbox 3) (Tigon 2 only) 0x518 - 0x51F

Jumbo Receive Producer Index (Mailbox 4) (Tigon 2 only) 0x520 - 0x527

Mini Receive Producer Index (Mailbox 5) (Tigon 2 only) 0x528 - 0x52F

Reserved (Mailbox 6- 31) 0x530 - 0x5FF

NOTE: Writing any value into Mailbox Register 0 (the Host In Interrupt Handler mailbox) hasside effect of clearing the PCI Interrupt.

Table 14. General Communications Registers

General Communications Registers Address

MAC address 0x600 - 0x607

General Information Pointer 0x608 - 0x60F

Multicast MAC Address Transfer Buffer 0x610 - 0x617

Operating Mode and Status 0x618 - 0x61B

DMA Read Configuration 0x61C - 0x61F



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2.1.1.4.1 MAC AddressThe MAC Address register contains the MAC address of the NIC. It is in MAC address formatFigure 1). This register must be initialized by the Host prior to starting the firmware. It is usuthe MAC address extracted by the Host from the NIC’s EEPROM.

The MAC address placed here is only read at two times by the NIC firmware. It is read atinitialization and it is read when a TG_CMD_SET_MAC_ADDR command is issued (See“TG_CMD_SET_MAC_ADDR”, section 3.2.12.)

2.1.1.4.2 General Information PointerThe General Information Pointer register contains the 64 bit Host address of the GeneralInformation page in Host memory. This register must be initialized by the Host prior to startingfirmware. Once the firmware has initialized, it does not reference the General Information pagain.

2.1.1.4.3 Multicast MAC Address Transfer Buffer (OBSOLETE)The Multicast MAC Address Transfer Buffer is where the host places the multicast MAC Addto be added or deleted from the NIC’s multicast list, using theTG_CMD_ADD_MULTICAST_ADDR or the TG_CMD_DEL_MULTICAST_ADDRcommands. It is in MAC address format (see figure 1).

The use of this buffer has been obsoleted by the newTG_CMD_EXT_ADD_MULTICAST_ADDR and theTG_CMD_EXT_DEL_MULTICAST_ADDR commands.

DMA Write Configuration 0x620 - 0x623

Transmit Buffer Ratio 0x624 - 0x627

Event Consumer Index 0x628 - 0x62B

Command Consumer Index 0x62C - 0x62F

Tuning Parameters 0x630 - 0x64F

NIC Trace Pointer 0x650 - 0x653

NIC Trace Start 0x654 - 0x657

NIC Trace Length 0x658 - 0x65B

ifIndex 0x65C - 0x65F

ifMtu 0x660 - 0x663

Mask Interrupts 0x664 - 0x667

Gigabit Link State 0x668 - 0x66B

10/100 Link State 0x66C - 0x66F

Reserved(4) 0x670 - 0x67F

Receive Return Consumer Index 0x680 - 0x683

Reserved(31) 0x684-0x6ff

Command Ring 0x700 - 0x7FF

Table 14. General Communications Registers

General Communications Registers Address



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2.1.1.4.4 Operating ModeThe Operating Mode register sets various operational modes in the firmware.

2.1.1.4.5 DMA Read ConfigurationThe NIC supports both 32-bit and 64-bit interfaces. Some Hosts may want to use 32-bit intewhile others may want 64-bit mode. The DMA Read Configuration register allows the Host tprogram the interface appropriately. Additionally, the this register offers flexibility to control whthe DMA engine should make a request for PCI operation.

Table 15. Operating Mode and Status

Bit Name Description

0x00000002 BYTE_SWAP_BD Byte swap buffer descriptors and events when DMAing them to andfrom the Host.

0x00000004 WORD_SWAP_BD This bit is not operational in the current release of firmware, butshould be set to one in case it should ever be enabled in futurerevisions.

0x00000008 WARN Enables warnings through events from the firmware. There are nooperational differences when setting this bit currently. It isrecommended that this bit be set for possible future enhancementsto the firmware.

0x00000010 BYTE_SWAP_DATA Byte swap data when DMAing it to and from the Host.

0x00000040 1_DMA_ACTIVE Program the interface to activate only one DMA Channel at a time,i.e. either Read or Write at a time, not both. It is recommended thatthis bit not be set. On SBus drivers, this bit MUST be set to One.

0x00000100 SBUS Must be set for SBus cards. Must not be set for non-SBus cards.

0x00000200 DONT_FRAG_JUMBOS Don’t split received Jumbo frames across multiple standard sizedbuffer descriptors if no jumbo sized buffer descriptors are available.

0x00000400 INCLUDE_CRC Include the CRC on all packets passed to the host and in the lengthfield of the buffer descriptor.

0x00000800 ALLOW_BAD_FRAMES DMA bad frames and associated receive buffer descriptors forframes that have errors. The error is indicated in the receive bufferdescriptor. (See See “Receive Buffer Descriptors”, section 3.1.1.)

0x00001000 DONT_RUPT_EVENTS Never generate interrupts when the event producer index isupdated.

0x00002000 DONT_RUPT_SENDS Never generate interrupts when the send consumer index isupdated.

0x00004000 DONT_RUPT_RECVS Never generate interrupts when the receive return producer index isupdated.

0x40000000 FATAL Enables fatal error indication through events. There are nooperational differences when setting this bit currently. It isrecommended that this bit be set for possible future enhancementsto the firmware



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The DMA read configuration register must be set by the Host based upon the interface it withe NIC to use while reading data from the Host Memory. Please refer to Table 16 for theappropriate values.

2.1.1.4.6 DMA Write ConfigurationThe NIC supports both 32-bit and 64-bit interfaces. Some Hosts may want to use 32-bit intewhile others may want 64-bit mode. The DMA Read Configuration register allows the Host tprogram the interface appropriately. Additionally, the this register offers flexibility to control whthe DMA engine should make a request for PCI operation.

The DMA Write Configuration register must be set by the Host based upon the interface it withe NIC to use while writing data into the Host Memory. Please refer to Table 17 for approprvalues.

2.1.1.4.7 Transmit Buffer RatioThis register is used to indicate the ratio of the remaining memory in the NIC that should bedevoted to Transmit Buffer vs. Receive Buffer. The bottom 7 bits are used to indicate the ratio64th increments. For example, setting this value to 16 will set the transmit buffer to 1/4 of thremaining buffer space. In no cases will the Transmit or Receive buffer be reduced below 68For a 1 MB NIC the approximate total space for data buffers is 800 KB. For a 512 KB NIC thnumber is 300 KB.

2.1.1.4.8 Event Consumer IndexThe Event Consumer Index register contains the index of the next event in the Event Ring thabe consumed. The Host writes this register whenever an event is consumed. This register minitialized to 0.

Table 16. DMA Read Configuration Mode

Bit(s) Name Description

0x00000008 FORCE_32_BIT_PCI If set, force PCI Operation to be performed as if on a 32-bit PCIBus. By default the bus will “self detect.”

0x000001F0 Threshold This is a five bit field and represents the number of empty wordsin the FIFO before the DMA channel requests a PCI operation.The Host must set a value between 1 - 16. It is recommended touse a value of 8. SBus Driver Note: Use threshold value of 8 bytesfor SBus Drivers.

Table 17. DMA Write Configuration Mode

Bit(s) Name Description

0x00000008 FORCE_32_BIT_PCI If set, force PCI Operation to be performed as if on a 32-bit PCI Bus.By default the bus will “self detect.”

0x000001F0 Threshold This is a five bit field and represents the number of empty words inthe FIFO before the DMA channel requests a PCI operation. Oncethe last word to be written to the host has been placed into the FIFO,the host bus will be requested until the FIFO goes empty. The Hostmust set a value between 1 - 16. It is recommended to use a valueof 8. SBus Driver Note: Use threshold value of 8 bytes for SBusDrivers.



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2.1.1.4.9 Command Consumer IndexThe Command Consumer Index register contains the index of the next command in the ComRing that will be consumed. The NIC writes this register whenever a command is consumed.register must be initialized to 0.

2.1.1.4.10 Tuning ParametersThese are the tuning parameters that may be modified by the Host at any time to tune the Nfirmware.

2.1.1.4.10.1Receive Coalesced TicksThe Receive Coalesced Ticks register contains the number of clock ticks (of 1 microsecondsthat must elapse before the NIC DMAs the receive return producer pointer to the Host andgenerates an interrupt. This tunable parameter works in conjunction with the Receive MaxCoalesced BDs tunable parameter. This NIC will return the receive return producer pointer Host when either of the thresholds is exceeded. A value of 0 means that this parameter is igand Receive BDs will only be returned when the Receive Max Coalesced BDs value is reacThis register must be initialized by the Host.

2.1.1.4.10.2 Send Coalesced TicksThe Send Coalesced Ticks register contains the number of clock ticks (of 1 microseconds ethat must elapse before the NIC DMAs the send consumer pointer to the Host and generateinterrupt. This tunable parameter works in conjunction with the Send Max Coalesced BDs tunparameter. This NIC will return the send consumer pointer to the Host when either of thethresholds is exceeded. A value of 0 means that this parameter is ignored and Send BDs wbe returned when the Send Max Coalesced BDs value is reached. This register must be iniby the Host. For hosts that need to recover their send buffers this value should be set a valuwill allow the Host to recover their send buffers in a reasonable time period. For hosts that dneed to recover their send buffers this value should be set to zero.

Table 18. Tuning Parameters

Tuning Parameters Offset

Receive coalesced ticks 0x00

Send coalesced ticks 0x04

Stat ticks 0x08

Send max coalesced BDs 0x0C

Receive max coalesced BDs 0x10

NIC tracing 0x14

Gigabit Link Negotiation 0x18

10/100 Link Negotiation 0x1c



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2.1.1.4.10.3 Stat TicksThe Stat Ticks register contains the number of clock ticks (of 1 microseconds each) that muelapse before the NIC DMAs the statistics block to the Host and generates a STATS_UPDAevent. If set to zero then statistics are never DMAed to the Host. This register must be initiaby the Host. It is recommended that this value be set to a high enough frequency to not missomeone reading statistics refreshes. Several times a second is enough.

2.1.1.4.10.4 Send Max Coalesced BDsThe Send Max Coalesced BDs register contains the number of buffer descriptors that will bcoalesced before the NIC updates the Send Consumer Index. This register is set to 0 to dissend buffer descriptor coalescing. This register must be initialized by the Host. There is no sirecommendation that can be given for this register. The factors that affect this register’s settinsize of the Send Ring and the Host’s usage of send buffers.

2.1.1.4.10.5 Receive Max Coalesced BDsThe Receive Max Coalesced BDs register contains the number of buffer descriptors that wilcoalesced before the NIC updates the Receive Return Ring Producer Index. This register is sto disable receive buffer descriptor coalescing. This register must be initialized by the Host. Tis no simple recommendation that can be given for this register. The factors that affect thisregister’s setting are the speed of the processor, the upper layers of the stack, and the interprocessing time.

2.1.1.4.10.6 NIC TracingThe NIC tracing register is a bit field that controls what runtime tracing is enabled.

The meanings of the various bits are:

NOTE: The one microsecond clock tick referenced above is a nominal time and the actualhardware may not provide granularity to this level. For example, on Tigon 2 (Revision 6) cardswith release 12.0 the clock granularity is 5 microseconds.

NOTE: The production code has the tracing disabled for performance reasons, so the NIC TPointer, the NIC Trace Start, and the NIC Trace Length fields are invalid. A version of thefirmware with tracing enabled is available in the Open Driver Kit.

Table 19. NIC Tracing definitions


0x00000001 TRACE_TYPE_SEND Enable all send related level 1 tracing.

0x00000002 TRACE_TYPE_RECV Enable all recv related level 1 tracing.

0x00000004 TRACE_TYPE_DMA Enable all DMA related level 1 tracing.

0x00000008 TRACE_TYPE_EVENT Enable all event generation related level 1 tracing.

0x00000010 TRACE_TYPE_COMMAND Enable all command processing related level 1 tracing.

0x00000020 TRACE_TYPE_MAC Enable all MAC related level 1 tracing.

0x00000040 TRACE_TYPE_STATS Enable all statistics related level 1 tracing.

0x00000080 TRACE_TYPE_TIMER Enable all timer related level 1 tracing.

0x00000100 TRACE_TYPE_DISP Enable all dispatcher related level 1 tracing.

0x00000200 TRACE_TYPE_MAILBOX Enable all mailbox related level 1 tracing.



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2.1.1.4.10.7 Gigabit Link NegotiationThe following table indicates the possible bit selection for the Link Negotiation parameter. Ymust set LNK_1000MB and LINK_FULL_DUPLEX for the SX fiber NIC.LNK_TX_FLOW_CTL_Y is only available on Tigon 2 ASICs. A normal setting for linknegotiation enabled and receive flow control packets would be LNK_1000MB |LNK_FULL_DUPLEX | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE |LNK_ENABLE.

Autosense (1000 SX only) is enabled if the LNK_NEGOTIATE bit is set. Autosense allows tNIC to automatically detect the way the connected hardware is attempting to bring up the linkact accordingly. Disabling LNK_NEGOTIATE disables autosensing as well. If the NIC was inautosense mode and brought the link up without link negotiation the LNK_SENSE_NO_NEGis set.

The copper PHY NIC uses only this register for link negotiation settings. In this case you maany of the speeds (LNK_10MB, LNK_100MB, LNK_1000MB) or either duplex setting(LNK_FULL_DUPLEX, LNK_HALF_DUPLEX). If you have LNK_NEGOTIATE the link willbe negotiated with the highest common speeds and duplex you have set. If you do not specLNK_NEGOTIATE set then you must specify only one of the speeds or duplex settings on bends, and the PHY will be set that way except LNK_1000MB. The 1000 speed innon-autonegotiation mode is not allowed, the 100 full duplex mode is selected to avoid no lisituation. External loopback is the new function added for TX, and it is only supported in TXrun test in loopback mode, select only one speed and duplex In some loopback cases (10/1speed), there is no link up event, simply wait for a while (2 seconds), and start sending data

0x00000400 TRACE_TYPE_RECV_BD Enable all receive buffer descriptor level 1 tracing.

0x00000800 TRACE_TYPE_LNK_PHY Enable all Physical Layer of Link bringup level 1 tracing.

0x00001000 TRACE_TYPE_LNK_NEG Enable all Link Negotiation level 1 tracing.

0x10000000 TRACE_LEVEL_1 Enable all level 1 tracing.

0x20000000 TRACE_LEVEL_2 Enable level 2 (data) tracing.

Table 20. Link Negotiation Bit Definitions


0x00001000 LNK_EXT_LOOPBACK Set this link into external loopback(TX only)

0x00002000 LNK_SENSE_NO_NEG Link brought up without link negotiation (read only)

0x00004000 LNK_LOOPBACK Set this link into loopback.

0x00008000 LNK_PREF This link is preferred. May be set in only one of

0x00010000 LNK_10MB 10 megabit data rate



0x00080000 LNK_FULL_DUPLEX set full duplex

0x00100000 LNK_HALF_DUPLEX set half duplex

0x00200000 LNK_TX_FLOW_CTL_Y emit flow control packets (Tigon 2 only)

0x00800000 LNK_RX_FLOW_CTL_Y obey received flow control packets

0x20000000 LNK_NEGOTIATE enable autonegotiation with autosensing

Table 19. NIC Tracing definitions (continued)




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2.1.1.4.10.8 10/100 Link NegotiationThe following table indicates the possible bit selection for the Link Negotiation parameter. Ycan either have the system autonegotiate the link speed or not by setting the LNK_NEGOTIbit. If this bit is set then it will autonegotiate depending on which of the LNK_10MB,LNK_100MB, LNK_FULL_DUPLEX, and LNK_HALF_DUPLEX bits you have set. That is youcan limit the range of the negotiation by only setting some of these bits or you can allow anycombination of these bits by setting them all. To hard code a speed or duplex setting just sefield appropriately without setting the LNK_NEGOTIATE bit.

LNK_TX_FLOW_CTL_Y is only available on Tigon 2 ASICs. Flow control will follow exactlythe bit settings specified (as long as the link is in full duplex mode). That is, there is no negotiaof flow control on 10/100 links. A normal setting for link negotiation enabled, allowing any speand duplex setting would be LNK_100MB | LNK_10_MB | LNK_FULL_DUPLEX |LNK_HALF_DUPLEX | LNK_NEGOTIATE | LNK_ENABLE.

2.1.1.4.11 NIC Trace PointerThe NIC Trace Pointer register contains a pointer to the current entry in the NIC trace buffeNIC memory space. This register is initialized to the beginning of the NIC trace buffer by the Nduring initialization and is updated by the NIC as the trace buffer is used.

2.1.1.4.12 NIC Trace StartThe NIC Trace Start register contains a pointer to the start of the NIC trace buffer in NIC memspace.

0x40000000 LNK_ENABLE enable link



0x00004000 LNK_LOOPBACK Set this link into loopback.

0x00008000 LNK_PREF This link is preferred. May be set in only one of




0x00080000 LNK_FULL_DUPLEX set full duplex

0x00100000 LNK_HALF_DUPLEX set half duplex

0x00200000 LNK_TX_FLOW_CTL_Y emit flow control packets (Tigon 2 only)

0x00800000 LNK_RX_FLOW_CTL_Y obey received flow control packets

0x20000000 LNK_NEGOTIATE enable autonegotiation (See the proposed 802.3zspecification)

0x40000000 LNK_ENABLE enable link

NOTE: Tracing is compiled out in operational firmware, so the NIC Trace Pointer, the NIC TraStart, and the NIC Trace Length fields are invalid. A version of the firmware with tracing enabis included in the Open Driver Kit.





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2.1.1.4.13 NIC Trace LengthThe NIC Trace Length register contains the total length (in bytes) of the NIC Trace buffer inmemory space.

2.1.1.4.14 ifIndexifIndex is the Interface Index number assigned to this interface by the Host. This variable isinitialized by the Host and the NIC firmware copies this into its stats area that is then DMAethe Host. As per RFC-1213, this is a unique value, greater than zero.

2.1.1.4.15 ifMtuifMtu specifies the size of the largest packet which will be sent/ received on this interface, spein octets. This value is initialized by the Host (and currently is never changed). The NIC firmwcopies this into its stats area which is then DMAed to the Host. The value may not exceed 9Jumbo Frames are enabled. It may not exceed 1518 if Jumbo Frames are not enabled.

This value should be set to the size of the largest Ethernet frame that you want to receive minCRC. The NIC uses this value to filter incoming frames as “too large”. If a frame is received thlarger than the ifMtu value it will be discarded and the dot3StatsFrameTooLongs counter wiincremented.

2.1.1.4.16 Mask InterruptsThis register acts similar to Mailbox 0. If it is non-zero, no interrupts will be generated. Thedifference is that it does not deassert the interrupt line, which touching Mailbox 0 will do. Thfeature is useful for operating systems that require the ability to mask interrupts at the chip. Tonly necessary on the original Tigon ASIC. On Tigon 2 ASICs (of Revision 6) you should useMask Interrupt Bit in the Miscellaneous Host Control Register (See “Tigon Miscellaneous HoControl Register”, section 2.1.1.2.1). If using the hardware bit please ensure that the MaskInterrupts Register is 0 because the firmware still honors it.

2.1.1.4.17 Gigabit Link StateThis register is valid after a Link State Event has been received. It uses the same set of bitsGigabit Link Negotiation field (See “Gigabit Link Negotiation”, section 2.1.1.4.10.7). This fielindicates how the Gigabit Link State was negotiated. If the Link is down (according to the laLink State Event) this register is invalid. This is a read-only register. For 10/100/1000 BaseT, ilink speed is 1000, this register is updated to indicates the link state, otherwise 10/100 LinkRegister is updated.

2.1.1.4.18 10/100 Link StateThis register is valid after a Link State Event has been received. It uses the same set of bits10/100 Link Negotiation field (See “10/100 Link Negotiation”, section 2.1.1.4.10.8). This fieldindicates how the 10/100 Link State was negotiated. If the Link is down (according to the latLink State Event) this register is invalid. This is a read-only register.

2.1.1.4.19 Receive Return Consumer Index (OBSOLETE on Tigon 2)The Receive Return Consumer Index register contains the index of the next Receive BD in Receive Return Ring that will be consumed. The Host writes this register whenever a BD isconsumed from the Receiver Return Ring. This register must be initialized to 0. Because it iimpossible for the NIC to overrun this ring, this value is now ignored on Tigon 2. It is still requiron Tigon 1.



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Base

ing.

nters

2.1.1.4.20 Command RingThe Command Ring is the 64 word Command Ring. (See “Command Ring”, section 2.4.1.1

2.1.1.5 Local Memory WindowThe Local Memory Window is a 2Kbyte region which provides the ability for the host to map aTigon local memory region into the Shared Memory region.

This window is accessed by setting the Window Base Address register. (See “Tigon WindowAddress Register”, section 2.1.1.2.5.)

The Host uses this window to download the firmware into the NIC and to update the Send R(See “Send Ring”, section 2.4.2.1)

2.1.2 General Information BlockThe general information block lives in Host memory and contains the statistics area and thecontrol blocks for the shared ring structures. The NIC DMAs this block from the Host duringfirmware initialization.

2.1.2.1 StatisticsThe statistics are maintained by the NIC and transferred to Host memory on demand. All couare cleared when a NIC reset occurs, or when a CLEAR_STATS command is received.

All statistics are four bytes long unless specified differently.

2.1.2.1.1 MAC StatisticsMIB Statistics, taken from RFC 1643, Ethernet-like MIB [7].

dot3StatsAlignmentErrors

dot3StatsFCSErrors

dot3StatsSingleCollisionFrames

dot3StatsMultipleCollisionFrames

Table 22. General Information Block

General Information Block Offset

Statistics 0x000 - 0x3FF

Event Ring Control Block 0x400 - 0x40F

Command Ring Control Block 0x410 - 0x41F

Send Ring Control Block 0x420 - 0x42F

Receive Standard Ring Control Block 0x430 - 0x43F

Receive Jumbo Ring Control Block 0x440 - 0x44F

Receive Mini Ring Control Block 0x450 - 0x45F

Receive Return Ring Control Block 0x460 - 0x46F

Event Producer Pointer 0x470 - 0x477

Receive Return Ring Producer Pointer 0x478 - 0x47F

Send Consumer Pointer 0x480 - 0x487

Refresh Stats Pointer 0x488 - 0x48F



dot3StatsSQETestErrors

dot3StatsDeferredTransmissions

dot3StatsLateCollisions

dot3StatsExcessiveCollisions

dot3StatsInternalMacTransmitErrors

dot3StatsCarrierSenseErrors

dot3StatsFrameTooLongs

dot3StatsInternalMacReceiveErrors

2.1.2.1.2 Interface StatisticsMIB Statistics, taken from RFC 1213 and RFC 1573, MIB-II [8, 9], interfaces group.

ifIndex

ifType

ifMtu

ifSpeed

ifAdminStatus

ifOperStatus

ifLastChange

ifInDiscards

ifInErrors

ifInUnknownProtos

ifOutDiscards

ifOutErrors

ifOutQLen

ifPhysAddress (8 bytes)

ifDescr (32 bytes)

ifHCInOctets (8 bytes)

ifHCInUcastPkts (8 bytes)

ifHCInMulticastPkts (8 bytes)

ifHCInBroadcastPkts (8 bytes)

ifHCOutOctets (8 bytes)

ifHCOutUcastPkts (8 bytes)

ifHCOutMulticastPkts (8 bytes)

ifHCOutBroadcastPkts (8 bytes)

ifLinkUpDownTrapEnable

ifHighSpeed

ifPromiscuousMode

ifConnectorPresent



er

s

L

2.1.2.1.3 Alteon Networks Proprietary MIB Statistics for the NIC

2.1.2.1.3.1 Host Commands StatisticsnicCmdsSetHostState - Number of TG_CMD_HOST_STATE commands

received. For the current and following commands, Refto section 3.2 for the command descriptions.

nicCmdsFDRFiltering - Number of TG_CMD_FDR_FILTERING commandsreceived

nicCmdsSetRecvProdIndex - Number ofTG_CMD_SET_RECV_PRODUCER_INDEXcommands received

nicCmdsUpdateGencommStats - Number of TG_CMD_UPDATE_GENCOM_STATScommands received

nicCmdsResetJumboRing - Number of TG_CMD_RESET_JUMBO_RINGcommands received

nicCmdsAddMCastAddr - Number of TG_CMD_ADD_MULTICAST_ADDRcommands received

nicCmdsDelMCastAddr - Number of TG_CMD_DEL_MULTICAST_ADDRcommands received

nicCmdsSetPromiscMode - Number of TG_CMD_SET_PROMISCUOUS_MODEcommands received

nicCmdsLinkNegotiate - Number of TG_CMD_LINK_NEGOTIATIONcommands received

nicCmdsSetMACAddr - Number of TG_CMD_SET_MAC_ADDR commandsreceived

nicCmdsClearProfilee - Number of TG_CMD_CLEAR_PROFILE commandsreceived

nicCmdsSetMulticastMode - Number of TG_CMD_SET_MULTICAST_MODEcommands received

nicCmdsClearStats - Number of TG_CMD_CLEAR_STATS commandsreceived

nicCmdsSetRecvJumboProdIndex - Number ofTG_CMD_SET_RECV_JUMBO_PRODUCER_INDEXcommands received

nicCmdsSetRecvMiniProdIndex - Number ofTG_CMD_SET_RECV_MINI_PRODUCER_INDEXcommands received

nicCmdsRefreshStats - Number of TG_CMD_REFRESH_STATS commandreceived

nicCmdsUnknown - Number of unknown or illegal commands received

2.1.2.1.3.2 NIC Events StatisticsnicEventsNICFirmwareOperational- Number of TG_EVENT_FIRMWARE_OPERATIONA

events generated.

nicEventsStatsUpdated - Number of TG_EVENT_STATS_UPDATED eventsgenerated.



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ated

s

hit

r

hit.

is

nicEventsLinkStateChanged - Number of TG_EVENT_LINK_STATE_CHANGEDevents generated.

nicEventsError - Number of TG_EVENT_ERROR events generated

nicEventsMCastListUpdated - Number ofTG_EVENT_MULTICAST_LIST_UPDATED eventsgenerated.

nicEventsResetJumboRing - Number of TG_EVENT_RESET_JUMBO_RINGcommands received.

2.1.2.1.3.3 NIC Ring Manipulation StatisticsnicRingSetSendProdIndex - Number of times the NIC has seen updates to the S

Producer Index (See “Send Consumer Pointer”, sectio2.1.2.5)

nicRingSetSendConsIndex - Number of times the send consumer index was upd

nicRingSetRecvReturnProdIndex - Number of times the recv return producer index waupdated

2.1.2.1.3.4 Host InterruptsnicInterrupts - Number of interrupts generated by NIC

nicAvoidedInterrupts - Number of interrupts avoided by NIC

2.1.2.1.3.5 NIC BD Coalescing Thresholdsnic Event Threshold Hit - Number of times Event Max Coalesce BD Threshold

nicSendThreshholdHit - Number of times either BD_FLAG_COAL_NOW orSend Max Coalesce BD Threshold hit.When these twoconditions meet, the firmware sends updated consumeindex to the host.

nicRecvThreshholdHit - Number of times Recv Max Coalesce BD Threshold When this happens, the firmware updates the ReceiveReturn Producer Index in the host.

2.1.2.1.3.6 DMA AttentionsnicDmaRdOverrun - Number of times DMA read overrun error occurred. Th

DMA error and following DMA errors are detected andreported by hardware. This error indicates that DMAFIFO data is overwritten by the new data from DMAread. If this counter is non-zero it indicates a seriouserror.

nicDmaRdUnderrun - Number of times DMA read underrun error occurred.This error indicates that DMA read engine is trying toread from an empty DMA FIFO. If this counter isnon-zero it indicates a serious error.

nicDmaWrOverrun - Number of times DMA write overrun error occurred.This error indicates that DMA FIFO data is overwrittenby the new data from DMA write. If this counter isnon-zero it indicates a serious error.



s

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an

.

torhe

nicDmaWrUnderrun - Number of times DMA write underrun error occurred.This error indicates that DMA write is ring to retrievedata from an empty DMA FIFO. If this counter isnon-zero it indicates a serious error.

nicDmaRdMasterAborts - Number of times DMA read Master Abort erroroccurred. Possible cause is hardware failure or a badaddress given to the NIC by the host driver

nicDmaWrMasterAborts - Number of times DMA write master Abort erroroccurred. Possible cause is hardware failure or a badaddress given to the NIC by the host driver

2.1.2.1.3.7 Ring/ Miscellaneous ResourcesnicDmaWriteRingFull - Number of times DMA write ring was full. The NIC

firmware was unable to queue the data being sent fromthe NIC to the host in the DMA write ring. This indicatesdata moving to the host is slower than write requestsgenerated by the NIC, typically due to a slow PCI bus/bridge chip

nicDmaReadRingFull - Number of times DMA read ring was full. The NICfirmware was unable to queue the data being sent fromthe host to the NIC in the DMA read ring. This indicatedata moving to NIC is slower than read requestsgenerated by the NIC, typically due to a slow PCI bus/bridge chip but sometimes due to a very large burst ofdata from the host.

nicEventRingFull - Number of times NIC Event ring was full. This indicateevents are being generated faster than they are proce

nicEventProducerRingFull - Number of times the DMA write ring was full trying toplace either the DMA event or event producer to host.This indicates events are generated faster than they cbe processed.

nicTxMacDescrRingFull - Number of times MAC TX Descriptor ring was full.Possible cause is not enough TX buffer space

nicOutOfTxBufSpaceFrameRetry - Number of times TX buffer space was full. Possiblecause is not enough TX buffer space

nicNoMoreWrDMADescriptors - Number of times NIC ran out of DMA write DescriptorsThis indicates the DMA can not keep up with writerequests. This is accompanied by anicDmaWriteRingFull.

nicNoMoreRxBDs - Number of times NIC ran out of the Recv BufferDescriptors. This indicates that the host is notreplenishing empty receive BDs quickly enough

nicNoSpaceInReturnRing - Number of times NIC could not place a buffer descripin the return ring because it was full. Possible cause is thost is too slow in processing packets.

nicSendBDs - Number of Send Buffer Descriptors current beinghandled in the NIC (host based send rings only)



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nicRecvBDs - Number of Standard Receive Buffer Descriptorsavailable to the NIC.

nicJumboRecvBDs - Number of Jumbo Receive Buffer Descriptors availabto the NIC.

nicMiniRecvBDs - Number of Mini Receive Buffer Descriptors available tthe NIC (valid in Tigon 2 only).

nicTotalRecvBDs - Total number of Receive Buffer Descriptors available the NIC.

nicTotalSendBDs - obsolete counter

nicJumboSpillOver - Number of times a Jumbo frame was split into multipstandard BDs.

nicSbusHangCleared - Number of times an SBus DMA bug was worked aro

nicEnqEventDelayed - Number of times posting an event was delayed.

2.1.2.1.3.8 Internal MAC RX StatisticsnicMacRxLateColls - Packets dropped due to late collisions. This error doe

not happen at Gigabit speed as the NIC operates in fuduplex mode.

nicMacRxLinkLostDuringPkt - Packets dropped because of loss of link. Possible caare cable disconnected, broken cable, NIC hardwarefailure, or the link partner hardware failure.

nicMacRxPhyDecodeError - Packets dropped because of PHY decode errors. Pocause is hardware failure which generates too much nosuch that the PHY can not recognize the signal. Anothpossible cause is hardware failure.

nicMacRxMacAbort - Packets aborted by MAC because of remote errors.Possible causes are receiving a packet smaller thanminimal size (64 bytes), a PHY decode error (see abova collision was detected during receipt, or an erroroccurred during gigabit half duplex frame extension.

nicMacTruncNoResources - Number of times a frame was dropped due to lack ofinternal resources (e.g. memory space or MACdescriptors). This is usually because the bus is too sloIncrease RX buffer ratio, live with it, or invoke flowcontrol.

nicMacRxDropUla - Unicast Packets dropped; this is caused by anonmatching unicast address. This happens regularly full duplex repeaters or during switch flooding.

nicMacRxDropMcast - Multicast Packets dropped; destination address in thereceived packet doesn’t match the Multicast address liThis is normal for multicast packets for groups not set uby the host.

nicMacRxFlowControl - Number of Flow Control packets received.

nicMacRxDropSpace - Packets dropped because of lack of space. This is usbecause the bus is too slow. Increase RX buffer ratio, livwith it, or invoke flow control.



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nicMaxRxColls - Total number of packets dropped because of collisionThis is caused by two nodes sending messagessimultaneously. This error does not happen at Gigabitspeeds as the NIC is operating in full duplex mode.

nicMacRxTotalAttentions - Total number of Mac Rx Attentions, e.g. ReceiveDescriptor Attention, Receive Buffer Attention, FlowControl XON Sent, Flow Control XOFF Sent, and FIFOoverrun.

nicMacRxLinkAttentions - Total number of link state change Attentions, e.g.Auto-Negotiation changed, Link State Error, and LinkReady Changed.

nicMacRxSyncAttentions - Total number of Sync lost Attentions.

nicMacRxConfigAttentions - Total number of Link Config Attentions. Possible cauare the link partner changing its link configuration. Undenormal situation, this attention does not indicatehardware failure, only when this number is greater thathe number of times link partner configuration changed

nicMacReset - Total number of times MAC was reset. This is causedlink lost and trying to re-establish the link.

nicMacRxBufDescrAttns - Obsolete

nicMacRxBufAttns - Total number of Receive Buffer Descriptor Attentions.This attention is triggered by received buffer descriptorreaches a predefined threshold. This happens when threceive buffer fills either due to a slow host or a badframe that has to be manually removed by the firmwar

nicMacRxZeroFrameCleanup - Number of times Received Buffer got cleaned up whthe Receive Buffer is full and the frame received count0. This indicates the data in the receive buffer is allgarbage. This could happen if the remote part keptsending errored frames.

nicMacRxOneFrameCleanup - Number of times Received Buffer got cleaned up whthe Receive Buffer is full and the frame received count1. This could happen if the remote part kept sendingerrored frames.

nicMacRxMultipleFrameCleanup - Number of times Received Buffer got cleaned up whthe Receive Buffer is full and the frame received countmore than one. This could happen if the remote part kesending errored frames.

nicMacRxTimerCleanup - Number of times setting up a timer to wait for ReceivBuffer space to be freed up when the Receive Buffer isfull. This could happen if the remote part kept sendingerrored frames.

nicMacRxDmaCleanup - Total Number of times DMA Buffer got cleaned up whthe Receive Buffer is full. This could happen if theremote part kept sending errored frames.

2.1.2.1.3.9 Internal MAC TX StatisticsnicMacTxCollision[1] - Tx collision histogram



ated

dressce (in

t is still

s set.

nicMacTxCollision[2]














nicMacTxTotalAttentions - Total number of Tx Attentions

nicProfile[32] - NIC profiling is not enabled, ignore these statistics

2.1.2.2 Ring Control BlocksEach shared ring (See “Shared Rings”, section 2.4) has a Ring Control Block (RCB) associwith it. An RCB has the following format.

Figure 2. Ring Control Block

The ring address is the Host address of the first ring element. The ring address is in Host adformat (See “Host Addresses”, section 1.3.1). Two of the rings have addresses in the NIC spaparticular, the Command and Send Rings). The address in this case is a NIC address, but iin Host address format (See Figure 1).

Flags contains the flag bits for Send and Receive Rings. The feature is active when the bit i

Table 23. RCB Flags


0x00000001 RCB_FLAG_TCP_UDP_CKSUM Perform TCP or UDP checksum calculations.

0x00000002 RCB_FLAG_IP_CKSUM Perform IP checksum calculations.

31 15 00x00

0x04

0x08

0x0c

ring address

max_len

0

flags



end

r

ced

ring.

e

ks.

d/or

The Send Ring RCB uses the max_len field to determine the total number of entries in the sring (see extended Send Ring Handling below).

The Receive Standard Ring RCB uses the max_len field to indicate the length of each buffeplaced into the standard ring. This way any frame received that is larger than this value willattempt to use a jumbo ring buffer instead of a standard ring buffer.

The Receive Mini Ring RCB uses the max_len field to indicate the length of each buffer plainto the mini ring. This way any frame received that is less than or equal to this value will beplaced in the mini ring if buffer descriptors are available.

The Receive Return Ring RCB uses the max_len field to indicate the number of entries in theThe only valid sizes are 2048, 1024, and 0 (which is equivalent to 2048 for backwardcompatibility). For 1024 to be a valid size the Receive Mini Ring RCB flag field must have thRCB_FLAG_RING_DISABLED bit set. If an invalid size is set the NIC will halt with an errorduring initialization.

The max_len field is unused in the Event, Command, and Receive Jumbo Ring Control Bloc

0x00000008 RCB_FLAG_NO_PSEUDO_HDR_CKSUM Do not include the pseudo header in TCP orUDP checksum calculations (Only valid ifRCB_FLAG_TCP_UDP_CKSUM flag is set).In order to get the correct checksum the drivermust seed the TCP/UDP checksum field withthe pseudo header’s checksum.

0x00000010 RCB_FLAG_VLAN_ASSIST Enable VLAN tagging insertion or deletion.

0x00000020 RCB_FLAG_COAL_UPDATE_ONLY When this bit is set the NIC will only generateinterrupts for transmit completions when theSend Coalesced Ticks value is exceeded.Send Consumer updates are still made basedon the Send Max Coalesced BDs and theBD_FLAG_COAL_NOW.

0x00000040 RCB_FLAG_HOST_RING For Send RCB only. Indicates the send ring islocated in host memory, not in NIC memory.The ring address is a bus virtual or physicaladdress in the host.

0x00000080 RCB_FLAG_IEEE_SNAP_CKSUM NIC will parse 802.3 SNAP frames and dochecksum offload on them

0x00000100 RCB_FLAG_USE_EXT_RECV_BD For Jumbo Recv RCB only. Indicates that theJumbo Recv Ring will use extended receivebuffer descriptors.(See Figure 11.)

0x00000200 RCB_FLAG_RING_DISABLED For Jumbo Recv or Mini Recv RCB only.Indicates Ring will never be used. If a Jumboor Mini Ring mailbox is updated (or theequivalent command is sent) the NIC will halt.

NOTE: In order to use the checksum offload feature, the RCB_FLAG_TCP_UDP_CKSUM anthe RCB_FLAG_IP_CKSUM bit must be set prior to starting the firmware.

Table 23. RCB Flags




lacestbytes may

thenter is byte areHost.

lacesst

bytes may

2.1.2.3 Event Producer PointerThe Event Producer Pointer is a Host Address which points to the location where the NIC pthe Event Producer Index. The Event Producer Pointer is in Host address format (See “HosAddresses”, section 1.3.1) and points to an aligned eight byte region where only the first fourcontain relevant information. The remaining four bytes are not explicitly set to zero, i.e. theycontain an unknown value and must be ignored by the Host.

Figure 3. Event Producer

2.1.2.4 Receive Return Ring Producer PointerReceive Return Ring Producer Pointer is a Host Address which points to the location whereNIC places the Receive Return Ring Producer Index. The Receive Return Ring Producer Poiin Host address format (See “Host Addresses”, section 1.3.1) and points to an aligned eightregion where only the first four bytes contain relevant information. The remaining four bytesnot explicitly set to zero, i.e. they may contain an unknown value and must be ignored by the

Figure 4. Receive Return Ring Producer

2.1.2.5 Send Consumer PointerThe Send Consumer Pointer is a Host Address which points to the location where the NIC pthe Send Consumer Index. The Send Consumer Pointer is in Host address format (See “HoAddresses”, section 1.3.1) and points to an aligned eight byte region where only the first fourcontain relevant information. The remaining four bytes are not explicitly set to zero, i.e. theycontain an unknown value and must be ignored by the Host.

Figure 5. Send Consumer

31 15 00x00

0x04 Event Producer Index

Not Used (Unspecified Contents)

31 15 00x00

0x04 Receive Return Ring ProducerIndex


31 15 00x00

0x04Send Consumer Index




f

ystem

tionr is inntical

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d at

llowe byuse.

2.1.2.6 Refresh Stats PointerThe Refresh Stats Pointer is a Host Address which points to the location where a new set ostatistics can be placed which can then be loaded into the NIC. This is useful if your systemsupports a hot swap capability on its bus. This way a new NIC card can be placed into the sand, with proper driver support, new statistics can be updated with theTG_CMD_REFRESH_STATS command to allow this card to transparently take over the funcof a failed card, even to the point that the statistics are consistent. The Refresh Stats PointeHost address format (See “Host Addresses”, section 1.3.1) and points to a region which is idein structure to the statistics region (See “Statistics”, section 2.1.2.1)

2.2 SBus Memory Model

The SBus uses a single linear address space. Different sections of the address space are uaccess different sections of the SBus card and the Tigon ASIC.

2.3 Serial EEPROM

The serial EEPROM contains manufacturing information and initialization code as describedChapter 5 of this document.

2.3.1 Reading and Writing the Serial EEPROMTo read or write the serial EEPROM requires a fairly complex algorithm. It is stronglyrecommended that you port the code from the sample driver. If you choose to rewrite this codserial EEPROM is an I2C device. In particular, it is an Atmel AT24C64 device. The device addreused is 010000[R/W] (binary). For read set the R/W bit to 1, for write set the R/W bit to 0.

2.3.2 Data fields in the Serial EEPROM

2.3.2.1 MAC AddressThe MAC address is an 8 byte field with the bottom 6 bytes being the actual Ethernet MACaddress. The top two bytes are 0 (See “MAC Addresses”, section 1.3.3). This field is locateoffset 0x8c in the Serial EEPROM.

2.3.2.2 Software KeyThere is a software key field in the EEPROM that allows the driver firmware to allow or disafeatures depending on the values in these fields. The first character of this 16 byte field is thsoftware vendor identifier. Your driver should check this value against the value given to youAlteon Networks so that your customers don’t buy cards from other sources and attempt to them with your driver. The software key field is located at offset 0x94 in the Serial EEPROM

Table 24. SBus Address Space

Address Range Access Region

0x00000000 - 0x0000FFFF Byte R/O FCode PROM

0x00010000 - 0x0001003C 32-bit R/W PCI Configuration Region

0x00010040 - 0x0001FFFF N/A Undefined Region

0x00020000 - 0x00023FFF 32-bit R/W Shared Memory Region

0x00024000 - 0xFFFFFFFF N/A Undefined Region



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holdsared

2.3.2.3 Customer Data AreaThere is a 32 byte free form region that the customer can use for any purpose they want. Thregion is from offset 0xd4 - 0xf3.

2.4 Shared Rings

The Host and the NIC use a series of shared rings to communicate with each other. While ering itself is shared, there are two indices that control the operation of each ring which are nshared. These are the producer index and the consumer index. The producer adds elemenring and increments the producer index while the consumer removes elements from the ringincrements the consumer index. When the producer and consumer indices are equal, the riempty. When the producer is one “behind” the consumer, the ring is full.

Figure 6. Producer-Consumer model

2.4.1 Control RingsControl rings contain their entire information in the ring element. There are two control ringsCommand Ring and the Event Ring.

2.4.1.1 Command RingThe Command Ring holds commands from the Host intended for the NIC. The Host controlCommand Ring producer and the NIC controls the Command Ring consumer. The ring elemfor the Command Ring is a command (See “Commands”, section 3.2). The Command Ring64 command elements and lives in shared memory. The Command Producer lives in the shmemory and is a mailbox. The Command Consumer also lives in shared memory.

descriptor

descriptor

descriptor

descriptor

descriptor

descriptor

producer

consumer

descriptors waiting tobe consumed



ing is hostointer

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nd

ocal

was

ould that

2.4.1.2 Event RingThe Event Ring holds responses from the NIC to the Host. The NIC controls the Event Ringproducer and the Host controls the Event Ring consumer. The ring element for the Event Ran event (See “Events”, section 3.3). The Event Ring holds 256 event elements and lives inmemory. The producer also lives in host memory and is pointed to by the Event Producer P(See “Event Producer Pointer”, section 2.1.2.3). The consumer lives in shared memory.

When the Event Ring is full, the NIC stops generating events until space is available.

2.4.2 Data RingsData rings contain some information about the data in the ring element and a pointer to the data buffer. There are two sets of data rings, a single Send Ring and set of Receive Rings. Thelement for all data rings is the buffer descriptor (See “Buffer Descriptors”, section 3.1).

Figure 7. Producer-Consumer Model with data

2.4.2.1 Send RingThe Send Ring is used to transfer data from the Host to the NIC for transmission onto the netThe Host is the Send Ring producer and the NIC is the Send Ring consumer. The Send Ringa variable number of buffer descriptors (See “Extended Send Ring Handling”, section 2.4.2.

This ring lives in NIC memory. The location of this ring, in NIC memory, is indicated by the SeRing RCB (See figure 2 on page 41). There are limitations on this value as indicated in theExtended Send Ring Handling section below. The Host writes to the Send Ring by using the LMemory Window (See “Local Memory Window”, section 2.1.1.5)

2.4.2.2 Extended Send Ring HandlingPrior to version 10.2 of this API document, the Send ring was at a fixed location (0x3800) andof a fixed length (128 entries). This fixed approach was taken to simplify the operation of theTigon base window register. The ring fit perfectly into the 2k region of the ring and the base cbe set once to 0x3800 and left alone. Unfortunately, some situations occurred that indicated

descriptor

descriptor

descriptor

descriptor

descriptor

descriptor

producer

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this ring size could be too small. To alleviate this, the ring size can now be specified in the maxfield of the Send RCB. The ring size can be any of three values, 128, 256, or 512 with respestarting addresses of 0x3800, 0x3000, and 0x2000. The ring fits into NIC memory between locations 0x2000 and 0x3fff and always ends at 0x3fff. It is up to the driver to manipulate theTigon Window base register in such a way that the Window is pointing into the proper sectiothe ring when writing Send Buffer Descriptors.

2.4.2.3 Receive RingsA set of Receive Rings are used to transfer data that has been received from the network frNIC to the Host. There are three rings into which the Host places BDs that point to empty bufand one ring that the NIC uses to place BDs that point to filled buffers. Three rings are usedallow for different sized data buffers. One ring, the Standard Ring, uses traditional (for Ethe1514 byte buffers. Another ring, the Jumbo Ring, uses extended 9014 byte buffers. The lastthe Mini Ring, uses small buffers whose maximum length can be specified in the max_len fieits Ring Control Block. On Tigon 2 products the Standard Ring contains 512 entries, the JumRing contains 256 entries, the optional Mini Ring contains 1024 entries and the Return Ringcontains either 1024 or 2048 entries, depending on whether the Mini Receive Ring is enablthe value placed in the max_len field of the Receive Return Ring’s RCB. The Mini Receive Rinonly supported on Tigon 2 products. On Tigon 1 products the Standard Ring contains 512 ethe Jumbo Ring contains 256 entries, and the Return Ring contains 2048 entries.

The Host writes the Receive Buffer Descriptors, pointing to empty buffers, into the ReceiveStandard Ring and Receive Jumbo Ring and hands them off to the NIC (via theTG_CMD_SET_RECV_PRODUCER_INDEX and theTG_CMD_SET_RECV_JUMBO_PRODUCER_INDEX commands). When the NIC fills thebuffers associated with these Buffer Descriptors, it returns them back to the Host in the RecReturn Ring. The Host determines which buffer descriptor was used by looking at the flag bindicate the Standard or Jumbo Ring) and index. (See figure 10 on page 57).

The Jumbo Ring is optional. If you do not send aTG_CMD_SET_RECV_JUMBO_PRODUCER_INDEX command (or update the Jumbo RecProducer Mailbox on Tigon 2 NICs) then the NIC will not use the Receive Jumbo Ring.

Similarly, the Rings do not need to be filled beyond the number of buffers you wish to give toNIC. If you want to trade off memory for performance, or you feel that your driver can keepbuffers available for the NIC receive engine without using all 512 Standard entries or 256 Juentries, just don’t completely fill the ring using the TG_CMD_SET_RECV_PRODUCER_INDEor TG_CMD_SET_SET_RECV_JUMBO_PRODUCER_INDEX commands (or the equivalenmailboxes on Tigon 2 NICs).

The Mini Ring is also optional. If you do not update the Mini Receive Producer Mailbox on tthe NIC will not use the Mini Receive Ring. In all cases, if the frame will not fit in a Mini Receivring or there are no Mini Receive Ring buffers available a Standard Ring buffer will be usedinstead.

Also, the Jumbo Receive Ring can be filled with Extended Receive Buffer Descriptors (SeeFigure 11) if the RCB_FLAG_USE_EXT_RECV_BD is set in the Jumbo RCB. This extendeReceive Buffer Descriptor allows the host to describe large buffers that are not contiguous. Unon-contiguous areas can be supported.



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If a large frame arrives and the NIC is out of Jumbo buffer descriptors and theDONT_FRAG_JUMBOS bit is not set in the Operating Mode register then the frame will be sinto multiple standard buffer descriptors. Unlike Standard buffers, Jumbo and Mini bufferdescriptors always contain one complete packet.

2.5 Interrupts

2.5.1 Interrupt GenerationSince interrupts to the Host are typically quite expensive, they are generated only if there isfor the Host. Any time a new event is generated by the NIC, for which the Host has not beennotified, an Interrupt is generated. However, the “Interrupt Avoidance” mechanism may choosuppress this interrupt and not post it to the Host depending upon the state of the Host (See“Interrupt Avoidance”, section 2.5.2 for further clarification).

Generation of the events can be tuned by coalescing the send and receive events.

The interrupt handler or, in the case of some OS’s, the event handling routine, in Host softwexpected to process all available events before exiting.

An interrupt may be cleared explicitly using the Miscellaneous Host Control Register (See “TMiscellaneous Host Control Register”, section 2.1.1.2.1) or implicitly by writing into Mailbox

2.5.2 Interrupt AvoidanceThe NIC will not interrupt the Host if the Host indicates that it is already processing events. Wthe Host is processing events, the NIC assumes that the Host will processall the pending eventsbefore returning from the “event processing” routine.

The NIC checks two conditions in order to determine whether the Host is presently processevents. These two conditions are:

• The Interrupt State Bit in the Tigon Miscellaneous Host Control Register.

• The Host-NIC handshake, whereby the Host explicitly indicates to the NIC that it isprocessing events and therefore does not want to take any interrupts. (See “Host In InteHandler”, section 2.1.1.3.1)

If either of the above two conditions is true, an Interrupt is not generated.

2.5.3 Masking InterruptsFor systems that need to mask interrupts at the card without changing the level of the interrupthis can be accomplished through the use of the Mask Interrupts field of the GeneralCommunications Area (See “General Communications Registers”, section Table 14.) for theoriginal Tigon ASIC or through the use of the Mask Interrupt bit of the Miscellaneous HostControl Register (See “Tigon Miscellaneous Host Control Register”, section 2.1.1.2.1) for thTigon 2 ASIC.

NOTE: The word event is used generically in this section to refer to events posted to the evering or the update of the Send Consumer or the Receive Return Ring Producer.



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2.6 Checksum Offload

2.6.1 Preparing the NIC for Checksum OffloadIn order to prepare the NIC to do checksum offload, you must set the proper bits in the sendreceive RCBs (See “Ring Control Blocks”, section 2.1.2.2). There are three bits that controlchecksum offload, RCB_FLAG_TCP_UDP_CKSUM, RCB_FLAG_IP_CKSUM, andRCB_FLAG_NO_PSEUDO_HDR_CKSUM. The first two bits indicate what checksum offloadcapabilities are enabled in the firmware. The last bit indicates the algorithm used to calculatchecksum. These bits may be set differently for send and receive. However, make sure thaenabled receive rings have the same flags set or an ERROR event will be generated.

2.6.2 Per Packet Settings When Using Checksum Offload

2.6.2.1 The Send CaseThe NIC can calculate the IP, TCP, and/or UDP checksum and insert it into the outgoing fracan even generate the checksum for IP fragmented packets. To have the NIC generate thechecksum include the appropriate bits in each buffer descriptor associated with a frame andzero or seed the checksum fields that are to be calculated.

For example, suppose that the host wants to send a packet that consists of three separate pdata but is a single TCP frame. Further suppose that you want the NIC to calculate the IP andchecksums, but you don’t want the pseudo-header included in the TCP checksum calculationplace a zero in the IP checksum field. Second, place the checksum of the pseudo-header in thchecksum field. Then generate the three buffer descriptors associated with the data. The firbuffer descriptor should set the flags BD_FLAG_TCP_UDP_CKSUM andIP_FLAG_IP_CKSUM. The last buffer descriptor should set the flagsBD_FLAG_TCP_UDP_CKSUM, BD_FLAG_IP_CKSUM, BD_FLAG_END, and (for the sendcase not running checksum offload) one of the BD_FLAG_UCAST_PKT,BD_FLAG_BCAST_PKT, or BD_FLAG_MCAST_PKT flags.

2.6.2.2 The Send Case for IP Fragmented PacketsThe NIC has the ability to calculate the TCP or UDP checksum for an IP fragmented packetof the IP fragments are placed into the send ringconsecutively and in the correct order. To usethis feature set the BD_FLAG_IP_FRAG_END bit in the very last buffer descriptor associatewith the last fragment and set the BD_FLAG_IP_FRAG bit in each of the other buffer descrip

2.6.2.3 LimitationsPrevious limitations on checksum offload (such as IP optioned packets and tagged VLAN frahave been removed. These frames will be properly checksummed.

NOTE: Do not set any capabilities that you do not wish to use. Setting extra bits changes thalgorithms used by the firmware and can increase the latency and decrease the throughputNIC.



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2.6.3 The Receive CaseThe NIC can calculate the IP, TCP, and/or UDP checksum and forward the calculation to thealong with each incoming frame. The host can use these values directly for unfragmented por can offload the checksum calculation for IP fragmented packets. That is, the TCP/UDPchecksum will include all the necessary data for unfragmented packets. For fragmented pacthe host needs to add up the TCP/UDP checksums for all the fragments to obtain the finalchecksum.

The NIC generates the checksum based on the bits set in the receive ring RCBs. It is importaall of the rings have the same bits set. If they do not, an ERROR event will be returned by theat initialization time.

The checksums calculated by the NIC are placed into the buffer descriptors in the receive rering. The TCP or UDP checksum will be calculated with the pseudo-header unless theRCB_FLAG_NO_PSEUDO_HDR_CKSUM field is placed in the receive ring RCBs.

2.7 VLAN Assist

The NIC has the ability to insert VLAN tags into transmitted frames and delete VLAN tags frreceived frames. The tags added and deleted are 802.1q compliant tags. An 802.1q compliVLAN frame means that there is an Ethertype field of 0x8100 in the Ethertype/Length field ofthe Ethernet header, there is a 16 bit VLAN tag field that is made up of 1 CNI bit, 3 priority band 12 VLAN Identification bits, and the “real” 16 bit Ethertype/Length field follows the 16 bVLAN tag field. Throughout the rest of this discussion the term “VLAN tag” is used to refer tomiddle 16 bit field.

2.7.1 Tag Insertion for Outgoing FramesTo enable tag insertion you must specify that you may use it in the send RCB. Set flagRCB_FLAG_VLAN_ASSIST.

To send a frame with a tag inserted you must specify the sixteen bit tag value in the Send BDescriptor (See “Send Buffer Descriptors”, section 3.1.2) and specify the buffer descriptor flBD_FLAG_VLAN_TAG in the first buffer descriptor of a frame.

2.7.2 Tag Deletion for Incoming FramesTo enable tag deletion you must specify that you may use it in the receive RCBs. Set flagRCB_FLAG_VLAN_ASSIST inall the receive RCBs. If the RCB_FLAG_VLAN_ASSIST flag isset differently in different RCBs an Error Event will be generated and the NIC firmware will h

When a tagged frame is received by the NIC, the NIC will set the BD_FLAG_VLAN_TAG bitthe flags field of the buffer descriptor. The actual sixteen bit tag value will be placed in theappropriate field of that buffer descriptor (See “Receive Buffer Descriptors”, section 3.1.1).



the

2.8 Transmit Flow Diagram

The following diagram shows how a single frame is sent from the Host to the NIC and onto network. For this example, the frame is described in a single buffer descriptor.

Figure 8. Transmit Flow Diagram


send producer index

1

2

7

3 4

6

5

DMA

DMA

TX Buffer

NIC Send ConsumerIndex

Kernel Buffer containing Frame

Pointer to frame

Send Ring

Send Consumer Ptr

Via Local Memory Windowor via DMA



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1. The Host creates a frame in Host memory.

2. The Host creates a buffer descriptor or series of buffer descriptors that describe the framplaces it or them in the Send Ring on the NIC, using the Local Memory Window. With anExtended Send Ring the Tigon Window Base Register may have to be adjusted to allow transfer.

If Host based send rings are specified then this step is skipped and replaced by a DMA trastarted by the NIC following step 4.

3. The Host updates the Send Producer Index, and writes it into mailbox 2 in the Shared Meregion.

4. The NIC receives an internal mailbox event informing it that the Send Producer Index hasmodified.

5. The NIC starts to DMA the frame from the Host to the transmit buffer in the NIC and enquethe frame on the MAC Transmit ring. Once the DMA of the frame is complete, the Frametransmitted onto the Network.

6. The NIC starts a DMA of the Send Consumer Index to notify the Host that the frame pointeby the buffer descriptor(s) has been consumed. The DMA goes to the address specified Send Consumer Pointer. This DMA is subject to “Send BD Coalescing”, i.e. if coalescingenabled, then the DMA may not be generated. The NIC may interrupt the host at this tim

7. If the Host was interrupted, or is already processing events or send and receive updatesthe new value of the send consumer and can now free the frame, as no further referencemade to it. This step takes place only if the DMA was generated in step 6, above, and anInterrupt was generated in step 6 above or the host was already processing events or sereceive updates.

During send processing, the Host may be interrupted, although it is not mandatory. When theis only sending frames, interrupts are caused by meeting the send BD coalescing thresholdsoon as a send consumer index is DMA’ed (in the case where no send BD coalescing is usInterrupts are also subject to Interrupt Avoidance (See “Interrupt Avoidance”, section 2.5.2)



nd

2.9 Receive Flow Diagram

The following diagram shows how a single frame is received from the network into the NIC ainto the Host. For this example, the frame fits into a single buffer descriptor.

Figure 9. Receive Flow Diagram


4

1

2

9

3

7

8

6

DMA

DMA

5

DMA

kernel buffer

Receive Return Pro-ducer

RX buffer

pointer to rx buf

nic recv ring

NIC recv returnproducer index

pointer to frame

recv return ring

DMA

jumbo recv prod idx

std recv prod index

pointer to frame

jumbo recv ring

pointer to frame

standard recv ring



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1. The Host allocates a buffer in Host memory.

2. The Host creates a buffer descriptor that describes the buffer (standard or jumbo) and plin the correct Host resident Receive Rings (Please See “Receive Rings”, section 2.4.2.3)

3. The Host updates the corresponding Ring Producer Index (“Mailboxes” on page 18).

4. The NIC receives an internal mailbox event informing him that a Receive Ring Producer Inhas been modified and starts the DMA of the new buffer descriptor from the appropriateReceive Ring to the NIC copy of that Receive Ring.

5. The DMA of the new buffer descriptor completes and the NIC now waits for a frame to arfrom the network.

6. A frame arrives from the network. The NIC immediately begins to DMA the frame into theHost buffer described by the buffer descriptor. If the frame is larger than the value specifithe max_len field of the standard ring RCB’s max_len field the NIC will use a buffer fromJumbo Ring if one is available. If a Jumbo buffer is not available or the packet is of less tmax_len size the NIC will use one or more buffers described in the Standard Ring.

7. When the reception of the frame completes, the NIC updates the length and the flags fiethe buffer descriptor in the NIC copy of the Receive Ring and starts the DMA of the buffedescriptor(s) back into the Host Receive Return Ring (Please See “Receive Rings”, secti2.4.2.3).

8. The DMA of the filled receive buffer descriptor(s) completes. The NIC starts a DMA of thReceive Return Ring Producer Index to notify the Host that the frame pointed to by the bdescriptor has been filled. The DMA goes to the address specified in the Receive ReturnProducer Pointer. This DMA is subject to the “Receive BD Coalescing”, i.e. if the coalescinenabled, this DMA may not be generated. The NIC may interrupt the host at this time.

9. If the Host was interrupted or was already processing events or send and receive updatesthe new value of the Receive Return Ring Producer Index and can now use the filled bufno further references are made to it by the NIC. This step occurs only if a DMA was generin step 11 above, and an Interrupt was generated in step 11 above, or the host was alreaprocessing events or send and receive updates.

During receive processing, the Host may be interrupted, although it is not mandatory. WhenHost is only receiving frames, interrupts are caused by meeting the receive BD coalescingthreshold or as soon as Receive Return Ring Producer Index is DMA’ed (when no receive Bcoalescing is used).

Note that the old mechanism of placing a TG_CMD_SET_RECV_PRODUCER_INDEX orTG_CMD_SET_RECV_JUMBO_PRODUCER_INDEX is still acceptable, but the new directmechanism is preferred.

2.10 Error Processing

The following classes of errors may be encountered:

• Error associated with a frame

• NIC internal error

• Host software invalid operation



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When the NIC encounters an error when receiving a frame, the frame is discarded and the staare updated.

When the NIC encounters an error in sending a frame, the frame is discarded and statisticsupdated.

When the NIC encounters invalid control information in Host memory or an internal inconsisstate the NIC halts its CPU. Host software is expected to reset the NIC.

2.11 Frame Filtering

The NIC does frame filtering based on the combination of settings of Promiscuous Mode (S“TG_CMD_SET_PROMISC_MODE”, section 3.2.10), Multicast Mode (See“TG_CMD_SET_MULTICAST_MODE”, section 3.2.14) and the specified local MAC addres(See “MAC Address”, section 2.1.1.4.1.)

If neither Promiscuous Mode nor Multicast Mode are specified the NIC will only accept andforward to the host unicast frames that are addressed directly to the MAC address specifiedhost in the MAC address field of the General Communications area, as well as broadcast frand multicast frames that have their multicast addresses added to the multicast filtering list “TG_CMD_EXT_ADD_MULTICAST_ADDR”, section 3.2.18 and See“TG_CMD_EXT_DEL_MULTICAST_ADDR”, section 3.2.19.)

In Promiscuous Mode all non-errored frames received by the NIC are forwarded to the host

In Multicast Mode all non-errored multicast frames are forwarded to the host as well as allbroadcast and correctly addressed unicast frames.




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3 Data Structures

3.1 Buffer Descriptors

Buffer descriptors are the elements of the Send and Recv rings. Individually, a buffer descridescribes an area within Host memory where data is waiting to be transmitted from or receiinto. The largest amount of data that can be referenced by a single buffer descriptor is 64K bits in length). Multiple buffer descriptors may be chained together to provide scatter/gathersingle frame. The descriptors may point to any byte boundary. The only limit to the number descriptors that describe a single Frame is the size of the Send or Receive Ring.

3.1.1 Receive Buffer DescriptorsReceive Buffer Descriptors (See figure 10 on page 57) are used for the reception of data fronetwork. There are 512 receive buffer descriptors in the Standard Receive Ring, 256 receivedescriptors in the Jumbo Receive Ring, 1024 buffer descriptors in the optional Mini Receive Rand either 1024 or 2048 buffer descriptors in the Receive Return Ring. See “Ring Control Blocsection 2.1.2.2.

Figure 10. Receive Buffer Descriptor

31 15 00x00

0x04

0x08

0x0c

0x10

0x14

Host address

index

type

ip_cksum

len

flags

tcp_udp_cksum

error_flag VLAN tag

reserved

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0x18

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Gigabit Ethernet/PCI NIC Software Definition Data Structures

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Figure 11. Extended Receive Buffer Descriptor

The Host address field contains the address of the buffer in Host memory. The Host addresHost address format (See “Host Addresses”, section 1.3.1). For the Extended Receive BuffeDescriptor this address it the first address in the list of addresses.

The Host Address n field in the Extended Receive Buffer Descriptor contains the address of thpiece of the buffer in Host memory.

The index field is used by the host to keep track of the position of the returned buffer in theStandard or Jumbo Receive Ring. The field is passed through opaquely by the NIC.

The len field is initially set by the Host and specifies the length of the buffer available for receivdata. On receive, the NIC modifies the length field to correspond with the amount of valid dathe buffer. A value of 0 indicates that there is no valid data in the buffer. For Extended ReceBuffer Descriptors this length field is the length of the data pointed to by Host address 0.

The len n field in the Extended Receive Buffer Descriptor contains the length of the nth piecthe buffer in Host memory.

The type field is used by the NIC internally and should be ignored and need not be set by the

The Flag bits are used to indicate special processing that is needed in the buffer. Bits that aexplicitly defined here must be zero. See Table 26 for details.

The ip_cksum field is the checksum of the entire IP header. A correct checksum is 0 or 0xF

0x00

0x04

0x08

0x0c

0x10

0x14

Host address 0

index

type

ip_cksum

len 0

flags

tcp_udp_cksum

error_flag VLAN tag

reserved

opaque data area

31 15 0

Host address 1

Host address 3

Host address 2

len 1

len 3

len 2

reserved

0x18

0x1c

0x20

0x24

0x28

0x2c

0x30

0x34

0x38

0x3c



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The tcp_udp_cksum field is the checksum of all data following the IP header, for the lengthdefined in the IP header. If the RCB_NO_PSEUDO_HDR_CKSUM bit is set then the pseudheader checksum is not added to this value. If the bit is set this value includes the pseudo h

The error_flag field contains a bitmask of possible errors. It is only valid if theBD_FLAGS_FRAME_HAS_ERROR bit is set in the flags field.

Table 25. Errored Frame Flags

The VLAN tag field is filled in if the BD_FLAGS_VLAN_TAG bit is set in the flags field. It is the2 byte VLAN tag that has been extracted from a 802.1q compliant frame.

The Reserved field is used internally by the Alteon NIC and does not have to be transferredbetween the NIC and the Host. The host should ignore the value of this field.

The opaque data field is reserved for the driver and any data placed here will be passed opby the driver from the receive buffer descriptor in the standard or jumbo receive ring to the recreturn ring.

3.1.2 Send Buffer DescriptorsSend Buffer Descriptors (Figure 12) are used for the transmission of data to the network. The128, 256 or 512 send buffer descriptors.

Figure 12. Send Buffer Descriptor


0x00010000 BD_ERR_BAD_CRC This frame has a bad CRC.

0x00020000 BD_ERR_COLL_DETECT This frame had a collision.

0x00040000 BD_ERR_LINK_LOST_DURING_PKT The link was lost while this, incomplete frame was beingreceived.

0x00080000 BD_ERR_PHY_DECODE_ERR The frame had an unspecified frame decoding error.

0x00100000 BD_ERR_ODD_NIBBLED_RCVD_MII The packet arrived with an odd number of nibbles.

0x00200000 BD_ERR_MAC_ABORT The MAC aborted the packet due to an unspecified internalerror.

0x00400000 BD_ERR_LEN_LT_64 The MAC received a short packet.

0x00800000 BD_ERR_TRUNC_NO_RESOURCES The MAC could not receive this entire packet due to a lack ofinternal resources.

0x01000000 BD_ERR_GIANT_FRAME_RCVD This frame was longer than the maximum packet length valueset in the ifMtu field (See “ifMtu”, section 2.1.1.4.15).

31 15 00x00

0x04

0x08

0x0c

Host address

len flags

reserved VLAN tag



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ing

The Host address field contains the address of the buffer in Host memory. A length of 0 indithat the descriptor does not have a buffer associated with it. The Host address is in Host adformat (See “Host Addresses”, section 1.3.1).

The VLAN tag field is only used when the BD_FLAG_INSERT_VLAN_TAG is set. It should set to the sixteen bit VLAN tag that should be inserted into the 802.1q compliant frame. Fortransmit this flag should only be set on the buffer descriptor that contains the Ethernet head

The Flag bits are used to indicate special processing that is needed in the buffer. Bits that aexplicitly defined and detailed in Table 26 below must be set to zero. In order to generate thcorrect statistics one of the BD_FLAG_UCAST_PKT, BD_FLAG_MCAST_PKT, orBD_FLAG_BCAST_PKT bitfields should be set in the same buffer descriptor that has theBD_FLAG_END bit set. This is only necessary if you are not running with send checksummenabled.

Table 26. Buffer Descriptor Flags


0x0001 BD_FLAG_TCP_UDP_CKSUM Generate the TCP/UDP checksum for the frame thatstarts with this descriptor and ends with the descriptorwith the BD_FLAG_FRAME_END bit set. Update theframe with the calculated checksum before transmitting it.

0x0002 BD_FLAG_IP_CKSUM Generate the IP checksum for the IP header containedwithin this descriptor. It is assumed that the entire IPheader is contained within a single descriptor.

0x0004 BD_FLAG_END The frame ends at the end of the data in this bufferdescriptor. This is set by the Host on transmit and by theNIC on recv.

0x0010 BD_FLAG_JUMBO_RING Indicates that this packet came from the Jumbo ReceiveRing, not the Standard Receive Ring (For Receive BDsonly). This must be set by the driver, it is just copiedthrough opaquely by the NIC firmware.

0x0020 BD_FLAG_UCAST_PKT Unicast packet (part of 2 bit field).

0x0040 BD_FLAG_MCAST_PKT Multicast packet that is not a broadcast packet (part of 2bit field).

0x0060 BD_FLAG_BCAST_PKT Broadcast packet (part of 2 bit field).

0x0080 BD_FLAG_IP_FRAG This BD is part of an IP fragmented frame.

0x0100 BD_FLAG_IP_FRAG_END Last BD in the last fragment in a train of fragments.

0x0200 BD_FLAG_VLAN_TAG IThe frame associated with this buffer descriptor has an802.1q VLAN tag associated with it.

0x0400 BD_FLAG_FRAME_HAS_ERROR An error was detected by the NIC. The error detected isset in the error_flag word of the receive buffer descriptor.

0x0800 BD_FLAG_COAL_NOW This bit is an explicit indication that the Send ConsumerIndex should be updated when the buffer associated withthis buffer descriptor has been DMAed to the NIC. Aninterrupt may or may not be generated depending on thestate of the RCB_FLAG_COAL_UPDATE_ONLY bit andthe interrupt avoidance mechanism.

0x1000 BD_FLAG_MINI_RING Indicates that this packet came from the Mini ReceiveRing, not the Standard Receive Ring (For Receive BDsonly). This must be set by the driver, it is just copiedthrough opaquely by the NIC firmware.



is to

nd them

is

3.2 Commands

A Command is a directive to the NIC.

Figure 13. Command Definition

Cmd is a 1 byte field that specifies the Command.

Flags is a 12 bit field that gives additional command-specific information.

Index is a 12 bit field that contains the index that the command relates to, or what the indexbe set to, depending on the context of the command.

3.2.1 Extended CommandsThere are some commands that are “extended”. That is, they take multiple command slots ainformation following the actual command is somewhat free form. The details of the free forinformation is described in the individual commands. All such commands start withTG_CMD_EXT.

3.2.2 TG_CMD_HOST_STATECmd: 0x01

Index: 0

Flags:

This command is sent by the Host to inform the NIC of the state of its stack. The Host stateinitialized to DOWN. There is no acknowledgment to this command.

3.2.3 TG_CMD_FDR_FILTERINGCmd: 0x02

Index: 0

Flags:

Table 27. TG_CMD_HOST_STATE flags

Value Meaning

0x001 Host stack up

0x002 Host stack down

Table 28. TG_CMD_FDR_FILTERING flags

Value Meaning

0x001 Enable software filtering

0x002 Disable software filtering

31 11 023cmd flags index



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This command is sent by the Host to inform the NIC to use software filtering of MAC addresinstead of hardware filtering. This is used to overcome a bug in the original Tigon MAC that cause the occasional loss of frames in environments where the NIC could receive a large qof frames not intended for it. This can happen when attached to a full duplex repeater.

This command is not implemented for Tigon 2 ASICs.

There is no acknowledgement to this command.

3.2.4 TG_CMD_SET_RECV_PRODUCER_INDEX (OBSOLETE)Cmd: 0x03

Index: New recv producer index

Flags: 0

This command is sent by the Host to inform the NIC that there are Receive Buffer Descriptoready to be consumed from the Standard Receive Ring. There is no acknowledgment to thicommand.

This command still works but has been obsoleted by a direct mechanism. (See Section“Mailboxes“).

3.2.5 TG_CMD_UPDATE_GENCOM_STATSCmd: 0x04

Index: 0

Flags: 0

This command is sent by the Host to inform the NIC that there is new data in the GeneralCommunications Area and it should be reread. Only the ifIndex and ifMTU fields are reread.command is typically used to reset the ifMTU field to establish the threshold where packets shbe marked as too long. There is no acknowledgment to this command.

3.2.6 TG_CMD_RESET_JUMBO_RINGCmd: 0x05

Index: 0

Flags: 0

This command is sent by the Host to inform the NIC that it should stop using the Jumbo ReRing. It is typically used to retrieve the buffers associated with the Jumbo Receive Ring wheinterface is using Jumbo Frames. This command is acknowledged by theTG_EVENT_RESET_JUMBO_RING.

3.2.7 TG_CMD_SET_PARTIAL_RECV_COUNTCmd: 0x06

Index: special

Flags: special



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This command is sent by the Host to inform the NIC that it should not DMA the entire packeInstead it should DMA the number of bytes specified in the concatenation of the index and tflags field. That is the Index and flags field are treated as a single 24 bit field. The maximum vallowed is 65532 (64k - 4). A value of 0 indicates that the entire frame should be DMAed. Nthat this command does not effect the value placed into the received buffer descriptor length

This command only operates if receive checksum is disabled. If this command is issued andreceive checksumming is enabled a TG_EVENT_ERROR event of type “Invalid command” generated by the NIC and the command is ignored.

3.2.8 TG_CMD_ADD_MULTICAST_ADDR (OBSOLETE)Cmd: 0x08

Index: 0

Flags: 0

This command is sent by the Host to inform the NIC of a new address in the Multicast MACAddress Transfer Buffer (See “Multicast MAC Address Transfer Buffer (OBSOLETE)”, sectio2.1.1.4.3). The NIC updates its multicast filtering list by adding this new MAC address andacknowledges the command with a Multicast List Updated Event (See“TG_EVENT_MULTICAST_LIST_UPDATED”, section 3.3.5).

Although this mechanism is still accepted, this command has been superceded by theTG_CMD_EXT_ADD_MULTICAST_ADDR command.

3.2.9 TG_CMD_DEL_MULTICAST_ADDR (OBSOLETE)Cmd: 0x09

Index: 0

Flags: 0

This command is sent by the Host to inform the NIC of a new address in the Multicast MACAddress Transfer Buffer (See “Multicast MAC Address Transfer Buffer (OBSOLETE)”, sectio2.1.1.4.3). The NIC updates its multicast filtering list by deleting this MAC address andacknowledges the command with a Multicast List Updated Event. (See“TG_EVENT_MULTICAST_LIST_UPDATED”, section 3.3.5).

Although this mechanism is still accepted, this command has been superceded by theTG_CMD_EXT_DEL_MULTICAST_ADDR command.

3.2.10 TG_CMD_SET_PROMISC_MODECmd: 0x0a

Index: 0

Flags:

Table 29. TG_CMD_SET_PROMISCUOUS_MODE flags

Value Meaning

0x001 Enable promiscuous mode

0x002 Disable promiscuous mode



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Upon receiving this command, the NIC enables or disables the promiscuous mode of its MAThere is no acknowledgment to this command.

3.2.11 TG_CMD_LINK_NEGOTIATIONCmd: 0x0b

Index: 0

Flags:

Table 30. TG_CMD_SET_LINK_NEGOTIATION flags

Upon receiving this command, the NIC renegotiates link negotiation based on the flags in thGigabit and/or the 10/100 Link Negotiation field of the Tuning Parameters structure (See “GigLink Negotiation”, section 2.1.1.4.10.7 and See “10/100 Link State”, section 2.1.1.4.18). Theno acknowledgement to this command.

3.2.12 TG_CMD_SET_MAC_ADDRCmd: 0x0c

Index: 0

Flags: 0

Upon receiving this command, the NIC rereads its MAC Address Register (See “MAC Addresection 2.1.1.4.1) and updates the MAC portion of the NIC. Note that this does not affect outgframes as they are built by the Host. There is no acknowledgment to this command.

3.2.13 TG_CMD_CLEAR_PROFILECmd: 0x0d

Index: 0

Flags: 0

Upon receiving this command, the NIC clears all of the profiling data. This command is avaionly if the driver has Profiling Enabled. Profiling is a compile time option and is disabled bydefault. Therefore, unless it is enabled at compile time, this command will result in an unknocommand. There is no acknowledgment to this command.

3.2.14 TG_CMD_SET_MULTICAST_MODECmd: 0x0e

Index: 0

Value Meaning

0x000 Renegotiate link on both PHYs

0x001 Renegotiate link on Gigabit PHY

0x002 Renegotiate link on 10/100 PHY



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Flags:

Upon receiving this command, the NIC enables or disables the multicast mode of its MAC. Wmulticast mode is enabled all multicast packets are delivered to the host, regardless of the sof the multicast filtering list. When multicast mode is disabled then only those multicast packthat are in the multicast filtering list are delivered to the host. This command does not affectcurrent entries in the multicast filtering list. If further entries are added to or deleted from themulticast filtering list while the NIC is in multicast mode the updated state will be used whenmulticast mode is exited. There is no acknowledgment to this command.

3.2.15 TG_CMD_CLEAR_STATSCmd: 0x0f

Index: 0

Flags: 0

Upon receiving this command, the NIC clears all stats. There is no acknowledgment to thiscommand.

3.2.16 TG_CMD_SET_RECV_JUMBO_PRODUCER_INDEX (OBSOLETE)Cmd: 0x10

Index: New recv producer index

Flags: 0

This command is sent by the Host to inform the NIC that there are Receive Buffer Descriptoready to be consumed from the Jumbo Receive Ring. There is no acknowledgment to thiscommand.

This command still works but has been obsoleted by a direct mechanism. (See Section“Mailboxes“).

3.2.17 TG_CMD_REFRESH_STATSCmd: 0x11

Index: 0

Flags: 0

This command is sent by the Host to inform the NIC that it should update its current statistics.new statistics are found in the structure pointed to by the Refresh Stats Pointer. There is apossibility that if the NIC is receiving or sending packets during the execution of this commasome statistics could be slightly incorrect. It is therefore recommended that this command onexecuted when the NIC is configured to not receive packets and while no packets are beingThere is no acknowledgment to this command.

Table 31. TG_CMD_SET_MULTICAST_MODE flags

Value Meaning

0x001 Enable Multicast mode

0x002 Disable Multicast mode



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3.2.18 TG_CMD_EXT_ADD_MULTICAST_ADDRCmd: 0x12

Index: 0

Flags: 0

Extension: 2 commands

This command is sent by the Host to inform the NIC of a new Multicast address that the NICshould accept. The address follows the command as a command extension in the next twocommand slots. The format of the standard MAC address format (See “MAC Addresses”, se1.3.3). The NIC updates its multicast filtering list by adding this new MAC address andacknowledges the command with a Multicast List Updated Event (See“TG_EVENT_MULTICAST_LIST_UPDATED”, section 3.3.5).

3.2.19 TG_CMD_EXT_DEL_MULTICAST_ADDRCmd: 0x13

Index: 0

Flags: 0

Extension: 2 commands

This command is sent by the Host to inform the NIC of a Multicast address that the NIC shoullonger accept. The address follows the command as a command extension in the next twocommand slots. The format of the standard MAC address format (See “MAC Addresses”, se1.3.3). The NIC updates its multicast filtering list by deleting this MAC address and acknowledthe command with a Multicast List Updated Event (See“TG_EVENT_MULTICAST_LIST_UPDATED”, section 3.3.5).

3.3 Events

An Event is a signal to the Host that something has occurred that the Host should be awareGenerally speaking, all Events cause interrupts. However, the events can be coalesced andinterrupts can be avoided. Please See “Interrupt Avoidance”, section 2.5.2 for details.

Events are 8bytes long.

Figure 14. Event Definition

Event is a one byte field that specifies the Event.

Code is a 12 bit field that gives event-specific information.

Index is a 12 bit field that gives additional code specific information.

31 11 023event code index

reserved



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3.3.1 TG_EVENT_NIC_FIRMWARE_OPERATIONALEvent: 0x01

Code: 0

Index: 0

This event is the first event that the NIC generates. The Host will not issue any commands tNIC until this event has been received. The Host is interrupted when this event is generated

3.3.2 TG_EVENT_STATS_UPDATEDEvent: 0x04

Code: 0

Index: 0

This event is generated whenever the NIC updates the statistics area in Host memory. The may also use this event to reset its watchdog timer. It is recommended that theTG_EVENT_STATS_UPDATED event be used as a watchdog event. Should the NIC not genthis event within a reasonable period of time (See “Stat Ticks”, section 2.1.1.4.10.3) you canassume that the NIC has died and appropriate action should be taken. The Host is interruptedthis event is generated (subject to the Interrupt Avoidance mechanism described in Section“Interrupt Avoidance“).

3.3.3 TG_EVENT_LINK_STATE_CHANGEDEvent: 0x06

Code:

Index: 0

This event is generated whenever the link changes state. When the NIC is initialized, the castate is initialized to OFF. The host is interrupted when this event is generated (subject to thInterrupt Avoidance mechanism described in Section 2.5.2 “Interrupt Avoidance“).

3.3.4 TG_EVENT_ERROREvent: 0x07.

Code:

Table 32. TG_EVENT_LINK_STATE_CHANGED codes

Value Meaning

0x001 Gigabit link is now UP

0x002 Link is now DOWN

0x003 10/100 link is now UP

Table 33. ERROR codes

Value Meaning

0x001 Invalid command

0x002 Unimplemented command



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Index: Command in question.

This event is generated whenever an error occurs. The host is interrupted when this event igenerated (subject to the Interrupt Avoidance mechanism described in Section 2.5.2 “InterruAvoidance“).

3.3.5 TG_EVENT_MULTICAST_LIST_UPDATEDEvent: 0x08.

Code:

Index: 0.

This event is generated in response to the Add Multicast Address (See“TG_CMD_ADD_MULTICAST_ADDR (OBSOLETE)”, section 3.2.8) or Delete MulticastAddress (See “TG_CMD_DEL_MULTICAST_ADDR (OBSOLETE)”, section 3.2.9) commanafter reading the Multicast MAC Address Transfer Buffer (See “Multicast MAC Address TransBuffer (OBSOLETE)”, section 2.1.1.4.3) and updating the NIC’s multicast list appropriately. host is interrupted when this event is generated (subject to the Interrupt Avoidance mechandescribed in Section 2.5.2 “Interrupt Avoidance“).

3.3.6 TG_EVENT_RESET_JUMBO_RINGEvent: 0x09

Code: 0

Index: 0

This event is generated in response to a TG_CMD_RESET_JUMBO_RING command. It isgenerated as soon as the consumer and producer of the jumbo ring have been disabled. Theinterrupted when this event is generated (subject to the Interrupt Avoidance mechanism desin Section 2.5.2 “Interrupt Avoidance“)

0x003 Invalid configuration

Table 34. TG_EVENT_MULTICAST_LIST_UPDATED codes

Value Meaning

0x001 Multicast address added

0x002 Multicast address deleted

Table 33. ERROR codes

Value Meaning


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4 PERFORMANCE TUNING

Performance tuning is an art. The following are a few pointers to key areas that you should study and use to experiment. Good luck!

4.1 Reducing the Host/NIC interaction

This API is designed to reduce the number of times that information must be passed betweHost and the NIC. This means that the amount of information passed on any interaction mularge. It also means that whenever possible the simplest and fastest mechanism should be carry the information. This reduction of interaction is done through coalescing work for multpackets into single information packets and by reducing interrupts through “Interrupt Avoida

4.1.1 Information CoalescingThe NIC Firmware is designed to pass information to the Host interrupt the Host in chunks. advantage of provide information in chunks is that it reduces the number of times the Host aNIC must interact. The disadvantage is that it can create latencies. This is a trade off that mcarefully tested by the Host driver designer. Setting the coalescing thresholds too high can longer latencies that you desire. The NIC firmware does attempt to reduce these latencies, hoby not coalescing in cases where it has been a “long time” since the last bit of information haspassed.

The mechanism used for receive packet coalescing is the Recv BD Coalescing parameter fothe Tuning Parameters area. This parameter controls the number of packets that NIC will rebefore updating the Receive Return Ring Producer Index. The NIC updates the Receive ReRing Producer Index immediately if a hard clock tick has occurred since the last update (10microseconds). After the Recv Return Ring Producer Index has been updated there may beinterrupt generated subject to the Interrupt Avoidance algorithms.

If the Recv BD Coalescing counter is set to zero, the Receive Return Ring Producer Index wupdated every time a frame is received generating extra DMA activity.

The Send BD Coalescing count reduces the number of times the Send Consumer Index is upFor example, if this count is set to 60, one update of the Send Consumer Index will be doneevery 60 frames transmitted. The number of clock ticks that must expire before the SendConsumer Index is updated regardless of the current coalescing count is set using the SendCoalesced Ticks parameter. The buffer descriptor also has an explicit return flag (See “BuffeDescriptor Flags”, section Table 26.)

If the Send BD Coalescing counter is set to zero, the Send Consumer Index will be updatedtime a frame has been transmitted.

The developer is encouraged to experiment with these values in order to obtain a good balanyour particular operating system.


Gigabit Ethernet/PCI NIC Software Definition PERFORMANCE TUNING

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4.1.2 Interrupt AvoidanceIn addition to the counts described above, the NIC firmware guarantees that it will not generainterrupt if it finds that the Host is already in the Interrupt Handler or processing Events. Thefirmware uses two mechanisms to determine if the Host is already in the Interrupt Handler oprocessing events.

First, the NIC firmware inspects the Interrupt State Bit in the Miscellaneous Host Control regi(See Section 2.1.1.2.1 “Tigon Miscellaneous Host Control Register.) The Interrupt State Bit, wset, indicates that the Host is already processing interrupts or events and the NIC firmware senqueues the new event or updates the appropriate index without generating an interrupt. Tmechanism is for platforms where the Host processes all the events while in staying in theInterrupt Handler.

Second, the NIC firmware inspects Mailbox 0 (See Section 2.1.1.3 “Mailboxes). If a 1 is writteMailbox 0, the NIC firmware assumes that the Host is already processing interrupts or evenwill not generate an Interrupt. This mechanism is for Hosts which do not perform all work inInterrupt Handler, but rather dispatch a task (or thread of execution) to process events and updates.

For the second type of Host, the first act of the task or thread is to write a 1 inmailbox 0 and storethe value of the event, send, and receive indices. Just prior to writing a 0 to mailbox 0 and ethe task or thread, the value of the indices must be compared to the previously stored valuedetermine if there is more work to do. A change in one of the values indicates the arrival ofadditional work which must be handled, since the NIC will not generate an interrupt for thembecause there is a 1 in Mailbox 0.

Finally, for send interrupts the interrupt mechanism can be further defeated by setting theRCB_FLAG_COAL_UPDATE_ONLY flag in the Send RCB. This bit might be used if your drivusually wishes to reap send completion events from the Send Packet handler.

4.2 Receive RingThe NIC firmware is designed to use multiple Receive Buffer Descriptors at a time. Developerencouraged to send empty Receive Buffer Descriptors to the NIC in blocks, rather than onetime, to reduce the per-frame overhead.

4.3 Send RingTo reduce per-frame overhead, it is recommended that the developers initialize all the fieldsSend Ring Descriptors once and update only those fields that are necessary for each frame.ample, if the same buffers are reused, the address field does not need to be rewritten over an

4.4 Transmitting Latencies and Buffer DescriptorsThe current version of the firmware takes approximately 5 microseconds to process a buffedescriptor (from the point where it reads the buffer descriptor until a DMA is begun on an idNIC). In order to get the best performance the host driver should coalesce small buffer descrinto a single buffer descriptor until the DMA time of the operation is approximately 5microseconds. For example, on a host system that has read DMA performance of 100 MB/shost should coalesce small buffers (when possible) until 500 bytes have been coalesced.



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4.5 NIC Data Buffer SizesThe NIC’s internal data buffering can be controlled by the Transmit Buffer Ratio parameter ofGeneral Communications Area. By changing this ratio you may find performance differencesystems that are limited in bus performance in either the read or the write direction. The useJumbo Frames may also affect this ratio. We have found that unless Jumbo Frames are bein64 KB of transmit buffer is plenty. However for Jumbo enabled drivers you may improveperformance by increasing this number to as much as 256 KB (about a 5/16 ratio for a 1 MB

4.6 PCI Command Memory Write and InvalidateOne some hosts there is a significant difference in performance between the PCI commandMemory Write and the PCI command Memory Write and Invalidate. The Memory Write andInvalidate command can be made to work on both Tigon and Tigon 2 ASICs.

4.6.1 Memory Write and Invalidate on the Tigon ASICTo use the Memory Write and Invalidate command on the original Tigon ASIC you must setso that it isalwaysused (that is, Memory Write commands cannot be generated). Setting this uvery simple, just set the PCI Write Command field of the PCI State Register to 0xF instead standard 7 (See “Tigon PCI State Register”, section 2.1.1.2.4). This will cause the entire cachto be invalidated every time a write DMA occurs, so it is important to ensure that any place wdata is going to be written using a DMA can handle a full cache line invalidation.

The sample driver code is set up to allow this to happen, so long as the cache line is 32 byteor smaller. In particular, the send, receive and event indices are placed in their own 32 byte lines. Also the Receive Buffer Descriptor is 32 bytes long and the array is aligned on a 32 bboundary to ensure that writing any descriptor will not cause a problem with any other previowritten descriptor. Finally, the data receive buffers are allocated in a way to ensure that cachewill not overlap other data.

4.6.2 Memory Write and Invalidate on the Tigon 2 ASICWhile somewhat harder to set up, the Tigon 2 ASIC will use the Memory Write and Invalidateway that is transparent to cache line boundaries. That is, when it is possible to use this commwill, but if the entire cache line is not being written it will not use this command. If your host habus implementation where Memory Write is significantly slower than Memory Write andInvalidate you may want to implement the cache line tricks described above. (See “Memory Wand Invalidate on the Tigon ASIC”, section 4.6.1)

To set up the use of this command make sure that you set thePCI_CONF_CMD_MEM_WRITE_INVALIDATE bit in the PCI Configuration CommandRegister (See PCI Local Bus Specification Revision 2.1 [1]). Also ensure that your BIOS haproperly set up the Cache Line Length field of the PCI Configuration region. Finally, set the WMax DMA field of the PCI State Register to indicate the same size as your the Cache Line Lefield of the PCI Configuration region. (See “Tigon PCI State Register”, section 2.1.1.2.4)



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4.7 PCI Command Memory Read MultipleThe NIC has two modes of operation for choosing which PCI Read Memory command to usThese modes are selected using the “Use Memory_Read_Multiple PCI Command” bit of theTigon PCI State Register (See “Tigon PCI State Register”, section 2.1.1.2.4). The following describes when each command is used. Normal Command Set refers to when the “UseMemory_Read_Multiple PCI Command” bit is not set. The Optional Command Set refers to wit is set.

4.8 PCI Burst LengthFor best performance, experiment with the Read Max DMA and Write Max DMA fields in the PState Register (detailed in Section 2.1.1.2.4). The default setting of 0 was selected for the sdriver because it provides optimal performance for most systems. Note that the use of the MeWrite and Invalidate command on Tigon 2 ASICs requires that the value for the Write Max Dfield be set to the Cache Line Length.

4.9 Checksum Offload

Checksum offload can significantly decrease the amount of time that the Host’s CPU spendprocessing a packet. Many systems spend as much as 15% of their time just calculatingchecksums. In general, if the host can support checksum offload there will be a major performgain. However, if you cannot support checksum offload in your host be sure you do not set athe flags in the RCBs that would enable these features. Enabling these features requires dialgorithms in the NIC that can adversely effect performance.

4.10 DMA Read Errata on Tigon 2 ASICs

4.10.1 Problem DescriptionWhen the Tigon 2 (Rev. 6) ASIC performs a read transaction, it can expect several responsranging from completing the cycle to being told to retry it. In the event of a retry, the device re-issue the same command to the same address in order to be compliant. Occasionally in operating modes, the Tigon 2 ASIC does not reissue the exact same command.

4.10.2 DetailsThe ASIC may issue a Memory Read Multiple (MRM) with either a Memory Read Line (MRL)a Memory Read (MR) command issued during the retry. It might also try a MRL with a MR onretry. Either one of these conditions violates the PCI spec.

Table 35. Memory Read Command Usage

Number of Words Normal Command Set Optional Command Set

< 1/2 the cache size or 1-2words if cache size disabled

Memory Read Memory Read

> 1/2 the cache size or 3-15words if cache size disabled

Memory Read Line Memory Read Multiple

> cache size or > 16 words ifcache size disabled

Memory Read Multiple Memory Read Multiple



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The Tigon ASIC uses the number of words remaining in the DMA to determine what readcommand to issue. From the time the length register changes until the correct command cadriven on the PCI bus is three cycles. Unfortunately, under certain conditions, the ASIC will ba new transaction in two cycles. In this situation, the Tigon can send out the old read commThis isn’t a problem by itself, although it may be inefficient for the memory sub-system. Howeif this access is retried, the length register will be fully updated and a different read commandcome out.

These three conditions must be met for the problem to occur.

• The Tigon ASIC must begin a read transaction within two cycles of finishing a previous retransaction.

• The number of words remaining after the previous transaction must cross a full or halfcacheline boundary.

• The command must be retried.

Your bridge chip may or may not create the third condition. If it does then you must by propeconfiguring the Tigon ASIC to avoid either the first or the second condition. If your bridge chdoes not cause a command to be retried then you need not worry about this errata.

4.10.3 Work-around OptionsThe first condition occurs only when the Tigon is voluntarily stopping DMA on programmablpower of boundaries. In this configuration, the Tigon ends all DMA bursts when the boundacrossed. It does not stop requesting the bus, so if the bus grant is still active, it will begin antransaction until the grant is removed or the DMA is finished. Any condition that forces the ASto drop its bus request will guarantee that it cannot begin another access within 2 cycles of thof a previous one. This behavior is controlled by the Read_Max_DMA bits in the PCI stateregister. When these bits are set to zero (Disabled), the Tigon will keep the bus until told to stuntil the DMA is finished. It will not be able to generate accesses that occur two cycles apart.“Tigon PCI State Register”, section 2.1.1.2.4).

The second condition can be worked around by forcing the read transactions to ask for moreWhen the Tigon ASIC realizes it doesn’t need more than a cacheline of data, it changes thecommand from MRM to something smaller (MRL or just MR.) If the ASIC is forced to use thlarger commands all the time, than the retry command will always agree with the originalcommand. To accomplish this, the use Mem_Read_Multiple bit must be set and the defaultread command must be a MRM. These bits are also located in the PCI state register. (See PCI State Register”, section 2.1.1.2.4).

4.10.4 Impact ObservationsEach workaround has potential performance impacts. The first workaround could change thutilization of the Tigon ASIC. If the bus grant is inactive when the ASIC ends a burst, the TIGhas lost control of the bus until the grant returns. If the Max DMA bits are zero, the ASIC willgive up the bus until the latency timer expires. If the latency timer is longer than the Max DMtime, changing the Max DMA time to unlimited could result in the Tigon holding the bus longbecause it will not release the bus until the latency timer expires. If the latency timer is shorterthe maxDMA time, disabling the max DMA time could also result in the ASIC giving up the bless often. This analysis is extremely dependent upon the host system arbiter performance.



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The second workaround will not change the bus utilization, but it might use the memorysubsystem poorly. With this workaround, the Tigon could ask for a MRM even if it only needcouple of bytes. Depending upon its design, the memory subsystem could have pre-fetchedthat it doesn’t need.


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5 Firmware Initialization

This section describes firmware start-up and processing from power on, system reboot andCode restart. The bootstrap loader is kept in ROM. NIC PCI register values and various othmanufacturing information such as the MAC Address are kept in the EEPROM. In addition, are two firmware code objects in the EEPROM. They are:

• PCI Configuration and Memory Initialization

• Diagnostics.

5.1 Power-on Bootstrap Sequence

The bootstrap sequence is:

1. Run ROM bootstrap loader and load step 2

2. Run PCI configuration and memory initialization code and load step 3

3. Run Diagnostics code and enter cable integrity loop

The ROM bootstrap loader checksums the bootstrap area of EEPROM and performs the 32CRC check on the PCI configuration and memory initialization code as it loads the firmwareinto the SRAM. Then it clears the ROM fail bit in the CPU_STATE register and executes thefirmware.

The PCI configuration and memory initialization firmware initializes the PCI configurationregisters and calls the bootstrap loader to load the diagnostics. The reason for this two stagprocess is that the PCI configuration registers must be set up before the host PCI BIOS detecard.

The diagnostics code tests the address and data lines and SRAM integrity, flashes the LEDthen go into an operational mode which monitors the link state and lights the link LED whenthe link is established.

5.2 Hard Reset

A hard reset is due to system power up, PCI reset, or the Hard Reset bit in the MiscellaneousControl Register (See “Tigon Miscellaneous Host Control Register”, section Table 6.) The hreset causes the bootstrap sequence to be executed.

5.3 Operation at System Reboot

When the Host system boots, the host driver executes its initialization. Part of this initializatiloading the Run Time Code into the NIC’s SRAM and starting it.

NOTE: At present, only Cable Integrity Check is supported. Other items will be supported infuture release.


Gigabit Ethernet/PCI NIC Software Definition Firmware Initialization

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5.4 Firmware Download

In order to use the NIC you must download the runtime firmware provided with your open drkit. See Section 5.5.1 “Runtime Program File. To download this code you must fill in the TexData, and Read-only segments with the data present in the appropriate array. This data is pinto NIC’s memory by copying it from the appropriate array into the NIC’s memory via the shamemory window. See Section 2.1.1.2.5 “Tigon Window Base Address Register. The BSS anshort BSS segments must be zeroed.

Once the firmware is loaded it is prudent to verify that it is correct. Just compare the memory iNIC against the original arrays. Again this must be done by using the shared memory windo

Finally, once the firmware is downloaded and verified set the Program Counter to the start adspecified in the firmware header file and start the firmware using the NIC’s CPU State register“Tigon CPU State Register”, section 2.1.1.2.8). For Tigon 2 systems, CPU B must not be staby the Host, the initialization code in CPU A’s firmware starts CPU B.

The initialization code at the beginning of the firmware load has a set of instructions that will hthe new driver developer determine if the NIC has been downloaded correctly with respect toswapping and word swapping. The following table indicates failure address, CPU state regisvalue and cause. The addresses specified assumes that the start address is 0x4000.

5.5 Firmware Reload Operation

The host software loads the firmware in two cases:

1. The NIC halts. In this case the Host takes a firmware core dump, resets the NIC, runs hodiagnostics, reloads the run code, re-initializes all data structures, and restarts the NIC c

2. An administrative request is received. In this case the software halts the NIC, reloads thecode, re-initializes all data structures, and restarts the NIC code.

Once the run code is started, the firmware initializes the NIC. When initialization is completeNIC informs the Host via a NIC_FIRMWARE_OPERATIONAL event.

NOTE: Be certain to stop the NIC processor before attempting to download the firmware usithe Halt Bit of the CPU State Register (See “Tigon CPU State Register”, section 2.1.1.2.8).

Table 36. Firmware Failure Locations

Failure Address CPU State RegisterValue

Cause

0x4002 0x80000 Byte swapped only

0x4004 0x10000 Word swapped only

0x4003 0x80000 Byte and word swapped



r filethe

e fiven theta, andropriate

icated are

5.5.1 Runtime Program FileThe firmware file is a binary file in MIPS ELF format that has been converted into a C headewith the instructions and data placed into initialized arrays. The name of this file is alt_fw.h fororiginal Tigon ASIC and alt_fw2.h for the Tigon 2 ASIC. One or both should be included intoyour driver and the correct one downloaded depending on the revision of the ASIC. There ardifferent sections of the runtime firmware, Text, Data, Read-only data, BSS, and short BSS. Ialt_fw.h file the starting address and length of each segment are specified. For the Text, DaRead-only data segments the actual data associated with these segments is given in the appinitialized array.

5.6 Link Ready Operation

The NIC passes frames only when the optical link is established. The state of the link is indon the “Link” LED on the NIC bulkhead. On means that the Link is Up. Changes in link statepassed to the Host software using the LINK_STATE_CHANGED event.

After the NIC_FIRMWARE_OPERATIONAL event is posted, the Run Code posts aLINK_STATE_CHANGED event.

The NIC EEPROM code does not have link negotiation code in it. Link negotiation isaccomplished via the NIC firmware.




. It is

d

6 Bibliography

The following documents are useful in understanding the context in which the NIC operatesalways encouraged to use the latest revision of each document.

[1] PCI Special Interest Group,PCI Local Bus Specification Revision 2.1, 1995, June.

[2] IEEE,Overview and Architecture, ANSI/IEEE 802-1990.

[3] IEEE,Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Methoand Physical Layer Specification, ANSI/IEEE Standard 802.3-1990.

[4] Postel, J.,Internet Protocol, RFC 791, 1981 September; 45 p.

[5] Postel, J.,User Datagram Protocol, RFC 768, 1980 August 28; 3 p.

[6] Postel, J.,Transmission Control Protocol, RFC 793, 1981 September; 85 p.

[7] Kastenholz, F.,Definitions of Managed Objects for the Ethernet-like Interface Types, RFC1643, 1994 July; 19 p.

[8] Rose, M; McCloghrie, K.,eds.,Management Information Base for network management ofTCP/IP-based internets:MIB-II, RFC 1213, 1991 March; 70 p.

[9] McCloghrie, K.;et.al., eds.,Evolution of the Interfaces Group of MIB-II, RFC 1573, January1994


Gigabit Ethernet/PCI NIC Software Definition Bibliography


Documents

Gigabit Ethernet/PCI Network Interface Card Host/NIC ...wpaul/Alteon/pcinic.pdf · July 1999 Alteon WebSystems, Inc. 50 Great Oaks Blvd. San Jose, CA 95119 1-408-360-5500 Gigabit