library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_unsigned.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;Entity uart1 isport( Clk : in STD_LOGIC;BRS : in STD_LOGIC_vector(2 downto 0);TxD : out STD_LOGIC;RxD : in STD_LOGIC;Mode_TxD_RxDBar : in STD_LOGIC;TxDbusy : out STD_LOGIC;RxDrdy : out STD_LOGIC; Rst : in STD_LOGIC; Load : in STD_LOGIC; --Din : in STD_LOGIC_VECTOR(7 downto 0); Dout : out STD_LOGIC_vector(7 downto 0)); end uart1;architecture Behavioral of uart1 issignal temp : integer;signal top16 : std_logic;signal TxDClk : std_logic;signal clkdiv : integer;signal RxDClk : std_logic;signal RxDdiv : integer;SIGNAL Din : STD_LOGIC_VECTOR(7 downto 0) := "10011010";--signal ClrDiv : std_logic;signal TxD_Reg : std_logic_vector(9 downto 0);signal RxD_Reg : std_logic_vector(7 downto 0);signal TxDBitCnt : integer;signal RxDBitCnt : integer;signal RegDin : std_logic_vector(7 downto 0);type state is (idle, load_TxD, shift_TxD,stop_TxD);signal TxDFSM : state;type state1 is (idle, start_RxD, Edge_RxD, DataErr_RxD, shift_RxD,stop_RxD);signal RxDFSM : state1;begin-- Baud rate selectionprocess (RST, CLK)beginif (RST='1') thentemp temp temp temp temp temp temp temp temp temp