G[G Àp G[ u YWX u GYWX - IEEE Computer Society · total synaptic current + Ý L + Ý > F + Ý ?.That way, the difference between positive and negative total synaptic current through

Editor-in-Chiefs: Anirban SenguptaSaraju P. Mohanty

ieee-tcvlsi.org

From the Editor-in-Chief’s Desk - Editorial

The IEEE VLSI Circuits and Systems Letter (VCAL)is affiliated with the Technical Committee on VLSI (TCVLSI) under the IEEE Computer Society. It aims to report recent advances in VLSI technology, education and opportunities and, consequently, grow the research and education activities in the area. The letter, published quarterly (from 2018), covers the design methodologies for advanced VLSI circuit and systems, including digital circuits and systems, hardware security, design for protection, analog and radio-frequency circuits, as well as mixed-signal circuits and systems. The emphasis of TCVLSI falls on integrating the design, secured computer-aided design, fabrication, application, and business aspects of VLSI while encompassing both hardware and software. TCVLSI sponsors a number of premium conferences and workshops, including, but not limited to, ASAP, ASYNC, ISVLSI, IWLS, SLIP, and ARITH. Emerging research topics and state-of-the-art advances on VLSI circuits and systems are reported at these events on a regular basis. Best paper awards are selected at these conferences to promote the highquality research work each year. In addition to these research activities, TCVLSI also supports a variety of educational activities related to TCVLSI. Several student travel grants are sponsored by TCVLSI in the following meetings: ASAP2018, ISVLSI 2018, IWLS 2018, iSES 2018(formerly iNIS 2017) and SLIP 2018. Funds are provided to compensate student travels to these meetings as well as attract more student participation. The organizing committees of these meetings undertake the task of selecting right candidates for these awards. The current issue of VCAL showcases the state-of-the-art developments covering several important areas: Low Power Artificial Neural Network Architecture, Ultra-Low Power Techniques to 10T Junction Less Double Gate Hybrid Full Adder, SOI FinFET Based Three Stage OTA, Reversible Logic Gate with Improved Parametric Attributes using GDI Techniqueetc. Professional articles are solicited from technical experts to provide an in-depth review of these areas. The articles can be found in the section of “Features Articles”. In the section of “Updates”, upcoming conferences/workshops, call for papers and proposals, funding opportunities, job openings, conference report and Ph.D. fellowships are summarized. Additionally, a “Member News” section is started from this issue onward covering the achievements of TCVLSI members. We would like to express our great appreciation to all editorial board members (Yiyu Shi, Himanshu Thapliyal, Michael Hübner, Theocharis Theocharides, Jun Tao Shiyan Hu, Hideharu Amano, Mike Borowczak, Helen Li, Saket Srivastava, YasuhiroTakahashi, Sergio Saponara, James Stine and Qi Zhu) for their dedicated effort and strong support in organizing this letter. The complete editorial board information is available at: https://www.computer.org/web/tcvlsi/editorial-board. We are thankful to our web chair Mike Borowczak, for his professional service to make the letter publicly available on the Internet. We wish to thank all authors who have contributed their professional articles to this issue. We hope that you will have an enjoyable moment when reading the letter! The call for contributions for the next issue is available at the end of this issue and we encourage you to submit articles, news, etc. to an associate editor covering that scope.

Saraju Mohanty Editor-in-Chief of IEEE VCAL, TCVLSI

University of North Texas

Anirban Sengupta Chair, IEEE Computer Society TCVLSI

Editor-in-Chief of IEEE VCAL, TCVLSI Indian Institute of Technology (I.I.T) Indore

ieee-tcvlsi.org

Features

Low Power Artificial Neural Network Architecture Krishna Prasad Gnawali ,Student Member, IEEE, Seyed Nima Mozaffari ,Student Member, IEEE, and Spyros Tragoudas ,Senior Member, IEEE Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, USA

Abstract –Recent artificial neural network architectures improve performance and power dissipation by leveraging resistive devices to store and multiply synaptic weights with input data. Negative and positive synaptic weights are stored on the memristors of a reconfigurable crossbar array (MCA). Existing MCA-based neural network architectures use high power consuming voltage converters or operational amplifiers to generate the total synaptic current through each column of the crossbar array. This paper presents a low power MCA-based feed forward neural network architecture that uses a spintronic device per pair of columns to generate the synaptic current for each neuron. It is shown experimentally that the proposed architecture dissipates significantly less power compared to existing feed forward memristive neural network architectures. 1. Introduction

Artificial neural networks are used in many applications such as pattern matching, character and speech recognition, and big data management, among others. They consist of an input layer, an output layer, and multiple hidden layers [1, 2, 3, 4]. Each layer consists of several neurons. Each neuron has multiple inputs that are typically real numbers and one output that is typically a real number. Each neuron communicates with other neurons through links called synapses that have positive or negative weight values. The neuron calculates the sum of all its weighted inputs and maps the sum into an output signal by a transfer function called activation function [1, 5-8].

An emerging artificial neural network paradigm uses reconfigurable memristive crossbar array (MCA) to perform the needed multiplication and addition operations [2, 6, 9-13] with low power and high performance. MCA-based NN (MNN) architectures require a pair of memristors to store either a positive or a negative synaptic weight. There are different type of MNN. This paper considers multi layer feed forward MNN [2] as opposed to spiking neural networks and recurrent neural network architectures, among other types of neural networks. The feed forward MNN in [9] uses a dual column structure where two adjacent memristors in a row store a synaptic weight. The MCA in [2] uses dual row structure where the two adjacent memristors in a column store a weight value. Both approaches store a weight value in one of the two memristors, and require the other to be in a very high resistive state so that the current through other memristor is negligible. The sign of the weight value determines which memristor is in the high resistive state. Other feed forward memristor-based NN architectures use the Wheatstone bridge [14, 15] instead of the MCA to implement a synaptic weight. Among these approaches, the least power consuming are the dual row MCA architecture in [2] that requires a voltage converter to implement positive and negative weight values and the dual column architecture in [9] that uses an operational amplifier per column.

Architectures as in [14-16] are gaining much attention because the required arithmetic operations can be performed by simple components that use emerging resistive devices. Power dissipation and execution time are drastically lower when compared to multiprocessor-based systems tailored to neuromorphic calculations [17, 18] or to GPGPU-based architectures [19].

This paper presents a dual column feed forward MNN architecture that avoids the operational amplifier of [9].Instead, it uses a spintronic device per neuron to compute the total synaptic current through each MCA column. SPICE-based simulation in 45nm technology shows that the proposed architecture dissipates considerably less power when comparing to [2]and [9]. Experimental results are presented on the benchmark data sets in [20-22].

The paper is organized as follows. Section 2 describes the proposed architecture. Section 3 presents the experimental evaluation of the proposed architecture, and Section 4 concludes the paper.

2. Proposed Architecture

VLSI Circuits and Systems Letter Volume 4 – Issue 4 November 2018

Figure 1 shows the structure of the proposed MCA-based layer in the feed forward MNN. It consists of n rows and 2m columns. Each layer has n inputs that are real numbers in the range [0, 1].There are m neurons, and each neuron has a pair of MCA columns. At the jth pair, there is an interface module (denoted by IM) that generates the total synaptic current into the activation function module . The output of the jth activation function , is also a real number in the range [0, 1]. Each IM is a domain wall spintronic device. In the current implementation, activation function is the sigmoid and is implemented by the circuit in [23]. It is noted that the architectures in [9] and [14] only implement sigmoid activation functions. In contrast, the proposed architecture as well as [2] can accommodate any existing current-based hardware implementation of an activation function, such as the step function in [2].

Each synaptic weight linking the ith neuron and the jth neuron consists of two adjacent memristors and , respectively. Only one of these two memristors is in the off-state. For instance, considering the jth column pair, if the weight is positive, is programmed to have the specific weight value, and is in the off-state. However, if the weight is negative, is programmed to have the weight value, and is in off-state. Let and denote the synaptic current for the positive and negative convolutions in the jth column pair.

(b) Figure2: (a) Proposed spintronic Interface module (IM) (b) Timing Diagram


Each column in the crossbar array of Figure 1 calculates the partial weighted sum of either positive or negative convolutions. The difference between two currents and in the jth column pair is calculated by the IM. This is the jth total synaptic current. Columns and in the jth column pair and the IM are part of the neuron that calculates the total synaptic current for the jth neuron.

Fig. 2 (a) shows the circuit diagram of the proposed IM where V denotes a control voltage. and are the inputs to the IM that determines the total synaptic current . The DW device is a three-terminal device that consists of a thin nano strip between two anti-parallel fixed magnetic layers (PL). This nano strip forms the free magnetic layer (FL). The magnetization of FL determines the resistive state of the device. The transition area between the two PLs is called the DW. The DW can be moved by injecting current along the nano strip. This changes the magnetic orientation of the FL. A fixed magnet and a domain wall strip form the Magnetic Tunnel Junction (MTJ) that reads the resistive state of the device [2, 24].

The operation of the IM is described using three non-overlapping clocks Clk1, Clk2, and Clk3. The duty cycles of each clock are different because the reset, write, and read times of the DW device are different. Let and denote the low and high resistive state of device, respectively. When Clk1 is high, the spintronic device is reset with resistive value

. In this case, the DW is at the center position. When Clk2 is high, the spintronic device is programmed using the total synaptic current .That way, the difference between positive and negative total synaptic current through consecutive columns of the MCA is mapped to a resistive value in the DW spintronic device. When Clk3 is high, the activation circuit is active, and the difference of total synaptic current is mapped to a voltage value.

The current mirrors in the Figure 2 (a) ensures that the range of current generated by the interface module falls into the range required by the activation circuit for reliable operation. The externally supplied negative current amounts to the current through spintronic device when the DW is at the center of the nanostrip. Let and denote the currents through IM when spintronic device has and resistive state, respectively. The value of . Figure 2 (b) shows the timing diagram of the operation of the interface module.

3. Experimental Results A simulator for the proposed architecture has been developed. We consider TiO2 bipolar metal-oxide memristors and

the VTEAM model in [25]. In our simulator, the length and the , memristance boundaries were set to 5nm, 5K , and 5M , respectively. Other memristor parameters were set as in [26]. The switching time was 100ns when the applied voltage was ±1V.Multiple bits of information can be stored in a single cell using different memristance values. Thus, and were implemented with a 5-bit memristive multi-level cell [27-29].

Since the current-voltage relation of a memristor is nonlinear, each level corresponding to a weight value was assigned using the approach presented in [29]. Any level of weight value can be realized by changing the memristance of the memristor gradually with a precise write control signal [27]. We used five different levels to implement 31 weight values. In our simulator, the dimensions of domain wall strip were 100×20×2nm3, the MgO thickness was 1.1nm,the saturation magnetization was 6.8×105 A/m, and domain wall width was15 nm. The DW could be moved from one edge of free layer to the other in 2ns when applying 35μA current.

The proposed interface module (IM), the voltage converter of [31], the operational amplifier-based sigmoidal neuron of [9], and the low power analog sigmoidal neuron of [23] were implemented in 45nm predictive technology. Our experimentation showed that the average power dissipated by [23] was 8μW.

Simulators for the MCA-based feed forward architectures in [2], [9] and non MCA-based feed forward architecture in [14] were also developed in 45 nm predictive technology for experimental comparisons. The simulator for the architecture in [2] was enhanced in order to implement the analog sigmoidal circuitry in [23].Table 1 shows the average power dissipated by the various components in the proposed architecture as well as the MCA-based feed forward

TABLE 1 COMPONENT WISE POWER DISSIPATION

Component Average Power Dissipation


architectures in [2], [9]. Table 1 shows that the power dissipated by the proposed interface circuit was almost the same as the power of the

voltage converter in the architecture of [2]. The proposed dual column architecture had reduced power when compared to the dual column architecture in [9, 16] because the number of voltage converters at any layer is equal to the number of inputs, and the number of IM equals to the number of neurons. The number of neurons in a layer is always less than the number of inputs.

TABLE 2 COMPONENT WISE POWER DISSIPATION

Dataset

Architecture Average Power Dissipation (mW) Power Reduction (%)

Simulation results for the proposed architecture as well as [2] and [9] were obtained in Python for the MNIST dataset [15], American Sign Language (ASL) dataset [16], and the CIFAR10 dataset [17]. MNIST contains 28 × 28 gray scale handwritten images, ASL contains 200×200 RGB images, and CIFAR10 contains 32×32 RGB images. For the MNIST dataset, the NN had 784 input neurons and 10 output neurons. There were three hidden layers with 500, 300, 128 neurons, respectively. For the ASL dataset, the NN had 400,000 input neurons and 24 outputs. There were three hidden layers with 1,000, 500, and 128 neurons, respectively. For the CIFAR10 dataset, the NN had 1024 input neurons and 10 output neurons. There were three hidden layers with 500, 256, and 64 hidden neurons each. Images in both the ASL and CIFAR10 datasets were converted to grayscale image before feeding them into the network.

Table 2 shows the total average power dissipated by the NN architectures in [2] and [9], and the proposed architecture. The total power dissipated by the proposed architecture is the sum of the power consumed by the interface module and the sigmoidal activation function in [18]. The total power by the NN architecture in [2] amounts to the power dissipated by voltage converter and the power by the sigmoidal activation function component [23]. The total power by the NN architecture [9] amounts to the average total power dissipated by the two differential amplifiers. Notice that the power savings over [2] were approximately 19%, 41%, 28% when considering the MNIST dataset, the ASL dataset, and the CIFAR10 dataset, respectively. The power savings over the operational amplifier-based architecture in [9] was 56% for all three datasets. These results exclude the power dissipation on the MCA, which is common to all architectures.

We also provided simulation results for the NN architecture in [14]. It was simulated for a small network consisting of 10 inputs and 4 output neurons. Weights were set between 5K -5M and inputs were in the range [0, 1] V. Even for that small network, the total power dissipation was 230mW. The power dissipated by the sigmoidal neuron alone was 2.06mW. These results show that [14] is not as power efficient as the proposed architecture.

It is noted that the proposed NN architecture had the same classification accuracy as [2, 9] in all benchmarks. In particular, the accuracy was 96%, 70% and 95% for the MNIST, CIFAR10 and ASL datasets, respectively.

4. Conclusion

A low power spintronic circuit has been introduced in order to generate the input current for the activation circuit of an MCA-based neuromorphic architecture. The proposed interface circuit uses the domain spintronic device. It has been experimentally shown that the power dissipation of the proposed neuromorphic architecture outperforms existing architectures with emerging resistive devices.

Reference [1] J. Grollier, D. Querlioz and M. D. Stiles, “Spintronic Nanodevices for Bioinspired Computing,”in Proceedings of the

IEEE, vol. 104, no. 10, pp. 2024-2039, 2016. [2] M. Sharad, D. Fan, K. Aitken and K. Roy, "Energy-Efficient Non-Boolean Computing With Spin Neurons and

Resistive Memory," IEEE Transactions on Nanotechnology, vol. 13, no. 1, pp. 23-34, 2014.


[3] K. Kim, J. Kim, J. Yu, J. Seo, J. Lee, and K. Choi, “Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks,” ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6, 2016.

[4] Z. Li, A. Ren, J. Li, Q. Qiu, B. Yuan, J. Draper, and Y. Wang, “Structural design optimization for deep convolutional neural networks using stochastic computing,” Design, Automation Test in Europe Conference Exhibition (DATE), pp. 250–253, 2017.

[5] H. Chung, S. J. Lee, and J. G. Park, “Deep neural network using trainable activation functions,” International Joint Conference on Neural Networks (IJCNN), pp. 348–352, 2016.

[6] S. N. Mozafferi, K. P. Gnawali, S. Tragoudas, “Aging Resilient Neural Network Architecture ,” IEEE/ACM Symposium on Nanoscale Architecture (NANOARCH), 2018, doi: https://doi.org/10.1145/3232195.3232208.

[7] R. Kumar, S. Sharma, “Hardware Efficient Second Order Implementation of Sigmoid Function using Distributed Arithmetic,”IEEE VLSI Circuits and Systems Letter, vol. 4, Issue-1, pp. 5-10, 2018.

[8] S. Srivastava, S. S. Rathod, “Simulation and Analysis of analog VLSI Silicon Neuron using Carbon Nanotube Field Effect Transistor and 180nm MOSFET Technology,”IEEE VLSI Circuits and Systems Letter, vol. 3, Issue 3, pp. 37-47, 2017.

[9] R. Hasan, T. M. Taha, and C. Yakopcic, “On-chip training of memristor based deep neural networks,” International Joint Conference on Neural Networks (IJCNN), pp. 3527–3534, 2017.

[10] A. Basu et al., “Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions,”IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 1, pp. 6-27, 2018.

[11] Chenchen Liu, Fuqiang Liu, and Hai (Helen) Li. Brain-inspired computing accelerated by memristor technology. In Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication (NanoCom '17), Article 17, 6 pages, 2017.

[12] M. V. Nair, L. K. Muller, and G. Indiveri, “A differential memristive synapse circuit for on-line learning in neuromorphic computing systems,” Nano Futures, vol. 1, no. 3, pp- 035003, 2017.

[13] G. Indiveri, B. Linares, R. Legenstein, G. Deligeorgis, T. Prodromakis, “ Integration of nanoscale memristor synapses in neuromorphic computing architectures,”Nanotechnology, volume 24, Number 38, pp- 384010, 2013.

[14] H. Kim, M. P. Sah, C. Yang, T. Roska, and L. O. Chua, “Memristor Bridge Synapses,” Proceedings of the IEEE, vol. 100, no. 6, pp. 2061–2070, 2012.

[15] S. P. Adhikari, H. Kim, R. K. Budhathoki, C. Yang, and L. O. Chua, “A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 215–223, 2015.

[16] M. Prezois, F. Merrikh-Bayat, B. Hoskins, G. Adam, K. Likharev, and D. Strukov, “Training and Operation of an Integrated neuromorphic network based on Metal-Oxide Memristors,” Nature Letter, vol. 521, no. 1, pp. 61–64, 2016.

[17] M. Davies e.t.al, “Loihi: A Neuromorphic Manycore Processor with On-Chip Learning,” IEEE Micro, vol. 38, no. 1, pp. 82–99, 2018.

[18] F. Akopyan e.t.al “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537–1557, 2015.

[19] E. Lindholm and S. Oberman, "The NVIDIA GeForce 8800 GPU," IEEE Hot Chips 19 Symposium (HCS), Stanford, CA, pp. 1-17, 2007.

[20] Y. LeCun, C. Cortes, and C. J. C. Burges, “The MNIST Database of Handwritten Digits,” [Online]. Available: http://yann.lecun.com/exdb/mnist/

[21] “American Sign Language Translation,” [Online]. Available: https://github.com/mjk188/ASLTranslator/tree/master/TrainData

[22] A. Krizhevsky, “The CIFAR10 dataset,” [Online]. Available: https://www.cs.toronto.edu/ kriz/cifar.html [23] G. Khodabandehloo, M. Mirhassani, and M. Ahmadi, “Analog Implementation of a Novel Resistive-Type Sigmoidal

Neuron,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 4, pp. 750–754, 2012. [24] K. P. Gnawali, S. N. Mozaffari and S.Tragoudas, “Low Power Spintronic Ternary Content Addressable Memory”,

IEEE Transaction on Nanotechnology, 2018, doi: 10.1109/TNANO.2018.2869734. [25] S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM: A General Model for Voltage-Controlled

Memristors,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 786–790, 2015. [26] S. Kvatinsky, K. Talisveyberg, D. Fliter, A. Kolodny, U. C. Weiser, and E. G. Friedman, “Models of memristors for

SPICE simulations,” IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp. 1–5, 2012. [27] F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, “High precision tuning of state for memristive devices by

adaptable variation-tolerant algorithm,” Nanotechnology, vol. 23, no. 7, pp. 1–7, 2012.


[28] S. Yu, Y. Wu, and H.-S. P. Wong, “High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm,” Applied Physics Letter, vol. 98, 2011.

[29] L. Zhang, D. Strukov, H. Saadeldeen, D. Fan, M. Zhang and D. Franklin, "SpongeDirectory: Flexible sparse directories utilizing multi-level memristors," International Conference on Parallel Architecture and Compilation Techniques (PACT), pp. 61-73, 2014.

[30] M. Wu, W.-Y. Jang, C. Lin, and T. Tseng, “A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture,” Semiconductor Science and Technology, vol. 27, no. 6, p. 065010, 2012.

[31] K. I. Hwu, W. C. Tu, and Y. H. Chen, “A novel negative-output KY boost converter,” International Conference on Power Electronics and Drive Systems (PEDS), pp. 1155–1157, 2009.

About the Authors Krishna Prasad Gnawali([email protected]) received his bachelors degree in Electronics and Communication Engineering from Tribhuvan University, Nepal in2014. Since 2016, he is a Ph.D. student in the Department of Electrical and Computer Engineering at the Southern Illinois University Carbondale. He is a member of the Electronic Design & Test Automation Lab, where he is searching for design and test of emerging technologies. His research interests include VLSI Designand Test Automation, RTL-level test and verification, Neuromorphic computing, emerging technologies (memristors, spintronics), and Logic in memory processing.

Seyed Nima Mozaffari([email protected]) received his M.S. degree from School of Electrical and Computer Engineering at the University of Tehran in 2010, and PhD degree in Electrical and Computer Engineering in 2018 from Southern Illinois University Carbondale. His research interests include VLSI Design and Test Automation, RTL-level test and verification, Neural network and neuromorphic computing, emerging technologies (memristors, spintronics), aging-aware design and analysis Synthesis of Threshold Logic Gates, and Synthesis on non-boolean near threshold functions. He is a reviewer in IEEE journals and conferences Spyros Tragoudas ([email protected]) received his Diploma in Computer Engineering from the University of Patras, Greece in 1986, and M.S. and PhD degrees in Computer Science from the University of Texas at Dallas in 1988 and 1991. He is Professor and Department Chair at the Electrical and Computer Engineering (ECE) Department, Southern Illinois University at Carbondale (SIUC), and the Director of the National Science Foundation (NSF) Industry University Cooperative Research Center (IUCRC) on Embedded Systems at the SIUC site. He has held prior appointments with the faculty of the ECE Department at the University of Arizona, and with the faculty of the Computer Science Dept. at SIUC. His current research interests are in the areas of VLSI design/test automation and embedded systems. Dr. Tragoudas has published over two hundred and fifty papers in peer-reviewed journals and conference proceedings

as well as book chapters in these areas. He has received three outstanding paper awards, and has directed many PhD dissertations and MS theses. His research has been funded by federal agencies and industry. He has served and current serving on the editorial board of several journals, the technical program committees of many conferences.

••

•

ieee-tcvlsi.org

Features

Evaluation of Ultra-Low Power Techniques to 10T Junction Less Double Gate Hybrid Full Adder (10TJLDGHFA)

Priyank Sharma and Sanjay Sharma Electronicsand Communication Engineering Department, Thapar University,Patiala, India

Abstract – In the modern scenario, the mountingutilization of nanoelectronic circuit devices, reducing power and leakage consumption haveposed a major challenge in the present VLSI circuit & system design. Reducing supply voltage with scaling threshold voltage is an efficacious approach to get soothing powerand sharp execution circuits. In this paper, we propose a novel10T Hybrid Full Adder (HFA) cellby merging dual logic approach and Negative Differential Forbearance (NDF) device, comprehended in a completely diminished Silicon on Insulator (SoI) Junction-Less Double Gate (JLDG)MOSFET methodology. We analyzed these 10TJLDGHFA (10T Junction-Less Double Gate Hybrid Full Adder) cell with varied Ultra Low Power Techniques (ULPT)of MTCMOS, Tri-Mode MTCMOS and SVL. With typically wrought circuit techniques, it ensures to diminish the leakage parametersin an Idle circuit. Simulated low power results show reduction in leakage power by 24.09% while the leakage current is reduced by 24.11%. Power & Current dissipation are concentrated by 98.55% in Tri Mode MTCMOS as compared to MTCMOS and SVL techniques. These proposed schematics and ultra-low power techniques have been implemented through Cadence Virtuoso Tool. Keywords:10T Junction-Less Double Gate Hybrid Full Adder (10TJLDGHFA), Low Power Techniques, MTCMOS, Tri Mode MTCMOS, SVL. 1. INTRODUCTION

Power has enhanced but withforemost apprehension, correlated to the design of digital integrated circuits, in case of gate lengths, wearing the appropriate nanoscale transistor Low-level voltages and weak electrostatic control Channel device. Various vectors have been improved according to the technology to circuit (power gating techniques, pass transistor logic), to multi core system (reconfigurable platforms) and to software (energy effective code) [5]. In this paper, we focus on Ultra-Low Power (ULP) [4]- [6] circuit structures in low, power pass transistor logic circuits with power gating techniques in SOI [8]and JLDG MOSFET devices for reducing leakage power, current and power dissipation [1]. Power Dissipation (PD) can be moderated by scaling down the supply voltage. Scaling linear voltage supply of attribute size evolved from half-micron technology. But the scaling of power supply make-believes the rapidity of the circuit, essential to retain time designs of low power [7] and high speed design networks. MTCMOS, Tri Mode MTCMOS & SVL Technology [2]-[3]have high speed logic gates , emerging as a good low power alternative as against the customary CMOS [4]. Tri Mode MTCOS is one of the proficient circuit-level techniques that feedson high execution and low power [6] designs with both low voltage and high threshold transistors. This technique is used for reducing the sub-threshold currents in standby approach whereas preserving the circuitry performance. In the proposed work , we have designed a new effective circuitry of Ultra Low Power (ULP) [4] 10T Hybrid Full Adder (10THFA) using low power techniques to Negative Differential Resistance (NDR) [8] device appreciated in a Fully Depleted (FD) Silicon on Insulator (SoI) Junction Less Double Gate (JLDG) MOSFET technology [8]. This technology is used to squeezethe current peak in NDR deviceand tocompel it to restore weak logic levels at outputs of the two low power sum and carry logic. Moreover, this process speeds up the decisive shift in the end.

2. 10T HYBRID FULL ADDER

The Junction Less Dual Gate MOSFET connects the two transistors in combination, parallel to their supply and connects the drains together. Junction Less Dual Gate can be categorized into two types based on the MOSFET Gate bias [4] [6]. When the front and back gate areasare connected to the unit, the earliest is achieved and is referred to as the three terminal device as shown in Fig.1. This system is exploited as an alternative for a single gate transistor. The second type can be achieved through independent control over the gate. ThroughJLDGMFET, [8] the execution and operation ofHFA improves with regard to reducing the power and leakage effects [1].

Fig. 1: Junction Less Double Gate Hybrid (10T) Full Adder

Where JLDG is derived as:

3. MTCMOS (Multi Threshold Complementary Metal-Oxide-Semiconductor)

While fabricatingthe physical structure of a MTCMOS circuit, it is imperative that the active current passing through transistors stops in active mode, considering the electro exodus in the wire [10]. The channel width is also important because of high power. There is a compromise between local and global standby devices. The MTCMOS tactic is stress-free on combinational systems, whereas it is difficult on sequential systems. If power supply is discontinued, the entire data accumulated in the circuit will be lost. This is the chief concern with MTCMOS circuits. To address this problem, a complex synchronization system or an additional circuit is used [10]. Due to these added factors, performance of the circuit is degraded. This also requires a large surface to terminatein addition to a high power loss. MTCMOS (multi-level CMOS) reduces drain current during standby and reaches high speeds in active mode.

Fig. 2: Block Diagram of 10THybrid Full Adder under MTCMOS Technique

MTCMOS Logic is an efficient leakage control technique. Multi-Level Logic uses MOS Vth and Vth transistors to meet low and high power requirements. Among the logic circuit and power supply rails, high-speed Vth transistors are used. These standby transistors are activated by standby signals and are used by high level transistors to reduce power consumption in a standby mode. In the logic circuit, Vth transistors are used to increase the performance in active mode. Fig.2 shows the general structure of MTCMOS circuits [10]. There are high transistors between PMOS and NMOS Vth Logic circuit and feed rails. High level transistor triggers an active mode for high logon signal real logic operation. Three V transistors are suspended at standby to destroy the logic circuit from feed rails. This reduces the sub-limit leakage during standby. MTCMOS has an effective technology for low-power and high-speed applications. Size of high level transistors is one of the tasks which analyses a circuit design with MTCMOS architecture [10] where 10TJLDGHFA is connected with MTCMOS technique in a series with a combination of PU PMOS as Vdd and PD NMOS as Vss as shown in Fig.2.

4. TRI MODE MTCMOS (Multi Threshold Complementary Metal-Oxide-Semiconductor)

Fig. 3: Block Diagram of 10TJLDGHFA under Tri mode MTCMOS Technique

The technique with three effective modes of low noise MTCMOS is called tri-mode MTCMOS. Tri mode

MTCMOS circuit works in three different modes: SLEEP, PARK AND ACTIVE [10]. When the three-mode MTCMOS circuit is inactive, sleep transistors (basement and parking) are interrupted to keep the circuit in low drain SLEEP mode. In base SLEEP mode, the base virtual line increases to almost VDD supply voltage. The actual source proficient in MTCMOS circuit is entirely wrinkledat voltage 0V [10]. Lower-level leakage issue produced by low-block circuit voltage is suppressed in SLEEP mode. Block diagram of Tri mode MTCMOS-JLDGHFA is shown in Fig.3. 5. SVL (Self Controllable Voltage Level) TECHNIQUE

An SVL method technique is used, where the charge circuit is distributed with maximum power supply voltage in active mode while retarding the flow by reducing the leakage current of the gate. Therefore, in standby mode, it has a slightly lower and relatively high voltage.Charging the voltage, using the switch as VDS turns off MOSFETs, will eventually reduce Vsub while V increases accordingly, as a current sub-limit drop [12]. Here, there are three techniques in SVL: 1) USVL 2) LSVL 3) ULSVL. It is the combination of Upper Lower SVL techniques asdepicted in Fig.4. The ULSVL is a technique used in standby mode to reduce the leakage power as compared to other techniques. In Upper SVL, the PU PMOS is connected parallel to the series combination of PD NMOS transistors [12] where Vdd is applied [2]. In Lover SVL, the PD NMOS is connected parallel to the series combination of PU PMOS transistors. Where Vss is applied. The 10T JLDGHFA is connected in series combination using the Upper & Lower SVL method.

Fig. 4: Block Diagram of 10TJLDGHFA under SVL Technique

6. 10TJLDGHFA RESULTS IN VARIOUS LOW POWER TECHNIQUES AND PARAMETERS

TABLE 1 THE LEAKAGE PARAMETERS OF 10TJLDGHFA IN VARIOUS LOW POWER TECHNIQUES

Leakage Current Leakage Power MTCMOS 5.93E-07 4.15E-07

TRI Mode MTCMOS 4.50E-07 3.15E-07 SVL 5.97E-07 4.18E-07

Here, results show that leakage power is shrunken to 30% of the leakage current in MTCMOS technique andleakage

power is shrunkento 29.9% of the leakage current in Tri mode MTCMOS technique [10]. Leakage power is reduced to 30% of the current dissipation in SVL technique [9]. Moreover, in an average condition, Tri mode MTCMOS technique is much efficient than MTCMOS and SVL technique. Results are shown in table 1 and 2 as well as graph 1 and 2.

Graph 1: Graphical Representation of Leakage Parameters of Low Power Techniques

0.00E+001.00E-072.00E-073.00E-074.00E-075.00E-076.00E-077.00E-07

MTCMOS TRI Mode MTCMOS SVL

Leakage Parameters

Leakage Current Leakage Power

Static power insinuates to power dissipation which ensues to the leakage current and the voltage by CMOS transistor. Dynamic power consumption minimizes static power, but transistor size persists tominimize while the static power may assailpower dissipation. Significantly, the techniques of MTCMOS, Tri Mode MTCMOS and SVL can reduce the power dissipation [10] [12]. Power Dissipation is obtained as:

Where Current Dissipation is gained as:

TABLE 2 THE DISSIPATION PARAMETERS OF 10TJLDGHFA IN VARIOUS DU TECHNIQUES

Current Dissipation (A) Power Dissipation (W)

MTCMOS 9.58E-09 6.71E-09

TRI Mode MTCMOS 1.38E-10 9.69E-11

SVL 1.39E-09 9.73E-10

Results depict that power dissipation is shrunkento 29.9% of the current dissipation in MTCMOS technique. Power dissipation is contracted to 29.78% of the current dissipation in Tri mode MTCMOS technique [10]. Power dissipation is shriveled to 30% of the current dissipation in SVL technique [9]. Moreover, in an average condition Tri mode MTCMOS technique is much competent than MTCMOS and SVL technique [12].

Graph 2 Graphical Representation of Dissipation Parameters of Low Power Techniques

7. CONCLUSION This paper has presented ultra-low power techniques (MTCMOS, Tri Mode MTCOMS & SVL) to 10T Hybrid Full Adder (HFA) along with Junction Less Double Gate (JLDG) MOSFET. Moreover, after assigning these techniques we scrutinized the parameters of leakage current & voltage and power dissipation. Hence, as per our results, we conclude that Tri Mode MTCOMS technique is far more effective in diminishing the leakage current & voltage and power dissipation as compared to MTCOMS and SVL techniques. REFERENCES [1] Shyam Akashe, Sushil Bhushan and Sanjay Sharma, “High Density and Low Leakage Current Based 5T SRAM Cell

Using 45nm Technology,” Romanian Journal of Information Science and Technology, vol.15, no.2, pp. 155-168, Dec. 2012.

0.00E+002.00E-094.00E-096.00E-098.00E-091.00E-081.20E-08

MTCMOS TRI Mode MTCMOS SVL

Dissipation

Current Dissipation (A) Power Dissipation (W)

[2] G.Sushma, V.Ramesh, “Low Power High Speed D Flip Flop Design usingImproved SVL Technique” IEEE Fifth International Conference on Recent Trends in Information Technology 2016.

[3] V.LeelaRani, Dr.M.MadhaviLatha, “DESIGN OF MTCMOS LOGIC CIRCUITS FOR LOW POWERAPPLICATIONS” International Journal of Engineering Science and Technology (IJEST) Vol. 6 No.7 Jul 2014.

[4] S. Wairya, Himanshu Pandey, R. K. Nagaria and S. Tiwari, (2010) “Ultra Low Voltage High Speed 1-Bit CMOS Adder,” in Proceedings of IEEE International Conference on Power, Control and Embedded System (ICPCES’10),India, pp. 1-6.

[5] Shyam Akashe, Sanjay Sharma, “Low Power SRAM Cell Design based on 7T Configuration” International Electronic Engineering Mathematical Society IEEMS” vol. 4, pp. 11-18, Mar. 2010.

[6] Anuj Kumar Shrivastava, Shyam Akashe, “Design High performance and Low Power 10T Full Adder Cell Using Double Gate MOSFET at 45nm Technology” IEEE International Conference on Control, Computing, Communication and Materials (ICCCCM) 2013.

[7] ShyamAkashe, Sanjay Sharma, “Low Power SRAM Cell Design based on 7T Configuration” International Electronic Engineering Mathematical Society IEEMS” vol. 4, pp. 11-18, Mar. 2010.

[8] I. Hassoune, X. Yang, I. O'Connor and D. Navarro, “Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance”IEEE Circuits and Systems and TAISA Conference, 2008.

[9] Shyam Akashe, Meenakshi Mishra, and Sanjay Sharma, ” SVL circuit for low power high speed 7T SRAM cell at 45nm technology” proc. of IEEE International Students Conference on Engineering and Systems (SCES-2012), pp.1-5, 2012.

[10] Priyanka Atre, Vaibhav Neema and Shubham Atre, “Evaluation of MTCMOS Technique with ParkMode On chain of 2 Input CMOS NAND Gate”IEEE International conference on Information, Communication, Instrumentation and Control (ICICIC-2017).

[11] V. Neema, S.S.Chouhan and S. Tokekar, “Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistors Stack”, IETE Journal of Research, vol. 56, no. 6, pp 350-354, 2010.

[12] Hemanth Kumar C S, Kariyappa B S, “Analysis of Low Power 7T SRAM Cell Employing Improved SVL (ISVL) Technique” IEEE International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques (ICEECCOT-2017).

[13] Amin Bazzazi, AlirezaMahini and JelvehJelini, “Low Power Full Adder Using 8T Structure” Proceedings of the International Multi conference of Engineers and Computer Scientists, Vol II, 2012.

[14] SubodhWairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, (2012) “Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design,” Hindawi journal of VLSI Design, Vol. 2012, Article ID 173079, 18 pages.

Author’s Biography

Priyank Sharma received his Bachelor’s degree in Electronics and Instrumentation Engineering from Uttar Pradesh Technical University, Luck now and Master’s Degree in Electronics and Communication Engineering from Shobhit University, Meerut in 2004 and 2010 respectively. Currently, he is pursuingPh.D.in the area of VLSI design from Thapar University, Patiala. His research interest includes Low power VLSI Design, Integrated Circuits and Electronic Measurements.

Dr. Sanjay Sharma was born on 2nd October 1971. He is currently working as an Associate Professor in Electronics and Communication Engineering Department of Thapar University, Patiala, India. He has done his B.Tech. in ECE from REC in 1993, Jalandhar, M.Tech. in ECE from TTTI, Chandigarh in 2001 and Ph.D. from PTU, Jalandhar in 2006. He has completed all his education with honours. He has published many papers in various journals and conferences of international repute. He has to his credit the implementation of research projects worth 12,000 USD. His main interests are VLSI Signal Processing, Wireless System Design using Reconfigurable Hardware, Digital communication Channel Coding, etc.

ieee-tcvlsi.org

Features Design and Analysis of SOI FinFET Based Three Stage OTA with Nested Gm-C Frequency Compensation

Abstract

1. Introduction


2. SOI FinFET device structure

Wfin= 2Hfin+Tfin Hfin

Wfin 2Hfin +Tfin n

fin

3. Preliminary Analysis

+Av2

gm2

+Avf1

-Avf2

-Av1 -Av3Vin Vout

Cm1

Cm2

gmLgm1

gmf2

gmf1


Lmmmmmmmmmmm

mmm

CCCsgCCsggsCggggggsH

wwmi

mii C

gw

Lm

mm C

ggkC

Lm

mm C

gg

kkC


4. Design of SOI FinFET based three stage OTA with NGCC Frequency Compensation

sww

sw

swA

AsHv

v

mi

mii C

gw

GBw

kww

GBww

GBw

PM

wk

kw


Lm Cwg

m

p

nm g

kkk

kg

m

n

pm g

kk

kg

DSATmD

VgI

Dn

m

IKg

LW

LW


minV+maxVmaxVVKI

LW

LW

nth,pthinDDp

LW

LW

LW

DD II

LWkn

nthssinDS VIVVsatV

satVKI

LW

LW

LW

DSp

pDm KL

WIg

DD II

Dp

m

IKg

LW

LW

LW

gg

LW

LW

m

m

LWK

gIp

mD

LW

LW

LW

LW


satVgI DSmD

Dp

m

IKg

LW

LW

II

LW

D

D

Lm

mm C

ggkC

Lm

mm C

gg

kkC

5. Simulation Results and Discussion


1 10 100 1k 10k 100k 1M 10M 100M 1G

50

60

70

CMRR= 72.11 dB

CMRR

[dB]

Frequency [Hz]

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06-1.2

-0.9

-0.6

-0.3

0.0

0.3

0.6

0.9

1.2

Out

put V

olta

ge [V

]

Input Voltage [V]

Output Voltage [V]

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G 100G-75

-50

-25

0

25

50

75

100 Gain = 90.67 dB

Gai

n [d

B]

Frequency [Hz]1 10 100 1k 10k 100k 1M 10M 100M 1G

-200

-150

-100

-50

0 Phase margin = 64.35 deg

Phas

e [d

eg]

Frequency [Hz]


-1.0 -0.5 0.0 0.5 1.0

0

10

20

30

40

Dra

in C

urre

nt in

M6

[uA]

Input Voltage [V]

-1.0 -0.5 0.0 0.5 1.0

-1.0

-0.5

0.0

0.5

1.0

Out

put V

olta

ge [V

]

Input Voltage [V]


6. Conclusion

Reference

MicroElectronic Engineering

IEEE Transactions on Electron Devices

Solid-State Electronics

IEEE Transactions on Circuits and Systems-I Regular papers

IEEE Transactions on Circuits and Systems-I Regular papers

IEEE

Transactions on Circuits and Systems-I Regular papers

IEEE Transactions on Circuits and Systems-I Regular papers IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications


IEEE

Transactions on Circuits and Systems Applications -I Regular papers,

IEEE Journal of Solid-State Circuits

IEEE Journal Solid-State Circuits IEEE Transactions on Circuits Systems –II: Analog Digital Signal Processing

IEEE Transactions on Circuits and Systems –II: Express Briefs,

IEEE Transactions on Circuits and Systems -I Regular papers,

InternationalJournal of Circuit

Theory and Applications

InternationalJournal of Circuits, Systems and Signal Processing

Journal of Semiconductor

Technology and Science IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications

IEEE Transactions on Circuits and Systems –II: Express Briefs,

IEEE VLSI Circuits and Systems Letter



IEEE International Conference on Electron Devices meeting


Solid State Electronics

IEEE Transaction on Electron Devices



Microelectronics Journal


IEEE Journal of Solid-State Circuits

Design of Different Reversible Logic Gate with Improved Parametric Attributes using GDI Technique Mayank Kumar Singh and Rangaswamy Nakkeeran Department of Electronics Engineering, Pondicherry University, Pondicherry, India Abstract- In today’s world, development in the area of very small scale device technology attempts to minimize the power issues of logic circuits. A reversible logic gate is a n×n device with a one-to-one mapping between inputs and outputs. A unique output vector is produced by the reversible circuit for each input vector. In this paper, a new reversible logic gate called MN Gate (MNG) is proposed. A set of benchmark circuits is implemented using the proposed MNG gate. The proposed design is optimal in terms of count of reversible gates, garbage outputs, constant inputs, quantum cost and delay when compared to the existing circuits. The proposed gate is designed using Gate Diffusion Input (GDI) technique. The design is simulated in Xilinx 14.7 Spartan 3e platform and the layout is generated using Microwind 3.8 and DSCH 3.8 in 45 nm technology. The work has been done for making the design optimal in terms of delay, power and area for low power VLSI applications.

1. Introduction For all the talk about computing unrestricted energy costs, the technical group doesn’t coherently work to lower them. Vacuum tubes were costly and fickle in the early days of computing, so Boolean logic circuits were designed to decrease the number of tubes. This design style has not been modified over the years, even though we now put so many transistors on a chip, we have to turn most of them off to avoid overheating. Reversible logics are widely used nowadays as it has potential to reduce the power dissipation of the circuits [2]. For designing quantum arithmetic components, reversible logic circuits are being used. Reversible computing entails that no information about the computational situations can ever be lost, so we can redeem any earlier stage by computing backwards or un-computing the results [10]. This is stated as logical reversibility [9]. Reversible logic is the leading edge for the fortune of electronics that stands on quantum computing [6]. According to Landauer’s principle, the loss of one bit of information dissipates kTln2 joules of energy, where k is the Boltzmann’s constant and T is the absolute temperature at which the operation is being performed [1]. In 1973, Bennett, explained that reversible circuits can be used to avoidkTln2 joules of energy dissipation [2]. The number of garbage outputs, constant inputs and reversible gates play an important role in optimizing the computation in reversible logic circuits [5].

2. Basic Reversible Logic Gates The primitive reversible logic gates are denominated as Feynman, Fredkin, Toffoli and Peres gates [4],[10]. Feynman gate has 2×2 matrix and others have 3×3 matrix of inputs and outputs. The quantum cost of each elementary gate is different such as 1, 5 and 4, respectively excluding the Toffoli gate. The quantum cost for Toffoli gate is not defined [3].These are called elementary reversible gates because all other reversible logics can be realized using them. These gates are not adequate enough to employ large reversible circuits, so we have to cascade them to realize large reversible circuits. Cascading of gates escalates the power dissipation. Thus, there is a huge requirement of those gates that can generate functions by their own. In this frame, R1 and R2 were developed [7]. They have three input and output vectors alike Fredkin, Peres and Toffoli. Hence, the elementary reversible gates are comparable with R1 and R2 in the reference of quantum cost, count of garbage outputs, constant inputs and reversible gates required.R1 and R2 surpass the existing gate in terms of quantum cost, but are not adequate enough for all basic logic gates development.

3. The GDI Technique GDI technique is extensively used for low power designs which solves most of the problems mentioned above [9],

[11]. It implements a wide range of logics using two transistors only. GDI is more optimum for the design of fast, low power circuits, using least number of transistors (as compared to CMOS and existing PTL techniques), while improving power characteristics.GDI cell shown in Fig. 1 consists of 3 inputs - G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS) and N (input to the source/drain of NMOS).The terminal D is acting as the output terminal as depicted in Fig. 1[11]. The functions obtained from the GDI cell are F1, F2, OR, AND, MUX and NOT as shown in Table 1.The GDI functions provided in table 1 are the elongation of a single input CMOS inverter into a triple input GDI cell in order to implement intricate logic functions with a minimal number of transistors. Any n-input CMOS structure to an (n+ 2) input GDI cell can be obtained by using P as input instead of supply voltage in the PMOS block of a CMOS structure and an N input at the place of ground in the NMOS block. This evolved implementation can be represented by the following logic expression [12].

F is a logic function of an NMOS block not of the whole original n-input CMOS structure. Shannon expansion explains the above method, where any function F can be written as follows:

= The output functions of basic GDI cell shown in Table 1 are based on Shannon expansion where A, B and C are

inputs to G, P and N respectively as [12],

TABLE 1 GDI FUNCTION AND TRUTH TABLE

Figure 1: GDI cell

4. Proposed Design The new design of reversible logic gate, namely, MNG, proposed in this letteris shown in Fig 2. It is capable of designing all basic logic gates and some of the combinational logic circuits. This proposed logic gate is comparable to elementary gates in terms of quantum cost, count of garbage outputs, constant inputs and gates required and also surpasses in logic and delay parameters. The power dissipation reduces when the circuit is designed with PTL. Consequently, operational time of the circuit gets reduced and produces a faster response [5]. An important aspect is that all energy is pumped into the inputs themselves. The truth table for the proposed design MNG is given in Table 3. It illustrates that there are significant reversible mapping between (1, 4, 1), (2, 7, 2) and (3, 6, 5, 3) compared with previous logic gates that had two reversible mappings, MNG has three reversible mappings between the input and output vectors.

TABLE 2INPUT COMBINATIONS

TABLE 3 TRUTHTABLE FOR MNG A

Figure 2: Block diagram of MNG

N P G D FUNCTION 0 B A A'B F1 B 1 A A'+B F2 1 B A A+B OR B 0 A AB AND C B A A'B+AC MUX 0 1 A A' NOT

Operation OR, NOR

NAND AND, DEMUX

NOT XOR, HS

Constant i/p

A=0 A=1 B=0 B=1 C=0

MNG

S.No.

INPUT OUTPUT

Din A B C P Q R Dout1 0 0 0 0 0 0 0 0 2 1 0 0 1 1 0 0 4 3 2 0 1 0 1 1 1 7 4 3 0 1 1 1 1 0 6 5 4 1 0 0 0 0 1 1 6 5 1 0 1 0 1 1 3 7 6 1 1 0 1 0 1 5 8 7 1 1 1 0 1 0 2

D

N

G

P=A'C+BC'

Q=A'B+AC

R=AB'+BC'

B

C

Figure 3: Schematic of the proposed MNG Din and Dout are the decimal equivalent for input and output. Fig. 3 explains the NAND implementation of the proposed MNG. It tells about the number of NAND gates and transistors used for implementation. MNG is competent itself of developing all the basic logic gates along with some combinational circuits such as 2:1 MUX, 1:2 DEMUX and Half Subtractor. Table 2 elaborates about the constant input needed for implementing the circuits. Besides NOR, the numbers of gates required for implementing the circuits are only one because NOR requires one more NOT gate for performing its equivalent operation. For implementing NOT gate with MNG, the second input is taken as constant ‘1’. For AND gate, second input is taken as ‘0’.

The first input is taken as ‘0’ for OR gate and ‘1’ for NAND gate. The XOR operation is performed by taking the last input as ‘0’. The second output of MNG produces 2:1 MUX by taking the first input as a select line and second input as ‘0’. The design can be changed into 1:2 DEMUX with the first and second outputs as DEMUX output. The design of half subtractor can be implemented by taking the third input as 0. The design using 2:1 MUX is elaborated. In this design, three 2:1 MUX and two NOT gate is used for the implementation of MNG. F0, F1 and F2 show the outputs as P, Q and R. Verilog code is written for Xilinx platform and verified the same using DSCH 3.8 that gives the Verilog file to generate the layout (metal diagram).

5. Simulation Results Simulation results can be observed from Fig. 4(a), (b), (c), (d), (e) and (f) for NAND, AND/1:2 DEMUX,

EXOR/HALF SUBTRACTOR, NOT, NOR and OR gate respectively. It is first time that reversible logic gate is implemented using GDI technique [11]. The simulation is performed on ISE design tool 14.7(Xilinx). 2:1 MUX can also be simulated in the same manner. In Fig. 4, the X-axis represents the time factor and Y-axis represents the input/output. The layout is generated using Microwind 3.8 and the Verilog file is developed using DSCH 3.8. Fig. 5 shows the GDI implementation of MNG which uses 18 transistors and Fig. 6shows the layout. This design uses 48 transistors when implemented in CMOS. The number of transistors required to implement the proposed MNG with GDI technique is very less that improves the power, delay and area.

A

C

BC

B

AC

AB

[1][2]

[3]

[4]

[5]

[6]

[7]

1

1

P

Q

R

(a)

(b)

(c)

(d)

(e)

(f)

Figure 4: (a) NAND Gate, (b) AND/1:2 DEMUX, (c) EXOR/HALF SUBSTRACTOR,

(d) NOT Gate, (e) NOR Gate and (f) OR Gate

Figure 5:GDI implementation of new reversible logic gate

Figure 6: VLSI Layout

In Table 4, it is illustrated that the number of PMOS and NMOS is ‘9’. Total number of transistors used is 18. Supply voltage is taken as 1 V and the current is found to be 1nA. The delays of different outputs P, Q and S are given in the Table 4. The values of start time (TS), rise time (TR), time pulse (TP) and fall time (TF) are taken from the simulation.

TABLE 4 LAYOUT PROPERTIES Parameters Values

VDD

(V) 1

IDD

(nA) 1

Frequency (GHz) 2.5 Dynamic power 471.6 (nW) or 0.4716 (μW )

Static power 1 (nW) Load capacitance (fF) 188.64

PMOS NMOS No. of transistors 9 9

Gate Capacitance (fF) 0.12 2.11 Metal capacitance (fF) 1.33 13.24 No of metal contacts 18 18

Time Out 1 Out 2 Out 3

TPHL

(ps) 24.8 24.8 375

TPLH

(ps) 24.8 24.8 175

Avg. delay(ps) 24.8 24.8 275 Start time TS (ns) 0.95 2.980 2.900 Rise time TR (ns) 0.050 0.050 0.050

Time pulse TP (ns) 0.950 0.950 0.950 Fall time TF (ns) 0.050 0.050 0.050

(a)

(b)

(c)

Figure 7: (a), (b), (c) Comparison of proposed and existing [7] reversible logic gate

6. Comparative Study From Fig. 7 (a), it is given that number of slices for the design is 1, which is better than R2 [7].The number of IOs is 6 and LUT is 2.The MNG is compared with R1 & R2 and they are considered from the literature because these are recently proposed reversible logic gates with better performance than previously existing reversible logic gates in terms of logic and route calculations.

TABLE 5 COMPARISON OF MNG WITH EXISTING REVERSIBLE LOGIC GATES (R1 & R2) Design Existing

(R1,R2) [7] Existing

[11] Proposed (MNG)

Operation AND only - AND,OR,XOR,NAND,NOT NOR,XNOR 2:1MUX 1:2DEMUX,HS No. of gates

1 - 1 2 2 1

Garbage o/p

2 - 2 2 1 1

Constant i/p

1 - 1 2 0 1

Logic (%) 73.4 - 77.0 Route (%) 23.6 - 23.0

Slices 1,2 - 1 LUT 2,3 - 2 IOs 6 - 6

Quantum cost

5,6 - 6

Power - 18mW 0.4726μw Area(μm2) - - 758.4 Delay (ns) 7.077 7.8 0.0231

Table 5 shows that the IOs are 6 for R1, R2 and MNG. Thus they are comparable to each other. One can also see that the delay gets reduced as shown in Table 5. It puts some light on the parametric comparision of MNG with R1, R2.The count of gate for all the operations is 1 except for NOR and XNOR as these logics use one extra NOT gate. The number of garbage output is two maximally which ensures least garbage data collection at the output. The constant input is applied to perform some specific operations and the maximum value is two for NOR and XNOR, otherwise it is one or zero. The quantum cost for MNG is six that is dipicted in Fig.7(c) [6]. The delay is reduced to very less and its value is 0.1082 ns when compared with existing i.e 7.8 ns as shown in Fig.7(b).

7. Conclusion In this letter, a new reversible gate called the MNG has been designed and implemented for realization of different types of combinational circuits like half subtractor, multiplexer, de-multiplexer and basic logic gates. These circuits have minimum quantum cost and garbage outputs and logic utilization with low power consumption and lesser delay. This reversible circuit can be used for designing other logic circuits with better parametric attributes. The future scope of this design includes its implementation in the realization of subsystem used for optical and quantum computing devices.

References [1] R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM Journal of Research

and Development, 5, pp. 183-191, 1961. [2] C.H. Bennett, “Logical Reversibility of Computation”, IBM J. Research and Development, pp. 525-532, Nov.

1973. [3] E. Fredkin, T. Toffoli, “Conservative Logic”, Intl. Journal of The-oretical Physics, pp. 219-253, 1982. [4] Peres, “Reversible Logic and Quantum Computers”, Physical review A, 32, pp. 3266- 3276, 1985. [5] D. Markovic, B. Nikolic and V.G. Oklobdzija, (2000) “A general method in synthesis of pass transistor

circuits”, Microelectronics Journal 31,pp. 991-998. [6] M. Nielsen and I. Chuang, “Quantum Computation and Quantum Information”, Cambridge University Press,

2000. [7] M. Mohammadi and M. Eshghi, “On figures of merit in reversible and quantum logic designs”, Quantum

Information Processing, 8(4):297318, Aug. 2009. [8] Bennett, C. “Logical reversibility of computation” IBM J. Res. Dev. Vol. 17, pp. 525–532, Nov. 1973. [9] Michael P. Frank, “The future of computing depends on making it reversible”, IEEE Spectrum, pp. 32-37, 25th

Aug. 2017. [10] Umesh Kumar, LavishaSahu, Uma Sharma, “Performance Evaluation of Reversible Logic Gates”, IEEE,

2016.

[11] Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner, “Gate-Diffusion Input (GDI) - A technique for low power design of digital circuits: analysis and characterization”, IEEE International Symposium on Circuits and Systems, Aug. 2002, USA.

[12] E. Shannon and W. Weaver, “The Mathematical Theory of Information”. Urbana-Champaign: University of Illinois Press, 1969.

Authors Biography

Dr. R. Nakkeeran has received his B.E in Electronics and Communication Engineering from Madras University in 1991 and M.E in Electronics & Communication Engineering with diversification in Optical Communication from Anna University 1995. He received his Ph.D. degree from Pondicherry University in 2004. His areas of interest are Antennas, Optical Communication and Networks, Ultra Wide Band Systems and Wireless Communication. He is currently working as an associate professor and head in the dept. of Electronics Engineering at Pondicherry University, Puducherry, India.

Mayank Kumar Singh has received his B.Tech in Electronics and Communication Engineering from Invertis University, Bareilly, UP in 2015 and his M.Tech in Electronics and Communication Engineering from Pondicherry University, Puducherry, India in 2018. Currently he is pursuing Ph.D. in the department of Electrical Engineering & Computer Science at Indian Institute of Science Education & Research (IISER), Bhopal, India. His areas of interest are Digital electronics, VLSI designing and Quantum Computing.

1. IEEE Symposium on Computer Arithmetic (ARITH), June 25-27 2018, Amherst,

MA, USA: ARITH 2018 organized 8 technique sessions, i.e., (1) Multiplication and fused-multiply-add, (2) Accelerators for artificial intelligence and machine learning, (3) Accurate computation, (4) Floating-point, (5) Division, (6) Function evaluator and numerical solver, (7) Industry track – SIMD operations and (8) Modular operations and cryptography. It also organized 2 special sessions, i.e., (1) Arithmetic for artificial intelligence and machine learning and (2) IEEE standard 754-2018 and future plans, and 2 panels about (1) Arithmetic requirements for AI and deep learning and (2) Future directions in computer arithmetic. ARITH 2018 invited 1 keynote talks, i.e., “Accelerated computing on POWER platform” given by Balaram Sinharoy from IBM. The General Chairs of ARITH 2018 were Israel Koren from UMass in USA and Eric Schwarz from IBM in USA. The Program Chairs were Naofumi Takagi from Kyoto University in Japan and Alex Tenca from Synopsys in USA.

2. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 8-11, 2018, Hong Kong SAR, China: ISVLSI 2018 organized 6 technique sessions, i.e., (1) Analog and mixed signal, (2) Digital circuits and FPGA based design, (3) Testing, reliability, and fault-tolerance, (4) Computer aided design and verification, (5) Emerging and post-CMOS technologies and (6) System design and security. It also organized a poster session, a student research forum and 12 special sessions, i.e, (1) Shall we jointly address VLSI reliability and security? (2) Emerging computing and memory technologies at Post-CMOS era, (3) Essential keys to manufacturability: layout features and lithography technologies, (4) Emerging trends in energy efficient and secure neural network acceleration, (5) Intelligent methods & techniques for reliable and adaptive multicore/manycore system, (6) Microfluidic Large Scale Integration (mVLSI): recent developments and upcoming challenges, (7) Secure hardware design for distributed agents, (8) Embedded multi-core in automotive and I4.0, (9) Energy efficient and hardware secured architectures for smart electronics, (10) Timing in the nanometer era, (11) Attacking dynamic optimizations in the era of complex heterogeneous multi-core computing and (12) Design using emerging devices. ISVLSI 2018 host 6 keynote talks, i.e., (1) “Future hybrid circuits for functionality, performance and energy efficiency” given by K.-T. Tim Cheng from Hong Kong University of Science and Technology, (2) “Low power high performance multicore hardware and software co-design” given by Hironori Kasahara from Waseda University in Japan, (3) “Machine learning further improve physical design PPA at advanced node”

given by Weibin Ding from Cadence, (4) “Power density and circuit aging – system-level means for mitigation” given by Jörg Henkel from Karlsruhe Institute of Technology (KIT) in Germany, (5) “Self-awareness for heterogeneous MPSoCs: a case study using adaptive, reflective middleware” given by Nikil Dutt from University of California, Irvine, USA and (6) “Cognitive vision systems: energy efficiency influences from algorithms to architectures” given by Vijaykrishnan Narayanan from Pennsylvania State University, USA, and 5 plenary talks, i.e., (1) “Achieving 19 TFLOPS in 10W for deep learning using network pruning on Xilinx Zynq Ultrascale + FPGA” given by Yi Shan from DeePhi Tech, (2) “Overcoming challenges of accelerating deep neural network computations” given by Deming Chen from University of Illinois Urbana-Champaign, (3) “The advanced technologies in the new generation of Phytium's processors – from the architecture to implementation” given by Zhuo Ma from Phytium, (4) “Security of the Internet of Things: can hardware change the game?” given by Swarup Bhunia from University of Florida, Gainesville, Florida and (5) “Designing safety-critical systems: rapidly and accurately!” given by Ulf Schlichtmann from Technical University of Munich. The General Chairs of ISVLSI 2018 were Wei Zhang from Hong Kong University of Science and Technology, Jason Xue from City University of Hong Kong and Zili Shao Hong Kong Polytechnic University. The Program Chairs were Hai Li from Duke University, USA, Yu Wang from Tsinghua University, China and Wujie Wen from Florida International University, USA.

3. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 10-12 2018, Milan, Italy: ASAP 2018 organized 10 technique sessions, i.e., (1) Applications: image processing, (2) Design methods and domain specific languages, (3) Short paper session, (4) Invited papers session, (5) Applications: image processing and machine learning, (6) Applications: bioinformatics, (7) Architectures, (8) Applications: security, networking and floating point arithmetic, (9) Design methodologies and (10) Lab session. It also organized a special session for “cloud computing” and a workshop on “FPGA-based accelerated cloud computing”. ASAP 2018 invited 5 keynote talks, i.e., (1) “How to make sparse fast” given by Saman P. Amarasinghe from MIT, (2) “Deep reinforcement learning and algorithmic risks in finance” given by Marcello Paris from UniCredit, (3) “How open source designs will drive the next generation of HPC Systems” given by David Donofrio from Lawrence Berkeley National Lab, (4) “Google pixel visual core: a portable domain-specific processor for computational photography and machine learning” given by Andrea Di Blas from Google and (5) “Design trade-offs for machine learning solutions on reconfigurable devices” given by Michaela Blott from Xilinx. The paper submission deadline of ASAP 2018 was extended from April 22, 2018 to May 7, 2018. The General Chairs of ASAP 2018 were Marco D. Santambrogio from Politecnico di Milano in Italy and Jose L. Ayala from Complutense University of Madrid in Spain. The Program Chairs were Zhiru Zhang from Cornell University in USA and Diana Goehringer from TU Dresden in Germany.

Corps™

Corps™

AcademicKeys

http://www.academickeys.com/

HigherEdJobs

https://www.higheredjobs.com/

IEEE Job Site

http://jobs.ieee.org/

IEEE Computer Society | Jobs

https://www.computer.org/web/jobs

Computing Job Announcements – CRA

https://cra.org/ads/

Polytechnic Positions www.polytechnicpositions.com/

www.theiet.org/books

Everything you need to know about writing a book with the IETVisit www.theiet.org/authors to get all the information and advice you’ll need as an author, editor or contributor to an IET research-level book, from the start of the process – submitting a proposal – through to publication and beyond.

The Institution of Engineering and Technology (IET) is working to engineer a better world. We inspire, inform and influence the global engineering community, supporting technology innovation to meet the needs of society. The Institution of Engineering and Technology is registered as a Charity in England and Wales (No. 211014) and Scotland (No. SC038698).

For more details or to purchase your copy, visit: To place your order in the UK/ Rest of World, please contact IET:

T: +44 (0)1438 767328 E: [email protected]

Institution of Engineering and Technology PO BOX 96, Stevenage SG1 2SD, UK

To place your order in the USA & Canada please contact Charles Nestor, Sales & Marketing Associate: E: [email protected]

www.theiet.org/books

ICCE 2019 Executive Committee ICCE 2019 Conference Chair Anirban Sengupta Indian Institute of Technology Indore, India ICCE 2019 Technical Program Chair Dhireesha Kudithipudi Rochester Institute of Technology, USA Past Chair Saraju P. Mohanty University of North Texas, USA Web Chair Daniel Díaz Sánchez (Spain) Industrial Liaison Thomas Coughlin (USA) Dennis Shapiro (USA) President, Consumer Electronics Soc. Sharon Peng VP of CE Conferences Stephen Dukes (USA) Treasurer/CEA Liaison Brian Markwalter (USA) Treasurer/Local Arrangement Chair/Special Session Chair Stuart Lipoff (USA) Marketing and Social Media Chair Lee Stogner (USA) Young Professionals Chair Shingo Yamaguchi International Advisors Francisco Bellido (Spain) Peter Corcoran (Ireland) Uwe E. Kraus (Germany) Tom G B Wilson (Canada) Reinhard Moeller (Germany) Aldo W. Morales (USA) Stefan Mozar (Australia) Simon Sherratt (United Kingdom) Conference Coordinator

Charlotte Kobert, Pittsburgh, PA, [email protected]

ISVLSI 2018

Students Travel Support Awards Alireza Mahzoon, University of Bremen Leslie Hwang, University of Illinois at Urbana-Champaign Xiaobang Liu, University of Cincinnati Zhiming Zhang, University of New Hampshire

What is TC-VLSI?

TCVLSI is a constituency of the IEEE-CS that oversees various technical

activities related to VLSI.

Join TCVLSI

It’s

Technical Scope

TCVLSI Offers

It’s

1 2 3

Technical Committee on VLSI (TCVLSI), IEEE-CS http://www.ieee-tcvlsi.org

Key People

–

–

– –

–

– –

–

–

TCVLSI Sister Conferences

IET Computers & Digital Techniques

Call for Papers SPECIAL ISSUE ON: Hardware-Assisted Techniques for Security and Protection of Consumer Electronics

The EDA/hardware/VLSI community comprises people from diverse backgrounds (especially hardware and IP cores) leveraged for Consumer Electronics (CE). The electronics design industry is heading for a paradigm shift towards secured, reliable and low cost CE hardware as compared to conventional approaches. With this special section, we aim to present novel solutions for any security/protection problems related to hardware used in CE. Consumer electronics comprising of high end devices ranging from digital cameras, multi-spectral cameras, smart tablets, and night vision cameras to smart meters, along with information and communication technology could make the emerging concepts of smart cities and Internet of Things (IoT) a reality. In the world of CE, security, privacy, and protection of hardware and its information are equally important. “Hardware-Assisted Security” is defined as the security/protection of hardware/intellectual property (IP) cores of CE devices or information by a hardware/system of CE devices. The term “security” encapsulates a broad theme that covers many aspects including hardware security, protection, privacy, trustworthiness, and IP protection and information security. System security may refer to the security of the system (e.g. a specific CE device) that handles the data or information. Manuscripts should be scoped within the domain of Hardware-Assisted Security for CE devices and should be original manuscripts prepared in accordance to the normal requirements of IET Computers & Digital Techniques.

Topics covered include: Hardware security against Trojans for CE devices Forensic engineering based protection of CE hardware IP core/hardware security against NBTI attacks on DSP Hardware security/IP core protection against reverse engineering attacks for CE devices Protection mechanisms of IC/IP buyer Protection mechanisms of IC/IP seller Energy-efficient digital-rights management hardware for CE IP core protection of CE hardware Active and passive IP security of CE hardware PUF based security and protection methods of CE hardware Side channel attack resistant embedded systems, DRM systems

Submit your paper to the manuscript submission and peer review site via the following link: www.ietdl.org/IET-CDT

Publication Schedule: Submission Deadline: 28th February 2018 Publication Date: November 2018

Editor-in-Chief: Andrew Tyrrell, University of York, UK

Guest Editors:

Anirban Sengupta, Indian Institute of Technology, India E: [email protected] Saraju P. Mohanty University of North Texas, USA E: [email protected]

Garrett S. Rose University of Tennessee, USA E: [email protected]

:

? =

7Acceptance Notification: April 21, 2019Submission of Final Version: May 12, 2019

Z

July 15-17,

Editor-in-Chiefs (EiCs): Saraju P. Mohanty, University of North Texas, USA, [email protected]

Anirban Sengupta, Indian Institute of Technology Indore, India, [email protected]

Deputy Editor-in-Chief (EiC): Yiyu Shi, University of Notre Dame, USA

Associate Editors: Features: Hideharu Amano, Keio University, Japan Features: Shiyan Hu, Michigan Technological University, USA Features: Saket Srivastava, University of Lincoln, United Kingdom Features: Qi Zhu, University of California, Riverside, USA Opinions: Michael Hübner, Ruhr-University of Bochum, Germany Opinions: Yasuhiro Takahashi, Gifu University, Japan Opinions: Sergio Saponara, University of Pisa, Italy Updates: Hai (Helen) Li, Duke University, USA, Updates: Jun Tao, Fudan University, China, Updates: Himanshu Thapliyal, University of Kentucky, USA Outreach and Community: James Stine, Oklahoma State University, USA Outreach and Community: Mike Borowczak, University of Wyoming, USA

More information at: https://www.computer.org/web/tcvlsi/circuit

s-and-systems-letter Submission details:

Please visit the website and use standard VCAL template to prepare the manuscript

The IEEE VLSI Circuits and Systems Letter (VCAL) is a quarterly publication which aims to provide timely updates on technologies, educations and opportunities related to VLSI circuits and systems. The letter is published four times a year and it contains the following sections:

Features: selective research papers within the technical scope of TCVLSI. Goal is to report novel interesting topics related to TCVLSI, as well as short review/survey papers on emerging topics in the areas of VLSI circuits and systems.

Opinions: Discussions and book reviews on recent VLSI/nanoelectronic/emerging circuits and systems for nano computing, and “Expert Talks” to include the interviews of eminent experts for their concerns and predictions on cutting-edge technologies.

Updates: Upcoming conferences/workshops of interest to TCVLSI members, call for papers of conferences and journals for TCVLSI members, funding opportunities and job openings in academia or industry relevant to TCVLSI members, and TCVLSI member news.

Outreach and Community: The “Outreach K20” section highlights integrating VLSI computing concepts with activities for K-4, 4-8, 9-12 and/or undergraduate students.

Have questions on submissions; contact EiC: Dr. Anirban Sengupta ([email protected])

Join TCVLSI for FREE to be a part of a global community, visit:

http://www.ieee-tcvlsi.org

•related to “consumer electronics”.

• –

•

•

•••••••••••••••••••••••••••••••••••

••••••••••••••

Submission should follow IEEE standard template and should consist of the following: I. A manuscript of maximum 6-page length: A pdf of the

complete manuscript layout with figures, tables placed within the text, and

II. Source files: Text should be provided separately from photos and graphics and may be in Word or LaTeX format.

• High resolution original photos and graphics are required for the final submission.

• The graphics may be provided in a PowerPoint slide deck, with one figure/graphic per slide.

• An IEEE copyright form will be required. The manuscripts need to be submitted online at the URL:

More Information at:http://cesoc.ieee.org/publications/ce-magazine.html

Have questions on submissions or ideas for special issues, contact EiC at: [email protected]

The CEM won an Apex Grand Award for excellence in writing in 2013. The CEM is the winner in theRegional 2016 STC Technical Communication Awards - Award of Excellence! The CEM is indexed inClarivate Analytics (formerly IP Science of Thomson Reuters). The impact factor of CE magazine is 1.153.

IEEE Canadian Journal of Electrical and Computer Engineering Sponsored by IEEE Canada

http://journal.ieee.ca/index.html

CJECE Editorial Team CJECE Advisory Board Dr. Maike Luiken Dr. Wahab Almuhtadi Editor-in-Chief Dr. Shahram Yousefi Associate Editors Dr. Amir Aghdam Dr. Aldo Petosa Dr. Houshang Karimi Dr. Anirban Sengupta Dr. Jalal Habibi Dr. Sreeraman Rajan Dr. Umar Iqbal Dr. Peng Hu Dr. Ning Wang Dr. Bhavesh Bhalja Dr. Fabio Immovilli Dr. Bruno Neri Dr. Maher Bakri-Kassem Dr. Pedram Mousavi Dr. April Khademi Dr. Tiago H. Falk Dr. Hossein Rouhani Dr. Alexander Wong Dr. Sidney Givigi Dr. Om Malik Dr. Hani Mehrpouyan Dr. Davood Yazdani Dr. Ali Miri Dr. Ali Nasir Dr. Farzad Khalvati Dr. Hilmi Turanli Dr. Reza Zamani Dr. Alireza Safaee Dr. Vahid Garousi Dr. Waleed Ejaz Dr. Noureddine Chabini Dr. Yungang Zhu Dr. Sergio Saponara Dr. Rodrigo C. Guido

Call for Papers The Canadian Journal of Electrical and Computer Engineering (CJECE) is the flagship IEEE technical journal of the area in Canada. The CJECE (ISSN-0840-8688), issued quarterly, has been publishing high-quality refereed scientific papers in all areas of electrical and computer engineering since 1976 and is indexed in ISI and IEEE Xplore. Paper Categories The CJECE accepts the following categories of papers for publication; Papers presenting new and original results, techniques or concepts in a research area. Survey/Tutorial-style papers providing a rigorous analysis of existing results in a research area. Topics of interest include, but are not limited to: Artificial Intelligence Bioengineering/Biomedical Engineering Computer Systems Communication Systems Wireless Communication Multihop Wireless Networks Circuits Computer Networks Control Systems Electromagnetics Energy & Power Systems Microelectronics Robotics Network Security trust, & privacy Software Engineering Signal Processing Image Processing Notes for Prospective Authors Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated by CJECE. Manuscripts should be written in English or French and strictly adhere to the CJECE Author requirements. All manuscript submissions should go through Manuscript Central. Please visit: http://journal.ieee.ca/authors.html

IEEE Transactions on Nanotechnology (TNANO) Special Section/Issue on the

18th IEEE International Conference on Nanotechnology (IEEE-NANO 2018)

Nanoscience and nanotechnology have rapidly established themselves as enabling disciplines within many disciplines including materials science, engineering, physics, chemistry, and biology. Following the success of the 18th IEEE International Conference on Nanotechnology (IEEE-NANO2018), IEEE Transactions on Nanotechnology (TNANO) is extending a Call For Papers for a Special Section /Issue reflecting the scope of the conference. Submitted manuscripts will undergo a full peer review process. Submissions are welcome but limited to NANO presentations. Authors who are attendees are requested to significantly expand the previous conference version to contain substantial new technical material, as per TNANO and IEEE restrictions on duplicated publications and the competitive acceptance process. Manuscripts for the TNANO Special Issue/Section must be submitted on-line using the IEEE TNANO manuscript template and “Information for Authors”, via the IEEE Manuscript Central found at https://mc.manuscriptcentral.com/tnano. On submission to TNANO, authors should select the “Special Issue” manuscript type instead of “Regular Paper.”

Submissions that reflect the Conference Scope and current state of the field are welcome in areas including:

Micro-to- nano-scale bridging Nanobiology and Nanomedicine Nanoelectronics Nanomanufacturing and Nanofabrication Nano Robotics and Automation Nanomaterials Nano-optics, Nano-optoelectronics, and Nanophotonics Nanopackaging Nanoscale Metrology and Characterization Nanofluidics Nanomagnetics Nano/Molecular Heat Transfer & Energy Conversion Nano/Molecular Sensors, Actuators, and Systems Nanotechnology Safety, Education and Commercialization

Important Dates

Submission of papers: 1 December, 2018 Notification of first review results: 1 March, 2019 Submission of revised papers: 15 April, 2019 Notification of final review results: 15 May, 2019.

Society Website: https://cesoc.ieee.org/

Benefits Include:1) A nice color magazine

shipped to your door stepto update you on latest CE

2) Discount in conferenceregistration

3) Networking opportunitywith global peers

Online at: https://cesoc.ieee.org/membership.html

IEEE VCAL – TCVLSI Newsletter: Call for Contributions

The VLSI Circuits and Systems Letter aims to provide timely updates on technologies, educations and opportunities related to VLSI circuits and systems for TCVLSI members. The letter will be published quarterly a year (containing peer-reviewed papers) and it contains the following sections: Features: Selective short papers within the technical scope of TCVLSI. This section introduces interesting topics

related to TCVLSI, and short review/survey papers on emerging topics in the areas of VLSI circuits and systems. Opinions: Discussions and book reviews on recent VLSI/nanoelectronic/emerging circuits and systems for nano

computing, and “Expert Talks” to include the interviews of eminent experts for their concerns and predictions on cutting-edge technologies.

Updates: Upcoming conferences/workshops of interest to TCVLSI members, call for papers of conferences and journals for TCVLSI members, funding opportunities and job openings in academia or industry relevant to TCVLSI members, and TCVLSI member news.

Outreach and Community: The “Outreach K20” section highlights integrating VLSI computing concepts with activities for K-4, 4-8, 9-12 and/or undergraduate students.

We are soliciting contributions to all these four sections. Please directly contact the editors and/or associate editors.

Submission Deadline: All contributions must be submitted by Jan 1, 2019 in order to be included in the April issue of the letter.

Editor-in-Chief: Saraju Mohanty, University of North Texas, USA, [email protected] Anirban Sengupta, Indian Institute of Technology Indore, [email protected]

Deputy Editor-in-Chief: Yiyu Shi, University of Notre Dame, USA, [email protected]

Associate Editors: Features: Hideharu Amano, Keio University, Japan, [email protected] Features: Shiyan Hu, Michigan Technological University, USA, [email protected] Features: Saket Srivastava, University of Lincoln, United Kingdom, [email protected] Features: Qi Zhu, University of California, Riverside, USA, [email protected] Features: Theocharis Theocharides, University of Cyprus, [email protected] Opinions: Michael Hübner, Ruhr-University of Bochum, Germany, [email protected] Opinions: Yasuhiro Takahashi, Gifu University, Japan, [email protected] Opinions: Sergio Saponara, University of Pisa, [email protected] Updates: Helen Li, University of Pittsburg, USA, [email protected] (featured member story) Updates: Jun Tao, Fudan University, China, [email protected] (upcoming conferences, symposia, and

workshops, and funding opportunities) Updates: Himanshu Thapliyal, University of Kentucky, USA, (call for papers and proposals,

job openings and Ph.D. fellowships) Outreach and Community: Mike Borowczak, University of Wyoming, USA,

Emeritus Editor-in-Chief: Xin Li, Duke University, USA, [email protected]

Feature Member Dr. Swarup Bhunia Preeminence Professor, Steven Yatauro Faculty Fellow Director, NanoScape LabElectrical and Computer Engineering Department University of Florida Swarup Bhunia is a preeminence professor of cybersecurity and Steven Yatauro endowed faculty fellow of Computer Engineering at University of Florida, FL, USA. Earlier he was appointed as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over twenty years of research and development experience with 250+ publications in peer-reviewed journals and premier conferences and ten authored/edited books, including the first-ever text book in hardware security. His research interests include hardware security and trust, adaptive nanocomputing and novel test methodologies. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation career development award (2011), Semiconductor Research Corporation Inventor Recognition Award (2009), and SRC technical excellence award (2005) as a team member, and several best paper awards/nominations. He is co-founding editor-in-chief of a Springer journal on hardware and systems security. He has served as an associate editor of IEEE Transactions on CAD, IEEE Transactions on Multi-Scale Computing Systems, IEEE Transactions on CAD, ACM Journal of Emerging Technologies, Journal of Electronic Testing, and Journal of Low Power Electronics. He has served as program/general chair of several IEEE/ACM conferences. Dr. Bhunia received his PhD from Purdue University on energy-efficient and robust electronics. He is a senior member of IEEE.

Q1. Tell us a little about your research area and what motivated you to get into it?

My current research consists of two major thrusts: (1) hardware and systems security; and (2) food and medicine safety. These two topics cross-cut multiple disciplines, including electronics, algorithms, machine learning, and material science – many of the fundamental issues in both topics are common, including their origins (e.g., distributed nature of supply chain and lack of effective validation techniques), and the topics overlap among themselves in terms of solution paradigms. The first topic focuses on security of computer hardware and systems – it encompasses security of hardware intellectual properties, microchips and printed circuit boards (PCBs). With the emergence of Internet of Things regime and diverse attacks on the hardware itself, security issues at the hardware level have been more important than ever before. Over the past decade, as one of the early researchers in this field, I have contributed to this field through analyzing security vulnerabilities and developing effective solutions. The motivation to work in this field came from my understanding of the major demand for innovative solutions and suitability of my expertise in both algorithms and hardware. I also observed the critical need for low-cost reliable solution to analyze food/medicine safety. Both unintended as well as deliberate contamination of these consumable items are increasing rapidly leading to major impact on public health. Some critical safety issues on food and medicine arise from similar vulnerabilities as electronic hardware and can benefit from similar solutions. My research focuses on developing innovative solutions to empower people to verify the integrity of everything they consume.

Q2. What are some of your proudest accomplishments?

In 2007, two years after my graduation, when I was a young faculty, I saw a solicitation for research proposals on trusted electronics. After reading the solicitation, I came up with a promising idea and communicated that to the program manager. The proposal got funded and that launched me into the field of hardware security. I feel proud of that effort since it was a rather bold undertaking. Since then I have been steadily contributing to various aspects of hardware security and received many recognitions. I’m proud of the moments when some of my technologies got licensed by industry. Finally, I’m proud of my research on wearable and implantable imaging systems – arguably the first effort on wearable and implantable ultrasound, a best paper award on wearable imaging device (a functional prototype of which we demonstrated) for early detection of cancer, and an attractive technology I’ve been developing on detecting fake medicines and contaminated food.

Q3. How do you see your research field shaping up and what are the major directions?

The field of hardware security will have continued demand for robust and low-cost anti-piracy, anti-reverse-engineering and anti-Trojan solutions as well as novel system-on-chip architecture that can support security of the software stack that uses it as the trust anchor. These problems are expected to grow in significance over next decade and there will be tremendous opportunities to contribute in these areas. In particular, trust verification of hardware IPs, integrated circuits, and PCBs has emerged as a new sub-field in test/verification and effective methodologies, tools, and metrics in this area will be highly important. Protection of hardware IPs against reverse engineering and piracy through novel obfuscation and authentication methods would remain as major thrust. Finally, I believe safety issues in food/medicine would become epidemic and there would be a great demand to develop novel technology solutions to address them.

Q4. What advice would you give to junior researchers and graduate students?

Going through the early stages of my professional career as a faculty has been a wonderful learning experience for me. Prior to that I have been a graduate student myself – faced many challenges – and addressed them to the best of my ability. My advice to junior researchers and graduate students would be the following: (1) do not be afraid to explore and present revolutionary – non-incremental, potentially ‘crazy’ ideas – those are the ones that would give you a strong identity and likely have transformative impacts; and (2) don’t dampen your creative spirit due to rejections of papers/proposals, which are part of the peer-review process – just learn from the constructive criticisms and move on.

Q5. What profession would you be in if you weren't in this field?

I’ve a passion for acting. As a graduate student I was the President of a student organization at Purdue University, called PUTS. As part of the organization I participated in many student-led activities, including over 12 plays of different types. I’d probably be a stage actor or a theatre director (if you allow me to dream) if I were not in this profession.

Q6. Any final thoughts?

World is moving into a regime where security and safety issues will be omnipresent, probably become ever more significant due to the global economic trend, climate change, and many other issues beyond our control. As a researcher, we have a duty as well as power to serve our society. The world needs major innovations in security, safety and sustainability. Through my research, I try to do my part to make a positive impact on the society by addressing some of these critical problems. I’d ask everyone to keep this thought in mind and do things that make lasting positive impacts on our society and on our future generations.

Dr. Anirban Sengupta from Indian Institute of Technology (IIT) Indore elected Chairman of IEEE Computer Society Technical Committee on VLSI (TCVLSI) from Oct 2018 – 2020. Dr. Saraju Mohanty from University of North Texas, USA received IEEE-CS TCVLSI Distinguished Leadership Award in 2018.

Dr. Swarup Bhunia from University of Florida, USA received IEEE-CS TCVLSI Distinguished Research Award in 2018.

Dr. Anirban Sengupta from Indian Institute of Technology (IIT) Indore appointed Associate Editor of IEEE Canadian Journal on Electrical and Computer Engineering in 2018.

Dr. Anirban Sengupta from Indian Institute of Technology (IIT) Indore to lead as General Chair of 37th IEEE Int'l Conference on Consumer Electronics (ICCE), Las Vegas to be held on Jan 11 – 13, 2019.

Dr. Sudeep Pasricha from Colorado State University, USA received IEEE-CS TCVLSI Mid-Career Research Achievement Award in 2018

Dr. Anirban Sengupta from Indian Institute of Technology (IIT) Indore to join the Editorial Board of IEEE Transactions on Consumer Electronics (TCE) as Associate Editor from Jan 2019.

Special issue on “Hardware - Assisted Design for Security and Protection of Consumer Electronics” to be released in IET Computers & Digital Techniques in Nov 2018, by team of Guest Editors – Dr. Anirban Sengupta (Indian Institute of Technology (IIT) Indore), Dr. Saraju Mohanty (University of North Texas, USA) and Dr. Garrett Rose (University of Tennessee, Knoxville, USA)

Documents

G[G Àp G[ u YWX u GYWX - IEEE Computer Society · total synaptic current + Ý L + Ý > F + Ý ?.That way, the difference between positive and negative total synaptic current through