Generating a timing information (1-PPS) from a software definedradio decoding of GPS signals

D. Rabus1, G. Goavec-Merou1, G. Cabodevila1, F. Meyer3, J.-M Friedt1

1FEMTO-ST Institute, Time and Frequency Department, Besancon, France2OSU THETA, Besancon, France

e-mail: jmfriedt@femto-st.fr

https://github.com/oscimp/gnss-sdr-1pps

https://github.com/topics/gnss-sdr

May 28, 2021

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Software Defined Radio (SDR) implementation of a GNSS receiverI SDR: minimize hardware to RF frontend (antenna, amplifier and frequency transposition)I Process all radiofrequency signal as software on complex values I+jQI Gain access to the raw IQ stream for incoming plane wave physical characteristicsI Implement anti-jamming/anti-spoofing processing 1 in the SDR frontend (null-steering)I Full control of the complete signal processing chainI Steer local oscillator to match incoming timing information

How to materialize timing information is 1-Pulse Per Second (1-PPS)?1W. Feng, J.-M Friedt, G. Goavec-Merou, F. Meyer, Software Defined Radio Implemented GPS Spoofing and Its

Computationally Efficient Detection and Suppression, IEEE Aerospace and Electronic Systems Magazine 36 (3), March2021 and https://github.com/oscimp/gnss-sdr 2 / 11

Problem statement: SDR reception

ADC

ADCI

Q

FPGA

GP-C

PU

position,velocity

timesolution

(PVT)

interference

gnss-sdrGNU Radio

90◦

90◦

I Two-channel Ettus Research B210/AD9361 coherent radiofrequency frontend

I Complex frequency transpositionI = s(t) · cos(ωLOt) ; Q = s(t) · sin(ωLOt)

I ADC samples at fs ≥ 1.023 MS/s bothchannels (B ≥ 2.046 MHz)

I FPGA pre-processing and continuousdatastream transfer to general purposecentral processing unit (GP-CPU) runningfree, opensource implementation of GlobalNavigation Satellite System (GNSS) decodergnss-sdr

I compatibility with embedded applications,e.g. Raspberry Pi4 single board computer2,1.5 GHz quad-core in performance mode

I output: Position, Velocity, Timing (PVT)solution

2G. Goavec-Merou, J.-M Friedt, Porting GNU Radio to Buildroot: application to an embedded digital networkanalyzer, FOSDEM 2021, and gnss-sdr at https://github.com/oscimp/oscimp_br2_external 3 / 11

Problem statement: sample timing

time interval counterHP53132A

U−Bloxreceiver

hydrogenmaser

(inaccuracy< 1e−12)

ADCFPGA

gnss−sdr

AD9361 Raspberry Pi4

GbE

USB3

ADC CK

I, Q

Ettus Research B210

or

CPU CK

top value

B210 external10 MHz input

PLLext 10 MHz steering

R&S SMA100A

1−

PP

S

1−PPS

1575.42 MHz 40 MHz

ref clock

genuine GPS constellation

( )

40 MHz is 4-times multiplication of reference 10 MHz input of B210

HM always clocks the HP53132A counter and might clock the B210

I All communication betweenFPGA and GP-CPU hardwareasynchronous

I Only ADC sampling time isknown assuming continuousdatastream at fs

I Control the clock timing theAD9361 frontend ADC, whichalso clocks the FPGA

I Counter in the FPGA from 0 tofs − 1

I Characterization: HP53132Atime- interval counter clocked byHydrogen Maser (HM) andreference 1-PPS from U-BloxNEO-M8P hardware receiver

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1-PPS output: open loop

-600

-400

-200

0

200

400

600

800

0 50000 100000 150000

UB

lox-g

nss 1

-PP

S (

s)

time (s)

I 50 hour long measurementI time difference between a U-Blox NEO-M8P and the 1-PPS counter implemented in the FPGAI GP-CPU running gnss-sdr and logging the time-differenceI B210 clocked by a free running Rohde & Schwarz SMA100A synthesizer set to nominal 10 MHz,I +11.1 ns/s=ppb drift removed, only the residue is displayed.

⇒ objective: steer reference clock to keep 1-PPS within ±100 ns boundary5 / 11

1-PPS output: closed loop

I Control SMA100A frequency with time-offset information from gnss-sdr PVT solution

I comparison between the “single solution” and the PPP solution

I sampling period is 1-chip or 20 ms, control loop every 500 ms

I select a sampling rate fs fractional integer of the 40 MHz clock (1.25 MHz=integer division by 32,2 MHz=integer division by 20, 1.125 MHz=fractional division by 320/9) to avoid drifting 1-PPS

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1-PPS output: closed loop issue1

-PPS o

ffse

t (u

s)

time (s)

500 ns=1/2 MS/s

I Source → Conditioner →Acquisition/Tracking/Telemetry→ Observables → PVT

I Useless resampler from fs to fs :misses one sample every 232

I Make sure to Pass Through toavoid 1/fs jumps every232/fs = 2147.5 s at 2 MS/s

I (sampling rate 1.125 MS/s⇒ 232/(1.125 · 106) = 3817 s shiftby 1/1.125 = 0.888 µs)

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1-PPS output: closed loop result

-600

-400

-200

0

200

400

600

0 20000 40000 60000 80000 100000 120000 140000

1-P

PS

off

set

(ns)

time (s)

free runninggnss-sdr v.s UBlox

10-1410-1310-1210-1110-1010-0910-0810

-07

100 101 102 103 104 105Alla

n d

evi

atio

n (

no

un

it)

integration time (s)

gnss-sdr v.s UBlox

UBlox v.s HM counter

gnss-sdr v.s HM counterUBlox v.s HM counter

gnss-sdr v.s HM counter

I Long term stability assessment

I Drift of the HM with respect to1-PPS GNSS visible at ≥ X · 104 s

I Convert time interval x phase-timefluctuation to3 fractional-frequencyfluctuation y = xSigmaTheta-4.1/1col2col file

SigmaTheta-4.1/X2Y file_2col

I Allan Time Deviation (MDEV4)from 10−8 at 1 s (10 ns @ 1 s)↘ 1/τSigmaTheta-4.1/MDev file_2col.ykt

I Control loop time constant visibleτ ∈ [10− 100] s

4E. Rubiola, Phase Noise and Frequency Stability in Oscillators, Cambridge Univ. Press (2009), p.84F. Vernotte & al., SigmaTheta at https://theta.obs-besancon.fr/spip.php?article103&lang=en

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1-PPS output: OCXO→TCXO

I Replace SMA100A OCXO clockedsynthesizer with TCXO clockedAD9959 Direct Digital Synthesizer(DDS)

I Short term performance degradedby drift

I 32-bit resolution → 18.6 mHzDDS frequency resolution whenclocked by a 20 MHz TCXOinternally multiplied by 4

I close to SMA100A 10 mHzfrequency resolution

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1-PPS output: control loop initialization

0 100 200 300 400 500-120

-100

-80

-60

-40

-20

0

20

time (s)

0.5

0

-0.5

-1100 200 300 400

time (s)

1 P

PS

v.s

HM

(us)

1 P

PS

v.s

HM

(us)

free

runnin

glock on GNSS: define setpoint

I Excessive frequency offset betweenTCXO frequency and nominalfrequency ...

I ... prevents initial fast convergenceand leads to excessive oscillations.

I Initial coarse estimate of thefrequency offset by observing thefrequency drift once the first PVTsolutions are found before closingthe control loop

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ConclusionI Bridge the virtual output of SDR & application to GNSS decoding with hardware 1-PPS outputI Only the ADC timestamp provides accurate timing propagated to the asynchronous processing

chainI → need to steer the clock controlling the ADC ...I ... which also happens to control the FPGA in

which the counter is implemented.I Demonstrated 1-PPS frequency control to 10−8@1 s &↘ 1/τ consistent with hardware receiver performance

I Sample loss will hardly affect frequency control

Perspective: 1-PPS phase (time-offset) control evenwhen ADC samples are lost

Fork of gnss-sdr with 1-PPS support (SMA100A) availableat https://github.com/oscimp/gnss-sdr-1pps

Acknowledgement: the free, opensource soft-ware/gateware development community:

I gnss-sdr at github.com/gnss-sdr/ bythe Centre Tecnologic TelecomunicacionsCatalunya (CTTC, Spain): C.Fernandez-Prades and J. Arribas areacknowledged for fruitful discussions

I GNU Radio at github.com/gnuradio/

I Ettus Research FPGAgithub.com/ettusresearch/fpga andUSRP Hardware Driver (UHD) Softwareat github.com/ettusresearch/uhd

I Buildroot at https://buildroot.org/

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