General Introductionyieldwerx.com/new/wp-content/uploads/2020/04/yield... · NPI (New Product Introduction) - Ramping new product to market faster. Being able to quickly detect and

General Introduction1

© 2020 yieldWerx - Strictly Confidential

NPI (New Product Introduction) - Ramping new product to market faster. Being able to quickly detect and diagnose design, manufacturing, process and test issues. Correct the issues for material that’s WIP and avoid re-spins and costly test time – get your product to market on time and on budget.

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Top Challenges & Issues That yieldWerx Helps Customers Resolve

Data Quality Index – Allow the engineers to perform engineering, characterization within hours/days – not weeks or months. Improve their operational and business processes and improve the quality of data for them to perform engineering analysis, identify and fix yield issues.

Legacy Systems & Solutions – Non supportable solutions running on non supported HW and not being able to keep pace with new analysis needs, data volumes etc. IT/Solution developers retiring – non appealing solutions for current generation of product engineers.

Complex SCM/Test Flows – Chip Manufacturing – especially in the area’s of assembly and test is getting more and more complex as companies rely upon multiple OSAT’s and other facilities with little to non standardization and integration between the different players.

Customer Quality – Mission and Application critical consumer as well as industrial products are placing a huge demand on Chip Designers and manufacturers to provide the highest quality products and eliminate all and any ‘at risk’ chips We help customers implement Part Average Test (PAT) to meet Automotive Specs (AEC-Q001/AEC-Q002)

Complex Product Portfolios– Customers want simple tools to manage and monitor their complex portfolios. Focusing their energy on actual problems, new products instead of mature devices and product families. One stop shop for engineers, QA, Planners, Finance & Management.


Customers/End Users & Data Partners

Product &Design Engineers

Quality & YieldEngineers

World WideOperations

Planning Management

Fabless Companies Chip DesignCompanies outsourcing production& testing

IDMsIntegrated Device Manufacturers: design, manufacture, & sell IC products

OSAT'sOutsourced SemiconductorAssembly & Test Providers

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yieldWerx Customers

Test EquipmentManufacturers• Teradyne, LTX-Credence,

Chroma, HP, Advantest….

EDA Tool Vendors• Synopsys, Mentor Graphics,

Cadence…

Foundries• TSMC, Global Foundries, UMC, SMIC , ASMC, Tower…..

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yieldWerx Partners

End Users of yieldWerx

Your End Customers

4© 2020 yieldWerx - Strictly Confidential

Some of Our Customers


What is yieldWerx

Reporting & Analysis

ModuleData

Archiving & Purging Module

External Data

Source Integration

Automated Data

Loading & Business

Rules

Raw Data Monitoring

& KPI’s

Yield Calculation

& Monitoring

Standard Data Views

For SAS, JMP,

SpotFire

Statistical Process Control

(SPC)ModulePart

Average Test

(PAT++)Module

Real Time Handler &

Prober ControlModule

Lot Control &

DispositionModule

Lot Genealogy

Module

Cross Work Center

Correlation Self

Reporting & Executive

Dashboards Die/Wafer Banking &

Grading Module

Defect Data

Module

Memory & Bitmap Analysis Module

RMAAnalysis Module

Advanced Modules

Enterprise Module

Add On’s

Key

Overall Equipment Efficiency

OEE*

Test Program Mgmt.*

yieldWerx comprises of functionally feature rich suite of modules. At the heart of the solution is the Enterprise Modules that applies to every customer. Other modules can be selected based on the customers environment and needs. All of the modules are seamlessly linked and integrated with each other with common User Experiences. Some of the modules are Web Enabled – allowing functionality to be platform independent as well as accessible from any smart device so that customers can analyze and make decisions on the spot.

Bundled Modules

Solution ComplexityLow High

SAP, ERP, MES

Integration

Fabless Design HouseIDMS’s & OSATS


SMART Wafer Merge

Module

Automated Assembly

Map Generation

Module

yieldWerx – Core Functionality

© 2020 yieldWerx - Strictly Confidential 7

Automated Data Loading - Fully automated/lights out data loading functionality, business rules are applied to determine what is good/bad/engineering vs. production data. Ability to integrated with MES or other external systems to perform key data validation checks

Raw Data Monitoring – Daily/Hourly Email/Email Digests, Dashboards & Real Time alerts on any raw data that failed to load to production databases. Ability to rapidly reload failed raw data files after corrections have been applied.

Reporting & Analysis – Over 50 standard data analysis reports for Bin, Parametric, Functional, Yield, Defect, Image data across any work center

Standard Data Access For External Tools – Provision for SAS, JMP, Spotfire, Excel, Tableau, like tools to access data from standard or customized data views.

Yield Calculation Flexibility –ability to determine what rules should be applied to calculate yield, especially for Final Test data as well as for Wafer Sort where GDPW values are used over tested die.

Data Archive/Purge Module – Feature rich/automated policy driven data archival and purge functionality. Allows you to set data retention business rules at granular level.

yieldWerx – Core Functionality – Contd.


Assembly Map Generation – Generation of Inkless and Ink maps for Wafer Assembly in a variety of different industry and custom formats. Automated generation as well as xferring the maps to the desired Assembly Site.

Executive Dashboards/Datawarehouse Reporting – Ability to generate Executive Dashboards/Reports accessible from any Smart Device. Allows users to create their own reports in seconds. 100’s of yieldWerx widgets already designed and available. Ability to build data marts with yieldWerx and external data sources.

Lot Genealogy – Automatically generate Lot Genealogy from Fab to Wafer Sort/Assembly Test right down to the Die Level. Allows analysis to be performed top’s down OR bottoms up.

Wafer/Reticle Map Definition Tool – Reticle Definition and Wafer Map definition tool that allows you to define simple reticles to multi die and sub die reticle maps. Used then in reporting and analysis as well as Assembly.

yieldWerx – Quality, Data Monitoring & Part Average Test Modules


Part Average Test (PAT) – Real Time & Passive Part Average Test (PAT), Good Die in Bad Neighborhood (GDBN), GDBN-Z, Multi Variant PAT (MVPAT), Non Gaussian Data Distribution Detection, PAT Policy Editor, What If Analysis, PAT Limits Analysis & More.

SPC/SBL/SYL – Statistical Process Control, Statistical Bin Limit, Statistical Yield Monitoring functionality with the ability to define simple-> Complex rules. Handle WIP as well as integration with MES. Real time alerting mechanism as well as Mail Digests.

Smart Wafer Map Merge Module – Ability to merge data from different data sources, temperatures via user definable rules and policies. Ability to perform what if analysis. Ability to handle cases where parameters OR die were not tested. Can also create complex rules based on Bin, Bin & Parametric and define new Parameters generate Post Test.

Real Time PAT Final Test – Real Time Dynamic Limit Calculation/Monitoring on the tester. Ability to calculate DPAT limits on sample size defined by the end user as well as recalculate limits after N number of units have been tested if required.

yieldWerx – Advanced Functionality


Inspection Image Management – Automatically collect Inspection data and images and associate them to wafers/die and then use the data for both correlation purposes as well as Merge/Assembly business rules.

Defect Data Management –Ability to manage Metrology/Defect data, perform defect classification, defect carry over analysis and correlate defect data with test data.

Wafer Bank/Scrapping/Down Grading Management – Ability to manually scrap/down grade die AND pick select die from wafers and track them to Assembly lots vs. picking a complete wafer. Typically used in low volume/Aerospace & Defense Companies/Applications.

SMART Probe - Real Time Handler/Prober Control – Ability to control automatically control the prober/handler and collect real time data and make real time decisions. Re-test/re-probe portions of the wafer, certain die OR sample based probing are just some of the functionality offered.

Memory/Optical Bit Map Analysis – Ability to automatically construct image maps for memory or optical arrays (for example) just using failing data and then running pattern recognition on it to determine failure types/perform yield management.

yieldWerx – Advanced Functionality - Roadmap


Custom Limits Manager (CML) – Ability to create custom sets of limits OR import them and then manage them in yieldWerx. Then allow users to use custom limits to perform analysis instead of having to enter in custom limits manually (Available Q12020)

OEE Management – Equipment utilization and efficiency monitoring. Being able to detect cross test cell anomalies, determine equipment maintenance schedules, WIP planning and much more. Monitoring of Equipment Uptime, Idle Time, In Error State. Integration with MES systems. Data used for correlation with Test Data & more.

Test Program Management (TPM) – Functionality to manage Test Program and associated files releases to both internal test facilities as well as OSAT’s. Ensuring that correct Test Program is being used in Production. Ability to manage Engineering programs separately from Production, capture and define Correlation/Golden Units/Die data etc. Audit & Reporting capabilities. Release workflows & more.

CML

What are the strengths of yieldWerx


Modular by nature – you can pick and choose what modules you need now vs. later. Upgrades to new modules is seamless

Functionality to support NPI/Engineering/Characterization to high volume ramp and production – All available within the same tool.

Passive & Active Controls – yieldWerx can process and analyze the data post test OR it can directly be in the line of control.

Industry best practices/knowledge is continuously feed into the tool and made available in new releases

Raw Data In -> Electronic Assembly Maps Out – Fully Lights Out & Automated Vastly reduces IT/PDE FTE overheads

What yieldWerx Gives You

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A Trusted Partner – We provide years of Semiconductor knowledge/lessons learned and experience of working with and at some of the worlds largest semiconductor companies. Let us review your operations and provide recommendations.

Reduced Operations Cost – Reduce operations costs with live and accurate data to be used for planning purposes, better SCM decisions and data, Executive Management dashboards that show revenue, forecasts, target yield vs. delta , test capacity planning and where to focus resources on.

New Markets/Customers – Provide solutions that provide a higher quality product that allows you to enter/penetrate new markets and customers where product quality is essential. Especially the Defense, Automotive, Life Sciences industries.

Accelerated NPI– Get your product to market faster, save on product re-spins and focus the engineers on solving problems faster and more efficiently without adding more bodies/systems and tools.

Automation & Seamless Solution– We provide a seamless solution with high levels of automation that requires minimal support/configuration or customization as compared to other solution providers or in house solutions

Improved Yields– Improved yields across your product portfolio. Reduce the number of RMA and other escapes. Have data on hand to drive process issues/test issues at foundry’s and OSAT’s down and implement standards.


BIN WAFER MAPS

Comprehensive Reporting & Analytics – The Basics

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yieldWerx offers a comprehensive suite of over 100 reports ranging from Bin, Yield, Parametric, Characterization, Correlation and many more allowing engineers to quickly get to the root cause of issues. All reports and analytics can be set to run automatically saving engineers even more time.

PARAMETRIC MAPS PARAMETRIC TREND

BIN HISTOGRAM YIELD BY LOT + MANY MORE PARAMETRIC DISTRIBUTION

BOX PLOTS

CORRELATION


Examples of yieldWerx Modules & Analysis – Advanced

LOT GENEALOGY ENGINEERING CHARACTERIZATION

“Data Analysis Across Multiple Work Centers Enabled via Lot Genealogy”

“Statistical Process Control (SPC) with Real Time Alerts & MES/Equipment Stop Lot”

STATISTICAL PROCESS CONTROL -SPC

IMAGES- MEMORY/PIXEL ANALYSIS

Corner Temp Voltage vs. Parameter

Pixel/Memory Maps – Image Maps© 2020 yieldWerx - Strictly Confidential 15

yieldWerx Part Average Test (PAT) – Improved Quality

Outlier Die – eliminated real time @ Final Test OR post wafer sort. Good Die where parametric values are not within the normal distribution are downgraded.

Good die that are neighboring bad die are eliminated from being assembled. Customers can choose how aggressive a policy they want to implement.(Yellow Die are those that were tested good but were downgraded because they were next to a bad die neighborhood)

POST PAT

yieldWerx provides a comprehensive PAT module with Static & Dynamic PAT, GDBN , GDBN-Z and SBL/SYL functionality for multi site testing.

PRE GDBN POST GDBN

© 2020 yieldWerx - Strictly Confidential16

Reference: Multivariate Outlier Modeling for Capturing Customer Returns – How Simple It Can BeJeff Tikkanen1, Nik Sumikawa2, Li-C. Wang1, Magdy S. Abadir2 1UC-Santa Barbara, 2Freescale Semiconductor

• The PAT limits define a univariate outlier is set at +/- 3δ. (”3δ bounding box”) where dies outside the box are outliers

• The covariance-based PAT limits using the equivalent 3δ Mahalanobis distance gives an oval shape

(assumed to be 0.8 correlated)• Dies inside the shaded areas are classified by the covariance based model as outliers, but these

dies would have been missed by the univariate outlier analysis.

yieldWerx Part Average Test (PAT) – Multi Variate Analysis



yieldWerx Part Average Test (PAT) – Multi Variate Analysis

Start

Explore Data Characteristics

Normal Distribution

• Standard Deviation (SD) Method

Takes into account for Skewness / Large Gap

• Robust mean and Sigma• Median Rule • Median Absolute Deviation (MAD))• Tukey’s Method • Adjusted Boxplot• Semi-interquartile ranges (SIQRs)

• Adjusted Boxplot• Semi-interquartile ranges (SIQRs)

Yes

Yes

No

No

yieldWerx Part Average Test (PAT) – Non Gaussian Analysis


yieldWerx – Smart Wafer Map Merge Module (SWM)


• There is a growing need to support the merging of different wafer sort OR wafer related data to generate a final merged map and data set.

• This has typically been done via scripts and human glue – no systematic solution.

• This can apply to devices that are tested at multiple temperatures OR where Bump OR AOI data is captured

• Clients also want to be able to compute and stored differences between parameters OR apply other rules when merging data

• yieldWerx has introduced the SWM Module to provide this functionality

• Ability to define business rules that are BIN, Parametric OR a combination of the two

• Can daisy chain as many rules as required into a single policy

• Resulting merged wafer maps saved as unique data sets in the yieldWerx database

• Assembly maps then generated from merged wafer maps

• Polices can be executed manually to perform what if analysis and then automated

• Custom BIN’s can be defined on the fly

• Rules allow for new parameters to be calculated as part of rule/policy execution

Purpose Functionality Benefits

• Point and click configurable rules and policies – virtually eliminates all need for manual scripting

• New complex rules can be easily added to the library

• Adds a another layer of quality management where a die is only qualified as ‘Good’ if key parameters values are within a given tolerance at multiple measurement points

• Allows Bump/Inspection OR any other ‘Die’ level data to be merged post test

• Full auditability and traceability from source data to merge results

• Yet another way yieldWerx is improving end product quality and reliability

yieldWerx –Smart Wafer Map Merge

Module (SWM) –As Simple As 1-2-3


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Define The Rules & Policies

Manually Execute & Validate

Automate & Monitor


yieldWerx Part Average Test (PAT) – Real Time FT DPAT

yieldWerx Final Test DPAT Module provides Real Time Dynamic Limits to the tester/test program BUT also deal with many Operational issues (e.g. Shift change, Test Program crashes, changing from single site to multiple sites and vice versa)

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yieldWerx Statistical Bin Limits (SBL)/Statistical Yield Limits (SYL)

yieldWerx’s SBL and SYL functionality is tightly integrated with the other PAT modules and has the ability to put equipment or lots/wafers on ‘HOLD’ for engineering disposition.


yieldWerx – Assembly Mag Generation (AMG) Module


• Unless you’re performing ‘Blind’ assembly – you need to be able to generate an assembly/pick map.

• For engineering lots OR as part of the NPI process you may want to apply different criteria OR even assemble that were not classified as GEC OR manually pick the die you want to assemble

• You want the ability to be able to generate assembly maps from any test data collection point

• Additionally you want to be able to generate assembly maps from merged wafers

Purpose Functionality Benefits

• Complete ‘Lights Out’ capability & functionality. Automatically send your assembly maps to anywhere globally.

• Complete traceability and auditability – every die/wafer assembled generates a unique point in time dataset in yieldWerx

• No need to script or customize to meet special needs or requirements

• Ability to bank die/wafers• Integrated with MES systems so

that assembly maps are only generated on ‘Lot End’ signals

• Handle all industry formats• Robustness in being able to manage

multiple assembly map outputs for the same wafer

• Create business policies that allow you to automatically generate assembly maps – policies can be Test Point, Test Program OR Device Level

• Dashboards & automated monitoring

• Ability to manually pick any die and generate and include it in an assembly map

• Allows for a wafer to be picked and different die assembled many times

• Allows the user to be able to downgrade die and then assemble them

• On the fly BIN definition capabilities

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yieldWerx Assembly Map Generation(AMG)yieldWerx provides a comprehensive Assembly Map Generation Module that seamlessly and automatically generates Assembly Maps as well as Ink Maps and is integrated with PAT, GDBN and GDBN-Z


yieldWerx – Real Time Tester Controller

Smart Probe Module: Wafer Map Layout & Real Time Data Collection/Control. The savings, reduction in testtimes, ability to monitor and detect anomalies and issues quickly, react to hardwarefailures and save valuable data and continue probing from where you left off and more –can very quickly mean many thousands of dollars/millions of dollars of savings for largetest floors.

• Ability to probe the back and front of wafer (e.g. LED devices) – in either order and then only probe the die that passed from the first pass

• Probe only predefined die and skip die, to avoid probe card damage e.g. in the case of bumped die where you don't want to touch down and probe die with bad bumps.

• Stop/pause a wafer being probed at any time – and then start off from where you left off • Unload the wafer from a tester/ prober and then continue probing it on a different tester/

prober • Automatically saves data after N number of die (configurable) – preventing data loss in case

of hardware failure • Allows the operator to select and probe any die on the wafer • Skip Die, Next Die, Previous Die Controls all available to the operator • Displays yield, die probed/remaining die, time elapsed/remaining – real time • Automatically stop probing a wafer if yield is < X% after probing N number of die • Automatically detect site ( multisite ) yield issues • Automatically stop probing if N number of failures detected contiguously

• Many other new controls being designed and will be part of the future releases, including • Automatic Yield Recovery – go back and re probe suspect die or possible recoverable die without unloading the

wafer • Real time Parametric SPC Control charts • Sample Probing – probe only certain portions of the wafer and automatically assign bin values to unprobed die • Sample Probing – based on cumulative/stacked wafer map results from last N sets of data from similar lots/wafers • PCM/WAT Data Driven Probing – Only probe die/regions of wafer where the PCM/WAT Data is good.



yieldWerx – Automotive Specific Functionality

PAT (POST DATA ANALYSIS)Ability to execute Post Data Collection PAT analysis for both Wafer Sort & Final Test Data

REAL TIME PAT CONTROLAbility to calculate dynamic PAT limits real time interact with the tester/test program and modify limits by lot/wafer/screen & site.

MULTI VARIATE PART ANALYSISAbility to group like tests and identify outlier die not falling into the same range of other test results for the same die.

PAT RULES BY TOUCHDOWN COUNTSAbility to remove known Good Die where the maximum number of touch downs has been exceeded (to meet AEC spec’s & take into account multi temp testing

.

AMG ENHANCMENTSThe ability to manually generate Pick Lists/Maps using either BIN OR Parametric Data and also support Multi Die/Sub Die/Reticle

SMART WAFER MERGE MODULEAbility to combine via Policies and Automation – Wafer Probe data from different test conditions using rules based on BIN data or Parametric Results..NON GUASSIAN DISTRIBUTION DETECTIONAbility to detect non Gaussian Distribution of PAT Parameters and adjust SPAT/DPAT limits accordingly

PAT – Part Average Test

yieldWerx Executive Dashboards – Web & Mobile App

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Mobile Accessible via Phone App

100+ Management/SCM/Planning Widgets

100+ Engineering , Design& Product Development, Quality Control Widgets

Choose from our many widgets OR create your own reports in literally seconds via Self Service Capability


About yieldWerx

• yieldWerx brings over 300+ years of individual experience to the table with team members having worked insome of the worlds largest and top semiconductor, tool/equipment and EDA vendor/companies.

• We design and deliver solutions that have been tried and tested and adapt to both low volume design housesto large scale wafer fabrication foundry’s/assembly and test floors.

• Our knowledge and experience does not just lie within Test & Yield Management – but across R&D, Design,Manufacturing & Process Development and the complete Semiconductor Supply Chain.

• Hence when we design and implement solutions, we do with the complete “end to end vision in mind”

yieldWerx – End2End Test Data Intelligence!

Faster Time toMarket

Higher DeviceQuality

Improved Operational

Efficiency



Q&A

Q&A

Questions.docx

Suite 213, 8105 Rasor Blvd. Plano, TX 75024

+1-888-929-4022

[email protected]


Documents

General Introductionyieldwerx.com/new/wp-content/uploads/2020/04/yield... · NPI (New Product Introduction) - Ramping new product to market faster. Being able to quickly detect and