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ECEn 224 © 2003-2008BYU

Gates – Part 1

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ECEn 224 © 2003-2008BYU

Gates are Built With Transistors

nFET

gate

drain

source

3 volts

drain

source

0 volts

drain

source

currentflows

nocurrentflows

nFET On nFET Off

N-type field-effect transistor = nFet

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ECEn 224 © 2003-2008BYU

Gates are Built With Transistors

pFET pFET On pFET Off

gate

source

drain

0 volts 3 voltscurrentflows

nocurrentflows

source

drain

source

drain

P-type field-effect transistor = pFet

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Complement

Also known as invert or not.

x x'0 11 0

x’x

This is a schematic symbol.It is a graphical representationof a circuit which implementsthe operation.

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FET-Based Inverter

Vin Vout

Vcc = 3V

GND = 0V

3V 0V 0V 3V

off

on

on

off

Vcc = 3V

GND = 0V

Vcc = 3V

GND = 0V

“Ground”

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AND and OR Gates

A B Q=A•B

0 0 00 1 01 0 01 1 1

A

BQ

A

BQ

A B Q=A+B

0 0 00 1 11 0 11 1 1

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ECEn 224 © 2003-2008BYU

Boolean Expressions and GatesEach Boolean expression has a corresponding realization with logic gates.

A

BC

F

F = A’ + B C

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NAND Gates

A

BQ

A B Q=(A•B)'

0 0 10 1 11 0 11 1 0

NAND

A

BQ

A

BQ

Q is true iff A AND B are true

Q is false iff A AND B are true

AND

NANDBubble means NOT

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FET-Based NAND Gate

A

B

BA

Vcc

GND

F

Vcc

GND

1

1

11 off

on

off

on

0

Vcc

GND

1

0

01 off

on

on

off

1

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NOR Gates

A B Q=(A+B)'

0 0 10 1 01 0 01 1 0

A

BQ

NOR

A

BQ

A

BQ

Q is true if A OR B is true

Q is false if A OR B is true

OR

NOR

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ECEn 224 © 2003-2008BYU

FET-Based NOR Gate

A

B

BA

F

Can you complete the truth table?

A B F

0V 0V ?0V 5V ?5V 0V ?5V 5V ?

Vcc = 5V

GND

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ECEn 224 © 2003-2008BYU

FET-Based NOR Gate

A

B

BA

F

Can you complete the truth table?

A B F

0V 0V 5V0V 5V 0V5V 0V 0V5V 5V 0V

Vcc = 5V

GND

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ECEn 224 © 2003-2008BYU

FET-Based Gates

• P-type FETs must be on top of gate• N-type FETs must be on bottom of gate• Due to electrical characteristics of the two

FET types

• Output is driven to either ‘1’ or ‘0’– never both– never neither

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Exclusive-OR (XOR)

Output is true iff inputs are different.

A

B

Q = A B = A’B + AB’

Another definition: Q is true iff A does not equal B

A B Q = A B

0 0 00 1 11 0 11 1 0

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Exclusive-OR Theorems

X 0 = X

X 1 = X'

X X = 0

X X' = 1

X Y = Y X Commutative law

( X Y) Z = X ( Y Z ) = X Y Z Associative law

( X Y)' = X Y' = X' Y

The first 4 are important,

the others are used less frequently

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ECEn 224 © 2003-2008BYU

Equivalence Operation

denotes equivalence (also written as X==Y)

Output is true iff inputs are equal

X

Y

Q = (X==Y)= X’Y’ + XY

X Y X==Y

0 0 10 1 01 0 01 1 1

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XOR and EQUIV are Complements !!

X Y XY X==Y

0 0 0 10 1 1 01 0 1 01 1 0 1

Gate often called exclusive NOR or XNOR

Alternate equivalencesymbol

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Multi-Input Gates

A

B

BA

Vcc

GND

F

C

C

GND

A

B

BA

Vcc

F

Which one will be slower/faster?

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Alternative Gate Symbols

The symbolic meaning of the circuit should be clear from what

you draw...

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Alternative Gate Symbols

Q is true iff A is false OR B is false

A

BQ

Q is true iff A is false AND B is false

A B Q

0 0 10 1 11 0 11 1 0

A B Q

0 0 10 1 01 0 01 1 0

A

BQ A

BQ

A

BQ

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Alternative Gate Symbols

• Turn on sprinklers if it is not a holiday and it is not a weekend

or?

The problem statement uses AND, so use the AND symbol

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Alternative Gate Symbols

• Turn off the sprinklers if it is a holiday or it is a weekend

or?

The problem statement uses OR, so use the OR symbol

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Another Example

• Design a circuit to determine whether the bits of a 4-bit wire are all zero

This is the appropriate symbol to use…

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Mixed Symbols

• Such a gate doesn’t likely exist• Build from AND gate and inverter• Simplifies schematics, enhances

readability

Q is true iff A is false AND B is true

A

BQ

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Single Gate Conversion Rules

• How to change one symbol to another:– Change symbol

• AND to OR• OR to AND

– Invert all inputs and outputs• No change in behavior – merely a symbol change

Q is true iff A is false AND B is true Q is false if A is true OR B is false

A

BQ

A

BQ

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Alternative Gate Symbols - Summary

• Use the symbol that matches the problem statement– Clarity– Documentation– Maintenance

• If function is correct but symbol is wrong then your schematic is wrong

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Positive vs. Negative Logic

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Positive Logic and Negative Logic

V1LogicGate

V1 V2 V3 Vout

0V 0V 0V 0V0V 0V 5V 0V0V 5V 0V 0V0V 5V 5V 0V5V 0V 0V 0V5V 0V 5V 0V5V 5V 0V 0V5V 5V 5V 5V

V2

V3Vout

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Positive LogicLet:

0 volts => 05 volts => 1

The circuit is a logical AND gate

v1 v2 v3 vout

0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

V1 V2 V3 Vout

0V 0V 0V 0V0V 0V 5V 0V0V 5V 0V 0V0V 5V 5V 0V5V 0V 0V 0V5V 0V 5V 0V5V 5V 0V 0V5V 5V 5V 5V

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ECEn 224 © 2003-2008BYU

Negative LogicLet:

0 volts => 15 volts => 0

The same circuit is a logical OR gate

v1 v2 v3 vout

1 1 1 11 1 0 11 0 1 11 0 0 10 1 1 10 1 0 10 0 1 10 0 0 0

V1 V2 V3 Vout

0V 0V 0V 0V0V 0V 5V 0V0V 5V 0V 0V0V 5V 5V 0V5V 0V 0V 0V5V 0V 5V 0V5V 5V 0V 0V5V 5V 5V 5V

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ECEn 224 © 2003-2008BYU

Positive/Negative Logic

• The most common mapping is positive logic:

+V 10V 0

• Different systems have used different mappings in the past

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Multi-Level Logic

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Levels of a Network

Maximum number of gates between an input and the output

5 Levels

3 LevelsIn general:

- the more levels, the slower the circuit

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ECEn 224 © 2003-2008BYU

Number of Levels

• Number of levels can be increased by factoring

• Number of levels can be decreased by multiplying out

• Changing the number of levels affects area and speed

G = AB + ACDE + ACF = A(B+CDE+CF)

G = A(B+CDE+CF) = AB + ACDE + ACF

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Example

G = AB + ACDE + ACFLevels = 2Gates = 4Delay = tAND4 + tOR3

Gate Inputs = 12Transistors = 24Largest gate = 4 inputs

Area Calculations: - Each input to a gate costs ~2 transistors - Area number of transistorsDelay Calculations: - Find slowest path from inputs to output

tdelay = tAND4 + tOR3

- The 4-input AND is likely slower than the other AND gates

A

B

ACDE

ACF

G

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ECEn 224 © 2003-2008BYU

Change the number of levels by factoring

G = ACDE + ACF + AB = A(CDE + CF + B)

CDE

C

F

BA

G

Levels = 3Gates = 4Delay = tAND3 + tOR3 + tAND2

Inputs = 10Transistors = 20Largest gate = 3 inputs

factor

This is a 3-level circuit…

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Factor Again

G = A(CDE + CF + B) = A[B+C(F+DE)]

A

BC

F

D

E

G

Levels = 5Gates = 5Delay = 3 x tAND2 + 2 x tOR2

Inputs = 10Transistors = 20Largest gate = 2 inputs

factor

This is a 5-level circuit…

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ECEn 224 © 2003-2008BYU

Changing the number of levels

Three alternative solutions for same function…

2-level 3-level 5-level

Logic Levels 2 3 5Delay tAND4 + tOR3 tAND3 + tOR3 + tAND2 3 x tAND2 + 2 x tOR2

Gate Count 4 4 5Gate Inputs 12 10 10Transistors 24 20 20

Largest Gate 4 3 2

Each has different area/speed characteristics

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ECEn 224 © 2003-2008BYU

Two-Level vs. Multi-Level

• In general:– Two-level is fastest– Multi-level can be smaller

• Exploring by hand to find just the right solution can be difficult

• We will focus on two-level– Easy to get from truth table– Minimization techniques in later chapters focus on

it