Future ASIC technologies in HEP Experiments

Michael Campbell and Federico Faccio

Microelectronics Section

ESE Group, EP Department, CERN

Acknowledgements

• All those who signed up to the WP mailing list

• Those who presented as first meeting on 5th March

• Members (and one retired member) of ESE Group who provided important inputs. In particular Philippe Farthouat, Erik Heijne, Kostas Kloukinas, Sandro Marchioro and Walter Snoeys

• External experts: Alvin Loke from Qualcomm, Michael P. King from Sandia

Resources:

• Michael P. King : FinFET technologies for Digital Systems with Radiation Requirements: TID, SEE, Basic Mechanisms and Lessons Learnt https://indico.cern.ch/event/666568/

• Alvin Loke: Analog/Mixed-Signal Design in finFET Technologies https://indico.cern.ch/event/662048/

• Erik Heijne: Report on IEEE-ISSCC 2018: micro-nano-pico, we must go on https://indico.cern.ch/event/709523/

2

Outline

• Context

• ASIC’s used during LHC Runs 1 and 2 and lessons learned

• Transistor scaling: opportunities and challenges

• Chip stacking

• Radiation tolerance

• First work package meeting and preliminary conclusions

• One (optimistic) long term scenario

• The way ahead for this work package

3

Context

• The EP Department asks us to prepare a document by the end of 2018 outlining plans for R and D in the period beyond 2020

• A major decision concerning the next large project (expected ~2020) will have a large impact on which direction to take

• Let’s look briefly at ASICs from the first generation LHC detectors

• Let’s see where we are now with respect to industry

• What can we learn from our past and from what’s happening outside

4

pixeldetector

beam pipe

Si strip tracker

e-CAL

TRT

h-CAL

muon chambers•

Some of the ASICs in ATLAS

FE-I3 pix det

28 000 chips

80 M segments

1.7 m2 Si sensor

ABCD Si det

50 000 chips

6 M segments

60 m2 Si sensor

ASDBLR TRT det38 000 chips

DTMROC TRT det

19 000 chips

ASD muon det148 000 chips

Total ATLAS100 million sensor cellsappr. 800 000 chipsmajority ASICs

Chips to scale 1 cm

Slide by E. HeijneISSCC 2014 5

pixeldetector

Total CMSappr. 1 million chipsof which 700 000 ASICs

MAD muon det181 000 chips25 000 m2 gas-filled

APV25 Si det

110 000 chips

9.3 M segments

198 m2 Si sensorPSI46 pix det

16 800 chips

66 M segments

1 m2 Si sensor

QIE8 calorimeter220 400 chips

beam pipe

Si strip tracker

e-CALh-CAL

muon chambers

Chips to scale 1 cm

Some of the ASICs in CMS

Slide by E. HeijneISSCC 2014

6

List of main functions performed by on-detector ASICs

• Front-end ASICSignal amplificationNoise filteringPipelining (analogue, binary or digital)Discrimination / A to D ConversionL1 selectionData transmission off chip

• Module controllerSlow control interfaceMonitoring of FE ASICsTemperature monitoring

• Data transmissionData de/serialisation on/off moduleOptical receiver and transmitters

• Voltage regulators7

Radiation levels foreseen in ATLAS

Sub-detectorNIEL

[1MeV n.cm-2.year-1]

TID

[Rad.year-1]

SEU tolerance

[>20 MeV hadron.cm-2.year-1]

Pixel B-layer 1.62 1014 1.1 107 2.30 1014

Pixel 7.58 1013 4.98 106 8.98 1013

SCT 1.59 1013 7.83 105 1.22 1013

TRT 7.23 1012 1.56 105 2.86 1012

Lar 1.85 1011 4.77 102 3.78 1010

Tile 2.74 1010 37.8 6.74 109

CSC 8.34 1011 23.0 102 1.59 1011

RPC 5.71 109 11.5 1.04 109

TGC 6.53 109 16.5 1.75 109

MDT 4.80 1010 74.1 8.25 109

Slide by Philippe Farthouat 8

Example of ATLAS tracking ASICs

Tracking detectors ASIC Technology Functionality Quantity & remarks

Pixel

FEI 0.25 µ CMOS Front-end ~28000

Module Controller 0.25 µ CMOS Control ~1800

VDC 0.25 µ CMOS VCSEL driver ~500

DORIC 0.25 µ CMOS Timing and control receiver ~400

Silicon Strips

ABCD DMILL Front-end ~50000BiCMOS design

DORIC 0.35µ BiCMOS Timing and control ~4100

VDC 0.35µ BiCMOS VCSEL driver ~8200

TRTASDBLR DMILL Amplifier-shaper-

discriminator~38000

Bipolar design

DTMROC 0.25 µ CMOS Digitiser ~19000

Slide by Philippe Farthouat 9

Example of ATLAS MUON spectrometer ASICsASIC Technology Functionality Quantity & remarks

MDTASD 0.5 µ CMOS Amplifier-shaper ~5000

AMT 0.3 µ CMOS Time to digital conv. ~15000

CSC

CSC

ASM1 0.5 µ CMOS Preamplifier ~1300

ASM2 0.5 µ CMOS Multiplexor ~1300

Clock driver 0.5 µ CMOS Clock driver ~200

HAMAC-SCA DMILL Analogue memory ~2600Common with LAr

RPC

RPCASD GaAs Amplifier-shaper ~47000

CMA 0.18 µ CMOS Coincidence matrix ~3300

TGC

TGC

ASD Bipolar Amplifier-shaper ~81000

HpT 0.35 µ CMOS Trigger ~800

PP 0.35 µ CMOS Trigger ~15000

SLB 0.35 µ CMOS Trigger ~3000

JRC 0.35 µ CMOS JTAG controller ~1400

Slide by Philippe Farthouat 10

Additional functions in on-going upgrades

• Enhanced radiation hardness in trackers

• New architectures – with highly complex digital circuitry - needed to deal with higher pile up

• Fast timing layers also for pile up mitigation

• Serial powering or DCDC convertors

11

10um

3um 1.5um

1um

0.8um

0.35um

0.25um

180nm 65nm130nm

Moore’s uncertain future

Alice SPD chip 1999

RD-53 chip2017

12

Si CMOS technology nodes in papers ISSCC

2018

65 nm

14 nm

~300 papers acceptance <40%

'SiGe'

Slide by E. HeijneFrom ISSCC 2018

28 nm

13

Looking ahead – scaling

• As a community we have accumulated (at least) 10 years delay since 1999

• With the 65nm process we cannot increase IO speed beyond 10Gbps

• FPGA chips (which we rely on off-detector) are pulling away from us

• We cannot stand still but going forward requires significant resources

• Below 28nm FinFETs become the workhorse

14

Journey to FinFETs• 16/14nm complexity accumulated from scaling innovations

introduced earlier across multiple earlier nodes

TechnologyInnovation

FoundryDebut

ReasonRequired

Mechanical stressors 40nmMobility boost for more FETdrive & higher Ion/Ioff

HKMG replacement gateintegration

28nm (HK-first)20nm (HK-last)

Higher Cox for more FET drive & channel control

Multiple-patterning 20nmSub-80nm pitch lithography without EUV (13.5nm mostly l= 193 nm)

Complexmiddle-end-of-line

20nmContact FET diffusion & gate with tighter CPP

Slide courtesy of Alvin Loke, Qualcomm 15

Planar NMOS vs FinFET

Planar

p-substrate

channel

p-well

gaten+ drain

n+ source

STI

p-well tie

FinFETfully-depleted

body

p-substrate

n+ drain

p-well

STI

NMOSn+ source

p-well tie

Slide courtesy of Alvin Loke, Qualcomm16

A closer look

• Most commercial fabs have migrated to FinFETs below 20-nm gate length feature sizes

• FinFETs exhibit improved electrostatic control of the channel and improved reliability compared to equivalent scaled planar CMOS

T. Hook, FDSOI Conference, Taiwan, 2013

Courtesy of Michael P. King, Sandia17

Mechanical Stressors• Mobility depends on channel lattice strain (piezoresistivity)• Grow stressors to induce channel strain along L• Tensile for NMOS, compressive for PMOS• Techniques: S/D epitaxy, stress memorization, gate stress

• Anisotropic mobility & stress response• L vs. W direction, (100) fin top vs. (110) fin sidewall

NMOS PMOS

Garcia Bardon et al., IMEC [5]Liu et al., Globalfoundries [6]

Slide courtesy of Alvin Loke, Qualcomm18

Bulk FinFET Processing Technology

19

A. Yagishita (Toshiba), SOI Short Course (2009)

• Increasing processing complexity

• More challenging lithography• Quad patterning

• Soon EUV

• Line edge roughness

• Isolation steps• STI

• CSD/SSRW

Courtesy of Michael P. King, Sandia

FinFET evolution at Intel

Zheng Guo et al. Intel. paper 11.1 Slide by E. HeijneFrom ISSCC 2018 20

Stress-Related Layout Effects• Stressors are stronger in 16/14nm for more FET drive, so layout

effects can be more severe schematic/layout Δ

• Stress build-up in longer active, ID/fin not constant vs. # fins

• Interaction with stress of surrounding isolation & ILD

• NMOS/PMOS stress mutually weaken each other

• New effects being discovered, e.g., gate-cut stress effect

NMOS

Faricelli, AMD [7]Lee et al., Samsung [8]

Sato et al., IBM [9]

PMOS

Slide courtesy of Alvin Loke, Qualcomm 21

Advantages / Challenges of FinFETs

M. G. Bardon (IMEC) ICICDT (2015)

Gate length shrinkPerformance scaling

FET is on edgeDual gateReduces Ioff

Courtesy of Michael P. King, Sandia22

Designing with FinFET• More drive current for given footprint

draincontact

well

spacer

gatesourcecontact

Sheu, TSMC [18]Hsueh et al., TSMC [19]

• Quantized channel width

– Challenge for logic & SRAM

– OK for analog, enough gm granularity

• Less DIBL better rout, 3 intrinsic gain

• Essentially no body effect (ΔVT < 10mV)

• Higher Rs & Rd spreading resistance

• Lower Cj but higher Cgd & Cgs coupling

• Higher Rwell (Rdiode, latch-up)

• Mismatch depends on fin geometry, MG grains, gate density, stress, less on RDF

Slide courtesy of Alvin Loke, Qualcomm23

I/O Voltage Not Scaling With Core Supply

• Many I/Os still use 1.8V signaling despite core VDD reduction• Many peripheral ICs remain at lower cost nodes• Backward compatibility is key constraint for some I/Os

• Increasingly tough to keep 1.8V thick-oxide devices• Thick-oxide HKMG ALD fill not easy for tighter fin pitch• More complex level shifters to deal with wider voltage gap• Some standards no longer support legacy modes in favor of

higher link rate & lower power (e.g., LPDDR5)

• Need ecosystem consensus• Industry has migrated from 5.0V to 3.3V to 2.5V to 1.8V• Obvious power & area benefit to migrate to say 1.2V• 1.8V remains an industry-wide issue until next transition

Wei et al., Globalfoundries [22]Slide courtesy of Alvin Loke, Qualcomm

24

Considerations for HEP Application

• Significant logic area scaling migrating to finFET• Though not as good as 4x reduction from 28nm to 14nm (marketing)

• Mature 14nm & 10nm process

• No model corner uncertainty less overdesign & perf. compromise• Hf-based HK gate dielectric reliability

• May be prone to hysteretic (ferroelectric) polarization & worse BTI at high radiation levels, causing undesirable VT shift

• HK polarization issues resolved for “typical” CMOS usage• Latch-up prevention

• High fin resistance enforces stricter well-tie spacing & guard ring DRCs

• Beta ratio (NMOS-to-PMOS drive strength) 1• Mechanical stressors & (110) fin sidewall much more effective to boost hole vs. electron

mobility strong PMOS• Device mismatch

• Fully-depleted structure intrinsically superior (less/no RDF)• Benefit reduced by new mismatch sources (fin dimensional control, MG grain

orientation, LDE sensitivities)

Slide courtesy of Alvin Loke, Qualcomm25

Looking ahead – scaling

• As a community we have accumulated (at least) 10 years delay since 1999

• With the 65nm process we cannot increase IO speed beyond 10Gbps

• We cannot stand still but going forward requires significant resources

• Below 28nm FinFETs become the workhorse• Increased gain, faster switching, lower leakage current• Increased layout restrictions (already at planar 28nm) • Radiation tolerance largely unknown (although initial indications not promising)

26

Looking ahead - chip stacking

Po-Sheng Chou et al.TSMC; paper 5.5

1.1 µm pixelsmotion detection

Oichi Kumagai et Sony; paper 5.4

1.5 µm pixelsevent driven10b ADC

TSMC example

27

Slide by E. HeijneISSCC 2014

Looking ahead - chip stacking

Wafer level stacking @ pixel pitch 6.9 mm

SONY example

28

Slide by E. HeijneISSCC 2014

Radiation tolerance requirement is strongly machine dependent

Here reference TID levels are in the innermost tracker layer (note that in some cases the forward calorimeters might be exposed to larger doses, such as in FCC-hh).For a lepton FCC machine, no

simulation of the detectors’ environment is still available.

Slide from Federico Faccio

29

TID leakage current can depend strongly on manufacturer

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Vgs (V)

Ileak (A

)

1/0.08

0.5/0.08

pre-rad annealing

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

TID (rad)

Ileak (A

)

1/0.12

1/0.24

1/0.5

1/1.6

1/3

1/5

pre-rad annealing

Figure 2: Leakage current evolution with TID for different transistor sizes: W array (left), L array (right).

A peak can be observed also in the evolution of the threshold voltage shift with TID

(Figure 3). It is interesting to observe that the dose at which the threshold voltage shift

peaks is the same as for the leakage current, i.e. 1Mrad. Thus, we can conclude that as

well as for the leakage current, the degradation of the threshold voltage is due to the

balance between positive charge trapped in the bulk of the STI and interface states

creation at the STI-Si interface and not to radiation effects in the gate oxide. This effect,

already observed in the 130nm CMOS process, is called Radiation-Induced Narrow

Channel Effect (RINCE) [1]. In narrow channel transistors (W≤ 1µm) radiation induced

defects in the STI not only determine the working conditions of the lateral parasitic

transistors but also influence the electric field of the main transistor. This gives origin to a

shift of the threshold voltage inversely proportional to the W. As we can observe in figure

3 (left) where the threshold voltage shift evolution as a function of the TID is shown for a

W array of transistors, the transistor with W=0.5µm has a bigger threshold voltage shift

than the transistor with W=1µm. It is interesting to observe (Figure 3, right) that given

the same W there is a small variation of the maximum threshold voltage shift value: the

longer the transistor the bigger the threshold voltage shift. For all the transistors sizes the

value of the threshold voltage shift is anyway negligible being of only a few mV.

-0.006

-0.005

-0.004

-0.003

-0.002

-0.001

0.000

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Vgs (V)

ΔV

th (V

)

1/0.08

0.5/0.08

annealing

-0.006

-0.005

-0.004

-0.003

-0.002

-0.001

0.000

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

TID (rad)

ΔV

th (V

)

1/0.12

1/0.24

1/0.5

1/1.6

1/3

1/5

annealing

Figure 3: Threshold voltage shift evolution with TID for different transistor sizes: W array (left), L array

(right). The threshold voltage shift has been extracted by linearly fitting the square root of the Ids vs Vgs

curve in saturation and finding the intercept with Ids=0A.

Figure 4 shows immediately that PMOS transistors are less affected by radiation than

NMOS. In the case of PMOS transistors both fixed charge and interface states are

positively charged and contribute to increase the threshold voltage shift of the parasitic

lateral transistors in such a way that no leakage current degradation is observed. The

small deformation of the Ids vs Vgs curve at Vgs<0V is due to a phenomenon called Gate

after L.Gonella et al., “Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments”, NIM A 582 (2007)

130nm bulk CMOS

90 nm bulk CMOS

Manufacturer A

Manufacturer B

30

TID leakage current can depend strongly on a particular plantFA C C IO et al.:R IS C E A N D N A R R O W C H A N N E L (R IN C E ) E F F E C T S 2 93 7

F ig.8. Ion decreas e w ith T ID for N M O S tran s is tors at differen t bias in the

6 5 n m n ode (room T ).T he bias effect is large an d can be obs erved even on

un m atched tran s is tors (on differen t chip s ).

T he m agn itude of the n arro w chan n el effect (R IN C E ) is

s m aller for the N M O S ,but the obs ervation of the degra-

dation of tran s is tors w ith differen t W [F ig. 6 (b)] reveals

in teres tin g details of the dyn am ic evolution of the defects in

the S T I oxide.A t m oderate T ID ,hole trappin g in the bulk of

the oxide dom in ates , lo w erin g the equivalen t of n arro w

chan n el tran s is tors [7],[16 ] an d in creas in g their .A t higher

do s es ,m o s t of the hole trap s are already occupied an d room -T

an n ealin g is active, s uch that additio n al do s e is les s efficien t

in accum ulatin g po s itive charge in the S T I.A t the s am e tim e,

laten t in terface trap buildup occurs w here electron s can be

trapped an d com pen s ate for the fiel d gen erated by the trapped

holes [16 ].A s a res ult, the differen ce betw een n arro w an d

w ide chan n els dis appears at aroun d a T ID of M rad .

A t higher do s es , the in terplay betw een R IN C E an d R IS C E

determ in es the n et degradation of the tran s is tors : the on ly

con tributio n of R IS C E is s een in the E L T tran s is tor of F ig.6 (b),

w hich has m in im um degradatio n . H o w ever, its com paris o n

w ith the lin ear tran s is tor w ith m in dicates that,as for

the PM O S ,R IN C E s till affects tran s is tors w ith this gate w idth.

T herefore, the approxim ate 5 % degradation of the larges t

available tran s is tor [ m ,in F ig.6 (a)] is traceable

to R IN C E an d n ot to effects in the thin gate oxide.

a) Effect of the Bias: T he electric field applied durin g the

irradiation has a s tron g in flue n ce on the phen om en a des cribed

before.In particular,the m agn itude of the R IS C E s eem s to be

s tron gly depen den t on the app lication of durin g irradiation .

In F ig.8, w e report the decreas e for iden tical tran s is tors

bias ed w ith a (1.2 V ) but w ith or w ithout : the abs en ce

of drain -s ource field m akes the dam age con s iderably m ilder.

N ot s ho w n are the an d S ubS in creas es that are als o m uch

s m aller.

a) Effect of the Temperature: A s for the PM O S ,radiation -

in duced dam age in creas es w ith tem perature in the explored T

ran ge ( 3 0 to C ).A ls o,for the N M O S ,the effect of the

applied bias is relevan t at room tem perature an d at C ,

w hile it is n egligible at C .

2) 130 nm Node: S am ples available in this techn o logy w ere

m an ufactured in tw o differen t productio n plan ts : w hile the ra-

diation -in duced leakage w as n egligible in on e cas e,it w as very

F ig.9. E volution of the s ource-drain leakage curren t (m eas ured for

0 V an d 1.2 V ) for m in im um -s ize N M O S tran s is tors in the 13 0 n m

n ode ( 0.15 /0.13 m ).T he irradiatio n took place at room T an d w ith a

1.2 V bias .

s ign ific

a

n t in the other (F ig.9).T his is a clear exam ple of ho w

s en s itive the radiation res pon s e can be to the proces s in g details

of C M O S m an ufacturin g: fres h tran s is to rs from the tw o plan ts

have iden tical electrical perform an ce,an d the m an ufacturer can

us e both plan ts for an y product,depen din g on the available pro-

duction capacity.H o w ever,the radiation toleran ce of the prod-

ucts — in the pres en t cas e— can be very differen t.

C on cern in g T ID effects o n the other tran s is tor param eters ,

N M O S devices appear to be very res ilien t up to the m axim um

do s e that w e reached ( M rad ).T he degradation is

lim ited to belo w 5 % ,w ith a com parable decreas e in an d

s hifts belo w 5 0 m V .W ith the degradation bein g s o s m all,it

is n o t po s s ible to dis tin guis h the pres en ce of R IS C E ,n either the

effect of tem perature an d bias .H o w ever,s om e m an ifes tation of

the R IN C E is eviden t for m in im um W tran s is tors as an in creas e

of the at m oderate do s es for n arro w chan n el tran s is tors .T his

effect is s im ilar to,but s tro n ger than the on e s ho w n in F ig.6 (b)

for the 6 5 n m n ode belo w M rad .

A lthough the radiation -in duced leakage curren t w as very dif-

feren t for s am ples from the tw o production plan ts ,this w as n o t

the cas e for all other characteris tics : T ID effects w ere iden tical

for all other param eters .

IV . D IS C U S S IO N

F rom our res ults o n the PM O S an d N M O S tran s is tors ,w e

can con clude that the thin gate oxide is affected little by T ID .

R adiation effects determ in in g the tran s is tor’s res pon s e occur in

thicker “paras itic” oxides .

A. RINCE in PMOS and NMOS Transistors

D efects in the lateral S T I oxide determ in e the perform an ce

degradation of n arro w chan n el tran s is tors (R IN C E ).F ig.10

com pares the evolutio n of P- an d N -chan n el tran s is tors

w ith m in im um W (0.12 m ) an d m oderately lon g L (1 m ).

C om pared to the data s ho w n in F ig.2 (a) an d 6 (b),w here all

tran s is tors in the W array had m in im um gate len gth an d w ere

hen ce heavily affected by R IS C E ,this figure en ables to better

s ort out the phen om en a behin d the n arro w chan n el effect alon e.

W hile the tw o types of defects in the S T I oxide (oxide trapped

after F.Faccio et al., “Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs”, IEEE TNS 62, n.6, Dec.2015

31

Some devices in some bulk processes are ok for HL-LHC

65nm bulk CMOS 28nm bulk CMOS

100Mrad

14 nm14 nm

32

But the device physics is complicated

STI = Shallow Trench Isolation oxide

Edge on view of gate Edge on view of channel Real edge on view of channel

Spacer Oxide and nitride(above source/drain LDD diffusion)

33

Radiation Induced Short Channel Effects (RISCE) and radiation induced Narrow Channel effects (RINCE)

paper ID# 1297

6

degradation of narrow channel transistors (RINCE). Fig. 10

compares the Ion evolution of P- and N-channel transistors

with minimum W (0.12 µm) and moderately long L (1 µm).

Compared to the data shown in Fig. 2.a and 6.b, where all

transistors in the W array had minimum gate length and were

hence heavily affected by RISCE, this figure better allows

sorting out the phenomena behind the narrow channel effect

alone. While the two types of defects in the STI oxide (oxide

trapped charge and interface traps) tend to compensate in the

NMOS, as discussed in III.B.1.a, they add up in the case of the

PMOS. For the minimum W transistor in Fig. 10, this positive

trapped charge modifies the electric field in the full transistor

transforming its characteristics: the transistor almost end up

behaving as a large resistor at doses above about

400 Mrad(SiO2).

B. Possible causes for the RISCE

We can exclude that the damage responsible for the RISCE

occurs in the STI oxide edgeless (ELT) transistors (as reported

in Fig. 2.b and 6.a) are insensitive to STI charging. Instead, it

may be traced to the region of the spacers, thick insulator

islands around the gate used in CMOS processing for

source/drain engineering – Fig. 11 shows a schematic view of

a transistor. Note that this is an example of a textbook process

flow, as we do not have any information on the construction of

the specific transistors used in our study. During the

manufacturing process, a moderate doping implant covering

the full drain/source area (extension module) is first applied to

produce a shallower and more lightly doped region. In the

successive spacer module, the spacer insulator is built with the

role of preventing the high doping implant of the source/drain

regions to reach the proximity of the channel. This gives

origin to the Lightly-Doped Drain (LDD) construction that is

efficient in reducing the electric field responsible for hot

carrier degradation. The construction of the spacer normally

starts with the deposition of a relatively thin oxide (about

15 nm) replacing the thermal oxide that has been damaged by

the source/drain extension implant: this deposited oxide is

likely to have a much worse quality, in terms of defects in the

bulk and interface, than the thermal gate oxide. On top of this

thermal oxide, a thick layer of nitride is deposited, which

normally contains hydrogen in some percentage.

Radiation can induce significant damage in this deposited

oxide and/or at its interface with the silicon (lightly doped

source/drain region), with significant charge trapping that can

be responsible for an electric field affecting the surface

potential in the LDD at high levels of TID. The consequences

on the electrical characteristics of the transistors differ

according to their polarity.

In PMOS transistors the LDD regions are lightly doped with

acceptors (p-). The accumulation of positive charge in the

spacer oxide at high TID can build an electric field effectively

lowering the net effective doping of the LDD region, or in

parts of it. As a result these regions would present a larger

resistance to current flow. However, this resistance is not an

access resistance independent from the applied gate voltage:

such a model does not match the experimental data. On the

contrary, it is reasonable to believe that the fringing field lines

at the edges of the polysilicon gate (closing on the

source/drain LDD regions) have an influence on this

resistance. Overall the transistor would be able to carry less

current (the effective mobility would be smaller) and some

characteristics dependent on the effective gate length might be

affected – all in agreement with our observations.

In NMOS transistors the LDD regions are lightly doped

with donors (n-). In this case the accumulation of positive

charge in the spacer oxide would tend to increase the net

effective doping of the LDD region without impacting the

current in the transistor (the native resistance of the LDD

region is already smaller than the channel resistance so that its

further decrease would be irrelevant). On the other hand the

effective doping of the LDD is an important parameter in

determining the response of the device to Hot Carriers

Injection (HCI). The reason to mention HCI here is that some

of our observations resemble damage mechanisms typical of

hot carrier stresses:

- Only the shortest channel transistors (L = 60 nm), with the

highest source-drain field, are significantly damaged.

- Interface traps are created, as suggested by a sizeable

increase of the subthreshold swing (more than

30 mV/decade for the shortest channel transistors, Fig. 7).

- The damage is strongly bias dependent, being very large

only in transistors biased with a large drain-source voltage

Fig. 10. Ion decrease with TID for minimum W transistors with moderately

long channel (1 µm). In NMOS, the compensation of the effects of oxide

trapped charge and interface traps makes the radiation performance much

better than in PMOS, where the two effects add up.

Fig. 11. Qualitative view of the construction of a MOSFET, showing the

spacers used for the Low-Doped Drain (LDD) engineering.

were either very large (W = 20 μm) or Enclosed Layout Tran-

sistors (ELTs, where the central diffusion is completely sur-

rounded by the poly-crystalline Si gate [11]). Results of these

different transistors were very comparable, confirming that

RINCE becomes negligible for very wide transistors (above

about 4 μm in our experience). Groups of identical transistors

with separate terminals were used to study the influence of the

bias on the radiation effects. Large ELT transistors (W =

10 μm) with different L and without ESD protection were used

for charge pumping and noise measurements, performed in a

restricted set of conditions (bias, temperature, transistor type).

Comparison of the results with those obtained for the complete

study of the arrays, where terminals were ESD protected, con-

firmed that ESD structures did not influence the results. We

focused our study on standard-Vth devices; however, results on

low- and high-Vth transistor arrays, not reported in this paper,

yielded comparable results.

B. Radiation sources and exposure conditions

The CERN X-ray irradiation system (Seifert RP149) was

used for most of the current/voltage measurements and for the

charge pumping study. This system uses a 3 kW tube with a

tungsten target and a 150 μm Al filter to generate ~ 10-keV X-

rays, a typical configuration for radiation-effects studies on

semiconductor devices [12]. Bare Si chips were kept under

bias and measured with the help of a wafer prober inside the

irradiation cabinet. A thermal chuck controlled the tempera-

ture of the samples between –30 and 100 °C. DC bias was

applied during irradiation and post-exposure annealing, most

often in a “diode” bias configuration where |Vgs| = |Vds| =

1.2 V, which was observed to generally produce the largest

degradation [1]. Unirradiated control devices (data not shown)

show less than 2% bias-temperature instability for the bias,

times, and temperatures used in these irradiation and annealing

studies. Other bias configurations were the “off” (all shorted)

and “on” (where |Vgs| = 1.2 V and Vds = 0 V) conditions.

The Pelletron at Vanderbilt University was used for irradia-

tion with 1.8 MeV protons of devices used for the noise study.

Here samples were mounted in ceramic packages and exposed

in the “diode” bias configuration at room T. Both facilities

allow for a very high dose rate, which is necessary to reach

TID levels up to 1 Grad(SiO2). Typical dose rates were ~ 9

Mrad/h for the X-ray tests, with similar, effective dose rates

for proton irradiation.

C. Measurement details

Static transistor measurements, mainly output and current

transfer characteristics, were taken with a semiconductor pa-

rameter analyzer (Keithley 4200A or HP 4155 for the X-ray

study, HP 4156 for the proton tests). The main parameters we

extracted from the raw data are the maximum current Ion (drain

current for |Vgs| = |Vds| = 1.2 V), the maximum transconduct-

ance in the linear regime (Gmmax), the subthreshold swing

(SSW), and the threshold voltage (Vth). The absence of radia-

tion-induced leakage current in NMOS FETs in the studied

technology allowed the precise extraction of all parameters,

and in particular Vth and SSW, in these devices.

Charge Pumping (CP) measurements were performed at the

University of Padova. This technique can be used to determine

the average interface-trap density of MOS transistors, as well

as the spatial distribution and energies of these traps [13],

[14]. The low-frequency 1/f noise of ELT PMOS transistors

with channel lengths of 60 nm to 480 nm was measured at

room temperature at frequencies f of 3 Hz to 390 Hz using the

apparatus and procedures shown in [15],[16], before and after

1.8-MeV proton irradiation, at Vanderbilt University. During

1/f noise measurement, devices were operated in the linear

mode of operation, with Vds = –30 mV and 0.1 ≤ |Vgs – Vth| ≤

0.5 V. At least two devices of each type were evaluated for all

experimental conditions, with typical results shown below.

III. RESULTS AND DISCUSSION

Transistors in the studied 65 nm technology exhibit two dis-

tinct radiation-induced degradation mechanisms. During irra-

diation, the drain current Ion decreases in both P and NMOS

transistors with inverse proportionality to the gate length

(Fig. 1), mainly because of the increase of the parasitic series

resistance. In addition, short-channel transistors also exhibit a

threshold voltage shift ΔVth that depends on bias and tempera-

ture. In PMOS FETs exposed at room temperature this mainly

takes place during post-irradiation high-T annealing (Fig. 2).

This behavior makes it possible to separately study the series

resistance and the threshold voltage shift: in this paper we will

hence focus our attention mainly on PMOS transistors.

A. Drain current decrease during irradiation

A relevant Ion decrease is observed during irradiation of

both N and PMOS FETs. This performance degradation gets

milder during cold exposures (-30 °C), is consistently larger

for shorter length devices, and almost negligible for gate

lengths above 1 μm (Fig. 1). In degraded transistors the most

relevant parameter change is the transconductance Gmmax,

whose evolution closely follows changes in current drive. A

detailed observation of the Gm = f(Vgs) curve at different doses

(not shown here) displays comparable decreases for the full

range of Vgs, suggesting that mobility degradation is not the

dominant mechanism – or the degradation would be smaller at

Fig. 1. Radiation-induced degradation of the current in strong inversion

(|Vgs| = 1.2 V) and in the linear regime (|Vds| = 20 mV) for PMOS and NMOS

ELT transistors “diode”-biased during exposure at room temperature up to

400 Mrad(SiO2).

PreRad 107

108

TID [rad]

-40

-35

-30

-25

-20

-15

-10

-5

0

5

I ON

[%

]

pMOS (ELT)

W=1.32 m;L=0.06 m

W=1.42 m;L=0.12 m

W=1.63 m;L=0.24 m

W=1.84 m;L=0.36 m

W=2.43 m;L=0.6 m

W=3.24 m;L=1 m

W=8.95 m;L=4 m

PreRad 107

108

TID [rad]

nMOS (ELT)

Vgs

=1.2V; Vds

= 20mV

after F.Faccio et al., “Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs”, IEEE TNS 62, n.6, Dec.2015

after F.Faccio et al., “Influence of LDD spacers and H+ transport on the total-ionizing-dose response of 65 nm MOSFETs irradiated to ultra-high doses”, presented at NSREC 2017, to be published in IEEE TNS Jan.2018

34

2642 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 10, OCTOBER 2017

Fig. 3. Transfer characteristics of n (a), (b) and p (c), (d) types ofMOSFETs in saturation mode (|VDS| = 1.1 V) with respect to TID.(a) and (c) are for DUT1 with the largest W/ L ratio (3 µm/30 nm).(b) is for nDUT10 with the smallest W/ L ratio (100 nm/1 µm) and (d) isfor pDUT9 with 100 nm/1 µm. ID0,of f is the off-current (VGS = 0) before

irradiation.

a higher amount of oxide trapped charges. This decreases the

threshold voltage, increases the on-current, and degrades the

subthreshold swing. The negative threshold voltage shift also

leads to a higher off-current for short-channel nMOSFETs.

Long-channel nMOSFETs present a lower off-current, which

could be explained by the compensation of the interface

charge trapping. The bias loss between 940 and 963 Mrad for

pMOSFETs explains the slight fluctuation of the extracted

parameters for the last two TID steps.

B. TID Effects on Transfer Characteristics

Fig. 3 plots the normalized drain current of nDUT1,

nDUT10, pDUT1, and pDUT9 with respect to TID. The

on-current (ID,on) is defined at |VGS| = 1.1 V, and the

off-current (ID,off) at VGS = 0. nDUT1 has a negative

threshold voltage shift and a monotonic on-current increase,

as shown in Fig. 3(a). Nevertheless, as seen in Fig. 3(b),

the threshold voltage of nDUT10 first decreases and then

increases, leading to the corresponding on-current evolution.

Both irradiated nDUT1 and nDUT10 have a significant

off-current increase. In contrast, the threshold voltage of both

pDUT1 [Fig. 3(c)] and pDUT9 [Fig. 3(d)] decreases with TID,

leading to a continuous on-current loss. Note that when the

threshold voltage of a pMOSFET decreases, it becomes more

negative and its absolute value increases. The off-current of

both pDUT1 and pDUT9 is not sensitive to TID and has a

slight off-current change.

C. On-current

The relative on-current variation is plotted as a function

of TID in Fig. 4. All nMOSFETs present an on-current

improvement at a lower TID (∼ 10 Mrad) in Fig. 4(a). Then

Fig. 4. TID-induced on-current (ID,on ) variation of (a) n and (b) p typesof MOSFETs in saturation mode (|VDS| = 1.1 V). ID,on is obtainedat |VGS| = 1.1 V.

Fig. 5. Drain current (ID) versus the overdrive voltage (VG − VT0) with

respect to TID for (a) and (b) n and (c) and (d) p types of MOSFETs insaturation mode (|VDS| = 1.1 V).

for nDUT1-5, the on-current increase continues until reaching

a ∼ 15% increase. However, the on-current of nDUT6-10 starts

to decrease at a higher TID. nDUT10 with the smallest W/ L

ratio (100 nm/1µm) evidences as the most dynamic case with

a maximum on-current loss of ∼ 25%. Fig. 4(b) shows that

pMOSFETs are grouped into two distinct categories: pDUT1-6

and pDUT7-9. In each group, the narrower the channel,

the higher the on-current loss. Eventually, most of pMOSFETs

show a less than 30% degradation in the on-current. Narrow-

channel pMOSFETs with a smaller W/ L (pDUT6 and

pDUT8-9) present a more than 50% on-current loss.

Nevertheless, these results are much better compared with

the commercial 65-nm bulk CMOS technology from the same

foundry [9].

Both the threshold voltage (VT0) shift and the free carrier

mobility (µ ) reduction influence the on-current. To extract

VT0 and µ ,√

ID–VG curves are extrapolated linearly at the

maximum slope. The intercept at the VG axis is defined as VT0.

The slope of the linear extrapolation provides insights into µ .

after C.Zhang et al., “Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28 nm Bulk MOSFETs”, IEEE TNS 64, n.10, Oct.2017.

PMOSNMOS

Short channel

Narrow channel

35

28nm shows pronounced RINCE but little RISCE

Results from Scaltech28 (INFN) and GigaRadMOST (SNSF)

CHATTERJEE et al.: BIAS DEPENDENCE OF TOTAL-DOSE EFFECTS IN BULK FinFETs 4477

Fig. 1. 3D schematic illustration of a triple-well bulk FinFET.

Fig. 2. (a) Top-down SEM image of the structure of the FinFETs. (b) Cross-

sectional TEM image of an nMOS FinFET showing the fin structure [15].

III. EXPERIMENTAL DETAILS

Transistors were irradiated at room temperature with

10-keV X-rays using an ARACOR Model 4100 irradiator at

a dose rate of 31.5 krad SiO min to a cumulative dose of

300 krad SiO . The bias conditions during irradiation corre-

spond to 1) on-state (ON) and 2) off-state (OFF) for inverter

and 3) transmission gate (TG) operation. Other bias conditions

were also tested, with the source, drain, and gate either at 0 V

(ALL-0), and/or at negative gate bias, as shown in Table I. The

body and triple-well were held at 0 V and 0.7 V respectively

during all the irradiation experiments.

Current-voltage ( ) characteristics were measured with

an Agilent 4156 semiconductor parameter analyzer on unpack-

aged wafers. During measurements, both the source and the

Fig. 3. characteristics as a function of dose for irradiation at a dose

rate of 31.5 krad SiO min. The drain was biased at 0.7 V, the fin width is

13 nm, and the devices comprise 4 fins.

substrate were grounded, and a 50 mV bias was applied to the

drain. The gate voltage was varied from 0.3 V to 0.7 V. The

body terminals were grounded for all the bias conditions. The

triple-well (deep n-well) terminal was held at . Annealing

experiments were performed at room temperature, with all ter-

minals grounded, to understand the subthreshold slope modula-

tion in irradiated FinFETs.

IV. EXPERIMENTAL RESULTS AND DISCUSSION

A. Off-state Leakage Current

Total-ionizing-dose irradiation induces net positive trapped

charge in oxides and interface traps at silicon/oxide interfaces.

The extremely small increase in post-irradiation gate leakage

observed in these transistors suggests that there were no leakage

paths created in the gate insulator stack (Fig. 3). There is little

shift in the threshold voltage following irradiation, indicating

that the trapped charge in the gate insulator is quite small. How-

ever, similar to trends observed in planar CMOS technologies,

the radiation-induced charge trapping in the STI oxide still leads

to macroscopic effects, such as the drain-to-source leakage cur-

rent, and ultimately limits the radiation tolerance of CMOS cir-

cuits [16]. Thus, the post-irradiation response of these bulk Fin-

FETs is dominated by buildup of charge in the isolation oxides

(the shallow trench isolation) around the transistors. If an elec-

tric field exists across an insulator during total dose irradiations,

electrons and holes in the insulator will immediately begin to

transport in opposite directions. Electrons are extremely mobile

in the silicon oxides and are normally swept out of it in picosec-

onds [17], [18]. Holes generated in the silicon oxides transport

much slower than electrons and a substantial fraction may be

trapped. As a result, hole trapping usually determines the tran-

sistor response after irradiation. As the electric field increases,

the probability that a hole will recombine with an electron de-

creases and the fraction of un-recombined holes increases [19].

4478 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 60, NO. 6, DECEMBER 2013

Fig. 4. Schematic showing the trapped charges in the isolation oxide in a

multi-fin FET (representative figure only, not to scale). [20].

The electric field extends into the trench region and plays a piv-

otal role in both the initial separation of electron–hole (e–h)

pairs and the charge migration. Fig. 4 shows an illustration of

the trapped charges in the isolation oxides.

In contrast, for SOI FinFET devices, positive trapped charge

in the BOX is a greater concern. In FD SOI devices, charge trap-

ping in the BOX can affect the device degradation through a

direct coupling effect between the front and back interfaces. In

non-planar multiple-gate devices, the coupling behavior is dif-

ferent and complex, especially as fin widths and gate lengths

decrease below 130 nm. A lateral coupling effect induced by

the lateral gates appears in addition to the vertical coupling ef-

fect of single-gate devices [6], [8]. These complex electrostatic

coupling effects are strongly geometry dependent.

Fig. 5 shows a schematic diagram of the trapped charges in

the buried oxides. A wide-fin FinFET is similar to a “pseudo”

single-gate FD SOI transistor. Its electrostatic behavior is dom-

inated by the front and back gates. The electrostatic control of

the lateral gates over the potential in the active silicon film and

in the BOX under the silicon-film/BOX interface is weak [11].

Ionizing radiation exposure induces a positive charge buildup in

the BOX of SOI devices, which increases the back-gate surface

potential [21]–[23]. In single-gate FD SOI devices, the charge

trapped in the BOX acts as a positive back-gate bias. Because

of the strong vertical electrostatic coupling effects, the front

surface potential increases and induces a negative front-gate

threshold voltage shift. For narrow fin devices, on the other

hand, the primary effect is the screening of the trapped charges

into the BOX due to the strong electrostatic control of the lateral

gates when they are close to each other. The electrostatic poten-

tial in the silicon body and in the BOX under the Si fin/BOX

interface is dominated by the lateral gates, thereby limiting the

amount of radiation-induced hole charge trapped in the middle

of the channel [6]–[8].

The bias applied to the transistor terminals during exposure

to radiation is a critical parameter influencing charge trapping.

For fully depleted SOI transistors, the worst-case bias is fab-

rication process dependent. For partially-depleted SOI tran-

sistors, the worst-case bias conditions are when source and

drain are at with other terminals grounded (the trans-

mission-gate configuration) [24]. For some fully-depleted SOI

Fig. 5. Schematic showing the trapped charges in the BOX in a SOI

omega-FET (representative figure only, not to scale). [7].

technologies, the worst-case bias condition is the same as that

for partially-depleted SOI transistors, the Transmission-Gate

configuration, causing the most radiation induced charge trap-

ping in the buried oxide [25]. However, for other technologies,

the worst-case bias condition was determined to be the ON

bias configuration (gate at , other contacts grounded) [26],

[27].

Fig. 6 shows the pre- and post-irradiation character-

istics for the five bias conditions under consideration. The

highest increase in off-state leakage is observed for the OFF-

state bias condition, for all doses considered. The pre-rad off-

state leakage is 1 pA and increases to 25 nA after a cu-

mulative dose of 300 krad SiO . The smallest shift is ob-

served in the case of the negative gate and ALL-0 bias condi-

tion. The off-state leakage for these bias conditions increased

from 1 pA (pre-rad) to 100 pA 300 krad SiO . Fig. 7

shows vs. cumulative dose for the bias conditions under

consideration. At low dose, the high electric fields in the cor-

ners of the shallow trench isolation are partly responsible for

the increased transistor leakage current [16], [25]. The simu-

lations detailed in Section V show that the electric field at the

trench corners is highest for the OFF state bias. There are a

large number of oxygen vacancies in the STI close to the sil-

icon/oxide interface due to the out diffusion of oxygen near

the oxide and the lattice mismatch at the surface [16], [19].

These oxygen vacancies can act as trapping centers. Some

fraction of the holes will be trapped there, with the fraction

strongly related to the electric field in the oxide during irra-

diation [16], [26]. The overall response of bulk FinFETs is

similar to planar bulk MOSFETs in terms of the parasitic tran-

sistor dominating the radiation response of the devices.

B. Parasitic Transistor Threshold Voltage Shift

At a high dose, the leakage current becomes relatively inde-

pendent of gate voltage, which means that the parasitic tran-

sistors play an important role for the leakage current. The ac-

tual threshold voltage shift is calculated after subtracting the

leakage current from the measured characteristics. The in-

significant shift in threshold voltage shift observed is because

of a relatively small amount of charge trapping in the gate insu-

lator stack. As the fin width is less than 15 nm, the electrostatic

CHATTERJEE et al.: BIAS DEPENDENCE OF TOTAL-DOSE EFFECTS IN BULK FinFETs 4479

Fig. 6. characteristics as a function of dose for irradiation at a dose rate of krad SiO min for the various bias conditions under consideration.

The DUT is 4-fin 90 nm FinFET. (a) ON state. (b) OFF state. (c) ALL-0 state. (d) Negative gate. (e) Transmission gate (TG).

potential is predominantly controlled by the lateral gates, fully

depleting the silicon fin in the ON state. The longitudinal pen-

etration of the fringing electric field from the source and drain

to the channel, e.g., the drain-induced virtual substrate biasing

(DIVSB) effect [8], is prevented. Fig. 8 shows the threshold

voltage shifts in the DUTs after subtracting the leakage current

from the measured characteristics.

Fig. 9 shows the subthreshold swing ( )

of the 90-nm-gatelength FinFET as a function of dose for the

worst case and best case bias condition. The swing was mea-

In FinFETs source-drain leakage due to oxide charging occurs

36

A Tale of Two Commercial Processes

• Typically comes about when they fix a leakage problem

• Impossible to say if TID resilience remains a permanent feature of the technology going forward

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.210-6

10-5

10-4

10-3

10-2

10-1

100

101

102

103

104

Medium-Vth Device

On-state

Vgs = 1.0 V

Dra

in C

urr

en

t (m

A/m

m)

Gate Voltage (V)

Initial

100 krad(SiO2)

200 krad(SiO2)

300 krad(SiO2)

500 krad(SiO2)

1000 krad(SiO2)

Two snapshots of a commercial 14/16-nm FinFET technology show very different TID results

-0.2 0.0 0.2 0.4 0.6 0.810-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

LVT Dev 1

I ds (

mA

)

Vgs (V)

pre

100 krad

200 krad

300 krad

400 krad

500 krad

1 Mrad

Vg = 0.8 V

Vd = Vs = Vb = 0 V

W = 0.192 mm

L = 0.014 mm

Courtesy of Michael P. King, Sandia 37

Approach to R and D for Future IC Technologies

1. List of topics were drawn up:

• Pixel detector readout (hybrid) – monolithic is in Si WP• Strip detector readout• Calorimeter readout• Muon Detector readout• Control and monitoring

Slow control ADC, DACs etc• Trigger generation• Fast timing• Power supply distribution

DCDCLinear regulators

• Serial powering

• NB This list covers the applications of the Technologies. They must inform the technology choice but this R and D focusses on the technologies themselves, not the particular circuit solutions

38

Approach to R and D for Future IC Technologies

2. Some key players were identified and contacted

3. A Vidyo meeting was held on 5th

March to gather inputs:

4. Each presentation was followed by a discussion

/indico.cern.ch/event/704624

39

Some preliminary observations/conclusions

• Future experiments will rely on ASICs

• ASIC interconnect technology (TSV, bump bonding) should be included in the work package as it depends on or is inseparable from the ASIC Technology chosen

• As a community we would benefit from accessing newer technologies but large projects ($$$$) are needed to justify the effort to access such processes

• The provision of tools via Europractice has been vital for our community

• Access to technologies and the appropriate tailored design kits is also essential

• Many of our designs are still done in the ‘old fashioned’ analog way. This is already changing e.g. RD-53, MPA, SSA, Velopix etc

• Qualification of devices for operation sometimes falls between the cracks of the design team and the users

• Could we benefit from closer collaboration with other fields (ITER, synchrotrons..)?

40

Preliminary list of needs for IC Technology development

• CERN Microelectronics should continue to study and select (along with the design community) appropriate technologies to act as a common platform for developments.

• A deep understanding of radiation effects is essential

• Equally important is the provision of tailor made design kits for our community

• Designs can only be done using the latest tools

• Europractice needs our strongest support!

• Training in the new tools is essential to make the most of new opportunities

• More young (digital) engineers are needed

• We must learn to work in large collaborative efforts. 41

A few unpleasant practical facts - inconvenient truths?

• Our community represents a tiny fraction of the world market in microelectronics. The only leverage we have is good will.

• NDA’s take an age to negotiate but are an absolute necessity to enable collaborative work. They must also be scrupulously respected.• Confidential foundry information • Use restrictions• Export controls

• Accessing such technologies will not be cheap, but not going there could be even more costly

42

One optimistic scenario:

• FCC or CLIC gets approved and 1 000m2 of tracker needs to be constructed.

• We agree to use the same technology for all 1 000m2

• This represents 28 000 300mm wafers @ $1k per wafer (assuming 50% yield)

• Because of the extreme radiation these should be replaced every 5 year or so.

• We suddenly become an interesting client for a leading edge company with wafer stacking.

“You may say I’m a dreamer…”

“…but I’m not the only one…”

Jacques Dubochet, Nobel Prize for Chemistry 2017 after John Lennon.

https://www.nobelprize.org/nobel_prizes/chemistry/laureates/2017/dubochet-lecture.html

43

So what’s next?

• Complete work on understanding radiation tolerance of current processes and define qualification protocol

• Start to test 28nm and FinFET devices to understand the physics

• Put in the place the necessary infrastructure to allow us access to these processes• NDA’s• Technology files and support• Foundry access • Training

• Continue to work as a community to restructure our efforts to permit the design of future complex ASICs

• More fledged out plan to be presented at second meeting44

Thank you for our attention!

45