Fundamentals of Computer Systems - Finite State Machines

Fundamentals of Computer SystemsFinite State Machines

Stephen A. Edwards

Columbia University

Spring 2012

Finite State Machine Components

CL

CL

CLOCK

Next State Current State

Current State

Inputs

Next State

Current State

Inputs?

Outputs

Moore and Mealy Machines

Next StateLogic

Output Logic

CLK

NextState

CurrentState

Inputs Outputs

The Moore Form:

Outputs are a function of only the current state.

Moore and Mealy Machines

Next StateLogic

Output Logic

CLK

NextState

CurrentState

Inputs Outputs

The Mealy Form:

Outputs may be a function of both the current state andthe inputs.

A mnemonic: Moore machines often have more states.

Mealy Machines are the Most General

CLCurrentState

Next State

Inputs Outputs

CLK

Another, equivalent way of drawing Mealy Machines

This is exactly the synchronous digital logic paradigm

Moore vs. Mealy FSMs

Alyssa P. Hacker has a snail thatcrawls down a paper tape with1’s and 0’s on it. The snail smileswhenever the last four digits ithas crawled over are 1101.Design Moore and Mealy FSMs ofthe snail’s brain.

State Transition Diagrams: Looking for “1101”

S00

Moore Machine: States indicate output

S0

Mealy Machine: Arcs indicate input/output


S00

S10

1

0


S0



S00

S10

S20

S30

S41

1

0

1 0 1


S0



S00

S10

S20

S30

S41

1

0

1 0 1

01

0

1

0


S0



S00

S10

S20

S30

S41

1

0

1 0 1

01

0

1

0


S0



S00

S10

S20

S30

S41

1

0

1 0 1

01

0

1

0


S0 S11/0

0/0



S00

S10

S20

S30

S41

1

0

1 0 1

01

0

1

0


S0 S1 S2 S31/0

0/0

1/0 0/0

1/1



S00

S10

S20

S30

S41

1

0

1 0 1

01

0

1

0


S0 S1 S2 S31/0

0/0

1/0 0/0

1/10/0

1/0

0/0


Moore Machine

Next StateS A S’

S0 0 S0S0 1 S1S1 0 S0S1 1 S2S2 0 S3S2 1 S2S3 0 S0S3 1 S4S4 0 S0S4 1 S2

OutputS Y

S0 0S1 0S2 0S3 0S4 1

CLK

CLK

CLK

S′0

S′1

S′2

A

S0

S1

S2Y

Moore Machine

Next StateS A S’

000 0 000000 1 001001 0 000001 1 010010 0 011010 1 010011 0 000011 1 100100 0 000100 1 010

OutputS Y

000 0001 0010 0011 0100 1

CLK

CLK

CLK

S′0

S′1

S′2

A

S0

S1

S2Y

Mealy Machine

S A S’ Y

S0 0 S0 0S0 1 S1 0S1 0 S0 0S1 1 S2 0S2 0 S3 0S2 1 S2 0S3 0 S0 0S3 1 S1 1

CLK

CLK

S′1

S′0

A

S0

S1

Y

Mealy Machine

S A S’ Y

00 0 00 000 1 01 001 0 00 001 1 10 010 0 11 010 1 10 011 0 00 011 1 01 1

CLK

CLK

S′1

S′0

A

S0

S1

Y

More Intuitive Solutions using Shift Registers

A

Y

CLK

Mealy Form: Output Depends on Input Immediately

A

Y

CLK

Moore Form: Output Depends Only on State

FSM Example: A Traffic Light Controller

C

C

This controls a trafficlight at the intersectionof a busy highway and a farmroad. Normally, the highwaylight is green but if a sensordetects a car on the farmroad, the highway light turns

yellow then red. The farm road light then turns greenuntil there are no cars or after a long timeout. Then, thefarm road light turns yellow then red, and the highwaylight returns to green. The inputs to the machine arethe car sensor, a short timeout signal, and a longtimeout signal. The outputs are a timer start signal andthe colors of the highway and farm road lights.Source: Mead and Conway, Introduction to VLSI Systems, 1980, p. 85.

State Transition Diagram for the TLC

HGH : GF : R

HYH : YF : R

C+ L/TCL/T

FGH : RF : G

FYH : RF : Y

S/T

S/T

CL/TC+ L/T

S/T

S/T

Inputs:C: Car sensorS: Short TimeoutL: Long Timeout

Outputs:T: Timer ResetH: Highway colorF: Farm road color

S H F

HG G RHY Y RFG R GFY R Y


HGH : GF : R

HYH : YF : R

C+ L/TCL/T

FGH : RF : G

FYH : RF : Y

S/T

S/T

CL/TC+ L/T

S/T

S/T



S H F



HGH : GF : R

HYH : YF : R

C+ L/TCL/T

FGH : RF : G

FYH : RF : Y

S/T

S/T

CL/TC+ L/T

S/T

S/T



S H F



HGH : GF : R

HYH : YF : R

C+ L/TCL/T

FGH : RF : G

FYH : RF : Y

S/T

S/T

CL/TC+ L/T

S/T

S/T

S C S L T S’

HG 0 X X 0 HGHG X X 0 0 HGHG 1 X 1 1 HYHY X 0 X 0 HYHY X 1 X 1 FGFG 1 X 0 0 FGFG 0 X X 1 FYFG X X 1 1 FYFY X 0 X 0 FYFY X 1 X 1 HG



S H F


State and Output EncodingS C S L T S’


S H F


First idea: use a binaryencoding:

HG 00HY 01FG 10FY 10

G 00Y 01R 10


00 0 X X 0 0000 X X 0 0 0000 1 X 1 1 0101 X 0 X 0 0101 X 1 X 1 1010 1 X 0 0 1010 0 X X 1 1110 X X 1 1 1111 X 0 X 0 1111 X 1 X 1 00

S H F

00 00 1001 01 1010 10 0011 10 01

T = S1 S0CL+ S1S0S +

S1S0(C+ L) + S1S0S

S′1 = S1 S0S+ S1 S0 +

S1 S0S

S′0 = S1 S0CL+ S1 S0 S +

S1 S0(C+ L) + S1S0S

H1 = S1

H0 = S1 S0

F1 = S1

F0 = S1 S0



S H F

00 00 1001 01 1010 10 0011 10 01

T = S1 S0CL+ S0S +

S1S0(C+ L)

S′1 = S0S+ S1 S0

S′0 = S1 S0CL +

S0 S+ S1 S0(C+ L)

H1 = S1

H0 = S1 S0

F1 = S1

F0 = S1 S0



S H F

00 00 1001 01 1010 10 0011 10 01

T = S0�

S1CL+ S1(C+ L)�

+

S0S

S′1 = S0S+ S1 S0

S′0 = S0�

S1CL + S1(C+ L)�

+

S0 S

H1 = S1

H0 = S1 S0

F1 = S1

F0 = S1 S0

State and Output Encoding

10

10

10

10

CL

C

LS1

T

S′1

S′0

S

SS1

S

S0

S1

F1

S0H0

S1

H1

S0F0

T = S0�

S1CL+ S1(C+ L)�

+

S0S

S′1 = S0S+ S1 S0

S′0 = S0�

S1CL + S1(C+ L)�

+

S0 S

H1 = S1

H0 = S1 S0

F1 = S1

F0 = S1 S0



S H F


Second idea: use a one-hotencoding:

HG 0001HY 0010FG 0100FY 1000

G 001Y 010R 100



S H F

0001 001 1000010 010 1000100 100 0011000 100 010

T = S0CL+ S1S +

S2(C+ L) + S3S

S′3 = S2(C+ L) + S3S

S′2 = S1S+ S2(C+ L)

S′1 = S0CL+ S1S

S′0 = S0(CL) + S3S

HR = S2 + S3

HY = S1

HG = S0

FR = S0 + S1

FY = S3

FG = S2

State and Output Encoding

S′0

S′1

S′2

S′3

S0

HG

S1

HY

FR

HR

S

S2

FG

C

L

S3

FY

T = S0CL+ S1S +

S2(C+ L) + S3S

S′3 = S2(C+ L) + S3S

S′2 = S1S+ S2(C+ L)

S′1 = S0CL+ S1S

S′0 = S0(CL) + S3S

HR = S2 + S3

HY = S1

HG = S0

FR = S0 + S1

FY = S3

FG = S2

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Fundamentals of Computer Systems - Finite State Machines