FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART Ijose-silva-martinez/courses... · Fundamentals on ADCs: Part I Jose Silva-Martinez Efficient radio transceiver: Direct Conversion

Texas A&M University 1 Spring, 2019

Fundamentals on ADCs: Part I Jose Silva-Martinez

Jose Silva-Martinez

Many of these slides were provided by

Dr. Sebastian Hoyos

January 2020

FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1



• Fundamentals of Analog-to-Digital Converters

– Introduction

– Sampling and Quantization

– Quantization noise and distortion

– INL and DNL

– Technological related issues

– Sample and Hold

– Switching issues

– S/H Accuracy

– Active S/H

– Switch around S/H

Outline



R. Walden, 1999



What is an Analog-to-Digital Converter (ADC)?Analog

Continuous with no apparent discontinuities

The way we interpret our surroundings: sound, light, temperature … etc

Digital01001011001010010101010101010100101001010010100101010010010010010110011001010100100101001001010

Discrete with limited range; based on binary numbers with limited number of bits.

The way we mathematically represent and process our world using electronic “brain” power

ADC



How does an ADC work?Analog Digital

Continuous with no apparent discontinuities

The way we interpret our surroundings: sound, light, temperature … etc

10010100101001010010011001011001010

01001011001010010101010101010100101001010010100101010010010010010110011001010100100101001001010

ADC Discrete with limited range; based on binary numbers with limited number of bits.

The way we mathematically represent and process our world using electronic “brain” power



How does an ADC work?x(t)

t

Analog Digital

10010100101001010010011001011001010

ADC

δ(n)

nTS

x(n)

nTS

2N Levels separated by 1LSB, 1LSB = VFS

* / 2N

* VFS = full scale range, Vmax-Vmin

Quantization noise



ADCs are indispensable, but now need to handle smaller signals at higher speeds with similar or higher resolutions.

ADCs: Yesterday vs. TodayExample: Digital photography (8-12b ADCs)

Yesterday: 2000

CCD/CMOS Image Array

Balance Control

DSP(black level

compensation , encoding ...etc)

AMP ADC

0.5-0.8µm CMOS with 5V supply (moderate gate density and speed in DSPs)

2M pixel CCD sensor (low pixel scanning speed) Some pre-ADC analog conditioning ~ 2.5mV / LSB

Today: 2009

DSP(balance control, black level

compensation, image stabilization, exposure levels, noise reduction, lens shading

correction, encoding...etc)

AMP

CCD/CMOS Image Array

ADC

90nm-180nm CMOS with 1.2-1.8V supplies (high gate density and speed in DSPs)

12M pixel CCD sensor (high pixel scanning speed) Minimal pre-ADC analog conditioning ~ 0.5mV / LSB

Faster DSPs capable of performing numerous complex functions are developed thanks to advanced CMOS technologies.

ADCs are becoming the bottleneck for advancement, and new design techniques need to be developed.



ADCs: Tomorrow?ADC IEEE literature survey: 2006-2008

Pipeline ADC is currently most published architecture Pipeline ADC is breaking the trend set by Sigma-Delta and Flash ADCs Pipeline ADC is expected to be a key ADC architecture in future applications

2468

101214161820

0.1 1 10 100 1000 10000Signal Bandwidth (MHz)

Res

olut

ion

(bits

)

0.01

Sigma-DeltaPipelinedFlash

The development of new design techniques for high speed, low voltage and low power ADCs is crucial to stay on the future applications roadmap

Pipeline ADC is breaking the trend set by Sigma-Delta and Flash ADCs, and driven by consumer electronics



Multi-standard Wireless Systems– Multiple services

– Reuse circuits as much as possible• Power• Area• Competitiveness

– Smaller Cell phone,stronger function,longer battery duration

– Use of digital (analog unfriendly) nanometric tecnologies



Super-heterodyne Receiver

Invented by Armstrong in 1918 Hardware specific radio architectureExtensive filtering to relax ADC specsSuitable for narrow-band applications



Design issues for multi-standard solutions

Excessive power at the front-end (Linearity issues) Extensive down conversions: LO and mixers increase

both noise and power consumption Extensive filtering: Area, Power and Noise issues Not fully compatible for the Telecoms roadmap

Limited by flicker noise

Not flexible

Hardware intensive



Current Multi-standard designs

BPF LNA BPFVGA

LO2LO1

RF(1-2 GHz)

IF(100-200 MHz)

Antenna

RFSwitch

Receiver for standard 1

BPF LNA BPFVGA

LO2LO1

RF(1-2 GHz)

IF(100-200 MHz)

Receiver for standard 2

Minimum sharing of blocks

Area and powerconsumption overhead

Not Flexible at all

Limited number of standards can be accommodated



Efficient radio transceiver: Direct Conversion

Direct conversion + broadband ADC (1 receiver per service) Lowpass filter is required (~ 50-100 mW) 13-14 bits 80 MHz Lowpass ADC (500 mW from ADI) Bank of receivers, filters and ADCs

Antenna

RFsignal

Software Platform

DSP

or

FPGAs

LNA & VGA

16-Channel Multiband Digital Receiver

RF Filter 1 ADC 1IF Filter 180 MHz

4-channel digital

receiver

4-channel digital

receiver

ADC 2IF Filter 24-

channel digital

receiver

4-channel digital

receiver

Antenna

RFsignal

LNA & VGARF Filter 2

Optional

Mixer

Mixer

Frequency Synthesizer



How much RF processing should be done before the ADC? The front-end must be scalable and configurable to fit multiple standards

Roadmap for high-resolution Receivers



The single-chip Transceiver Paradigm15

Critical Analog components must be minimized

• Modern technologies:“Digital intensive” System-on-Chip (SOC) environmentScaling of transistor dimensions in digital CMOS technologiesIncreased intra-die variability from device scalingDefect densities increase in newer technologiesYields decrease as SOC chip sizes increaseYield impact on analog specifications leads to process corner-based overdesignto allow for analog parameter variations Increased test cost

M. Onabajo, 2011



Software radio transceiver: Design Issues

Makes it sense to have a multi-standard solution based on this architecture?

Bandwidth required? Dynamic range required? DTV SNRsignal=25 dB; Blockers > 45 dB; Crest factor > 20 dB LNA+VGA+ADC Dynamic Range over 90 dB (practical ?) Can you use tracking filters? (back to the past)



Ultimate goal: Reality or Dream

Concept introduced in 1991 Modulation/demodulation waveforms in software Flexible multi-standard software architecture



R. Walden, 1999



WiMAX

Where we were in 99? Where we are?





A Little bit of History



A Little bit of History



Jitter and noise limitations on ENOB



The quantized signal presents a finite number of output values that are associated with digital codes

Data Converters: The main issue



What the problem is?



The quantized signal presents a finite number of output values that are associated with digital codes

Issues: Sampling, Holding and conversion



Properties of the Fourier Series

Modulation properties

Convolution in time



Relevant properties of the Fourier Series

Product in time



Relevant properties of the Fourier Series



Additional properties of the Fourier Series



Define the problem: Sampling Operation



Sampling Operation: Nyquist Rate

According to the sampling theorem: If no alias issues, then

Ideal sampling does not add distortion but replicas of the original spectrum



Signal Sampling Theorem

Time domain sampling

Frequency Spectrum



Signal Sampling employing a train of pulsesTime domain sampling with pulses

Spectrum





Sampling

kscs

sk

s

FT

cs

ccs

kXT

jX

Tk

Tts

jSjXjX

nTttxtstxtx

1

2,221

T

ksc

Ts

n

nj

kXT

jX

znxeX

1

δ(t-nT)

xs(t)

t0 T 2T 3T 4T T

xc(t)·δ(t-nT)





Notice in the afore equation that the delay due to exp(-jfT) has being ignored

In practice, this term corresponds to a signal delay of T/2 seconds!



The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively

Quantization generates harmonic distortion components when sinusoidal input signals are used

S/H and Quantization errors



Distortion due to S/H errors

tVtVtV error0PKd sinThe S/H signal can be expressed as:

The first part of this equation does not generate any distortion since it is a pure sine wave function

The error signal is input dependent and non-linear! Fundamental component is at the signal frequencyIt can be expanded in a Fourier series and then the harmonic components can be found



Distortion due to quantization errors: Ramp

Nv1Nif1Nv2

v ininin

In general, the quantization error can be expressed as:

For the case of a ramp input signal, then Vin(t)=Kt, then

You may want to find the Fourier series that represent this sawtooth error function to find the harmonic distortion components.

NKt1Nif1N2

Ktt

or

NV1Nif1N2

tVt inin



The problem is more complex for a sine function, the quantization error can be expressed as a kind of frequency modulation function See Van dePlassche , pp. 14:

Interestingly, this complex expression can be simplified for n-bit converters, leading to a very simple result for the third order harmonic distortion

Distortion due to quantization errors: Sinusoidal input

oddispiffunctionBesselcomplexA

evenispif0A

pAv

p

p

1ppin

sin

1n2componentlfundamentaofPower

componentharmonicrd3ofPower3HD n51 .



For 10-Bit ADC, HD3 is in the range of -90.31 dB

HD3 reduces at a rate of -9dB per additional Bit

After 10 bits, this distortion can be easily ignored


n5123HD

.




Notice that SNR is over 20dB more relevant than HD3 for n>=7

n223IM

For the case of intermodulation distortion using a couple of test tones, it is found



Alias issue if undersampling





Under-sampling of a broadband signal



The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively

Error is an odd function (no even harmonic distortions, why?)

Quantization generates harmonic distortion components when sinusoidal input signals are used

S/H and Quantization errors

Freq Freq

Error signal

Quantized signal

tErrortStS qin



Distortion due to quantization errors



ADC metrics: Quantization error• Signal is sampled at given instants• Signal is encoded to a limited number of codes resulting in

quantization noise (random signals) and distortion (periodic signals)





What the fundamental problem is?Mapping an infinite resolution analog signal into a digital but finite resolution representation



Quantization noise for Random (Ramp) input signal





dB.N./

/P

/APP

SQNRN

noisenoise

signalideal 761026

12222

2

22

The maximum Signal-to-Quantization Noise ratio (SQNR) for an N-bit ADC:

02.676.1)dB(SNDRENOB

• For an ADC with a measured SNDR, the effective number of bits is defined as:

ADC metrics: SQNR



The dynamic range of a system is equal to the signal to noise ratio measured over a bandwidth equal to half of the sampling (Nyquist) frequency

Then,

Is the total while the quantization noise density (quantization noise measured in a bandwidth of 1 Hz)

s

2

s

2

22

f6

q

f

2densityNoise

12

q

Quantization noise density

fs/2-fs/2











Practical Limitations



Digital to Analog Converters



Practical Definitions







Quite critical issue! Usually not a major issue



Practical Limitations: Offset error




Usually not a major issue Quite critical issue!



Practical Limitations: Gain error



Practical Limitations: Differential Error






Practical Limitations: Integral error






Practical Limitations: Absolute Accuracy



Analog to Digital Converters

Usually the effects

of the systematic

offsets can be

minimized through

calibration or

accounted in

digital domain



Digital to Analog Converters










DNL must be smaller or equal to 1 LSB






Offset Voltages














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FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART Ijose-silva-martinez/courses... · Fundamentals on ADCs: Part I Jose Silva-Martinez Efficient radio transceiver: Direct Conversion