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Full Design of an Electrochemical ImpedanceSpectroscopy Sensor
Erasmo J. D. Chiappetta Filho1, Luiz E. Bento Ribeiro2, F. Fruett21Instituto de Pesquisas Eldorado, Campinas - Brazil
2State University of Campinas (UNICAMP), Campinas - [email protected], [email protected], [email protected]
Abstract—This paper presents a full design of an electrochem-ical impedance spectroscopy (EIS) sensor for a wide range ofapplications. The sensor is composed of an integrated circuitfabricated in 0.35µm technology with a Detection Dynamic Rangehigher than 100dB, and an electrode microfabricated on glass andgold coated for wider applicability. The system was validatedinside a climatic chamber measuring the relative air humidityfrom 25Rh% to 85Rh%.
I. INTRODUCTION
The study of the electrical impedance of a system ora material as a function of frequency, called impedancespectroscopy, has proven to be a powerful analytical toolin many fields [1]. The analysis of materials and systemsproperties by applying alternating electric signals of differentfrequencies and measuring the corresponding electric outputsignals, allows important applications in medicine [2], biology[3], [4], food analysis [5], food engineering [6], geology[7], buildings [8] and electrochemistry [9]. ElectrochemicalImpedance Spectroscopy (EIS) is a suitable technique for in-vestigating many physical and chemical parameters in liquids,gases and solids like conductivity, dielectric constant, andinterfacial properties. Furthermore, EIS technique combinedwith microfluidics, micromachining and MEMS techniquescan be a very useful and valuable tool in biochips.
In this paper, an EIS integrated circuit was designed andtested. The sensor is composed of a 0.35µm technology in-tegrated circuit and a microfabricated Interdigitated Electrode(IDE) structure, which was fabricated using inert materials astitanium and gold over a glass substrate allowing better agingproperties and wider applicability. The system was charac-terized and its functionality was validated inside a climaticchamber through humidity measurement ranging from 25Rh%to 85Rh%.
The section II presents a detailed description of the sensordesign, where are discussed some important design issuesof the integrated circuit and the microfabricated electrodes.Section III summarizes the experimental results and finally,some conclusions are given in section IV.
II. SENSOR DESIGN
A. Circuit
An integrated circuit was designed to detect the impedanceof the microfabricated electrodes in the range of 0 to 50MHz.This circuit was proposed and used as a biosensor by [3].
It is basically composed of two main block types: a Tran-simpedance Amplifier (TIA) and a Gilbert Cell QuadratureMixer. A sinusoidal signal, Vx(ω), is applied to one terminalof the IDE as shown in Figure 1, while the other terminalis tied to the input of the TIA, which is used to convert thecurrent that flows through the electrodes in an output voltage.The electrode current is phase-shifted and modulated by theconductivity and permeability sensed by the electrodes, andthe same occurs with TIA’s output voltage, VTIA. Thereafter,the output modulated voltage is multiplied by two orthogonalsquare-wave and processed by a low-pass filter, in order toremove the high frequency harmonics generated in the mixingoperation. As a result, VQ(ω) and VI(ω) signals are obtained,which can be translated to phase and magnitude of the inputelectrode admittance by the following equations:
|Y (ω)| =√VQ(ω)2 + VI(ω)2
Atotal · |Vx(ω)|(1)
6 Y (ω) = tan−1(VI(ω)
VQ(ω)
)(2)
Where Y (ω) is the admittance of the electrode at ω fre-quency, Atotal is the system total gain and Vx is the electrodeinput signal. The design of each block is described as follows:
1) Transimpedance Amplifier: This block is a transducerthat converts its input current to an output voltage. In orderto improve the linearity of the conversion, it is necessary toimplement a low input impedance. To meet this requirementa common-gate stage connected to a gain boosting amplifieris used. The resultant input impedance can be approximatedto 1/(gm2 · Ab), where gm2 is the transconductance of thecommon-gate transistor and Ab is the gain of the gain boostingamplifier. The input impedance value, Zin(ω), is aimed to staybelow 100Ω for the whole frequency range (0 to 50MHz).This guarantees an readout error lower than 1% for a typicalelectrode impedance (≥ 10kΩ). Another important character-istic of the gain boosting operational amplifier is the ability toimpose a DC level over the electrodes. This is useful to controlfaradaic processes where DC bias over the sensed mean canresult in different measured values [3]. The DC level can beapplied by changing the operational amplifier input voltage(Vc pin).
Q
VQ+
_
Q
Q
I
VI+
_
I
I
RL1 RL2
M1
IxVx
VTIA VREF
M2
M3 M4
Vc
Quadrature MixersTIA TIA
Replica
IDE
structure
Ibias Ibias
Ibias Ibias
Fig. 1. EIS circuit.
2) Quadrature Mixers: This part of the system is respon-sible to down-convert its input signal to the baseband (DC to1kHz). To do this, I and Q inputs are switched with the samefrequency of the input signal, but orthogonally phase-shifted.
The total system gain will be given by
Atotal =gm3
gm1·Rout (3)
where gm1 is the transconductance of the diode connectedtransistor in TIA, gm3 is the mixer input transistors transcon-ductance and Rout is mixer output load resistors.
To make the system gain dependent on just the mixer outputresistors both gm2 and gm3 transconductances should match,so Atotal can be rewritten as:
Atotal ≈ Rout (4)
To guarantee a proper biasing for the M4 mixer inputtransistors a TIA replica is used, so the M4 gate voltage,VREF , will sits in the middle of the VTIA range.
3) System Considerations: For input currents between-38µA and 40µA, the simulation results show that the linearityof the system stays below 1dB of distortion (P1dB). To workinside a linear region, a safe input range can be definedbetween -25µA and +25µA.
To achieve a high Detection Dynamic Range (DDR), itis mandatory to keep the noise at very low levels. In thetopology chosen for the TIA the main sources of noise are thediode connected pFET and the current source nFET. The noisecontribution of these devices can be substantially reducedby raising its width/length dimensions to 6.3µm/3µm and50µm/6µm, respectively. The common-gate nFET and its gainboosting amplifier have negligible influence on the systemnoise once their voltage noise acts over the drain of a currentsink with relatively high input impedance, so the translationof operational amplifier output noise voltage to input currentis negligible [3].
In the mixer the main sources of noise are the currentsource and the input pFETs, which also can be reduced byraising its width and length, but keeping its DC and AC
characteristics within the specified range. The chosen valueswere, respectively, 100µm/2µm and 5.9µm/1.5µm. The I andQ transistors are negligible as noise contributors, and the mixerload was chosen to be a resistor, avoiding another source of1/f noise in the case of diode-connected nFETs are used.The simulated worst case noise referred to TIAs input currentachieved 140.8pA rms and 244.3pA rms for bandwidths of10Hz and 1kHz, respectively. This guarantees a DDR of108.5dB for a maximum input current of 25µA.
B. Electrode
The IDE design was based on studies conducted by RuiIgreja [10] and coworkers about interdigitated sensors. Param-eters such as spatial wavelength, metalization ratio, number offingers, length and width, define the area and the total IDEimpedance. The first step was to calculate and adjust theseparameters to obtain the desired impedance and to fit it intothe fabrication process limitations.
Fig. 2. Image of the six fabricated IDEs (upper-left corner) and the detailedmicrography of the electrode fingers.
A better understanding of the electrical properties of theelectrodes was reached by using a finite elements simulationsoftware (CST Computer Simulation Technology AG.). Withthis tool, six independent electrodes with 128 fingers each
were designed as shown in the detail of Figure 2. Thedimensions of each finger are as follows: width and spacingof 20µm (metalization ratio of 0.5) and length of 560µm. Thetotal IDE dimension is 5120µm by 560µm.
It is important to note that we need at least two independentelectrodes configuration to realize an EIS. For air conductivityand air permeability values, the simulation results reveal avery high resistance, bigger than 100MΩ, and a capacitanceof approximately 1.67pF for each pair of IDE. Furthermore,by using more electrodes in parallel or in series, differentimpedance values can be reached, raising even more theapplication range of the sensor.
The IDE fabrication started with the production of theelectrode masks using high resolution direct writing pho-tolithography with a laser beam. In the next step, a photoresistlayer was deposited onto a square optical glass plate (60mmside Kodak 1A High Resolution Glass) and patterned byconventional ultraviolet light (UV) photolithographic methodfollowing the electrodes masks. The UV exposures were car-ried out in a MJB-3 UV300 contact mask aligner (Karl-Suss,Garching, Germany). Titanium-gold-titanium (TiAuTi) thin-films, deposited with a Leybold Univex 300 ebeam evaporator(Cologne, Germany) using the lift-off technique, were usedas electrode materials. After thin-film depositions, the deviceswere immersed in acetone to remove the photoresist layer andexcess of metal, leaving the patterned electrodes on the glasssurface [11].
III. EXPERIMENTAL RESULTS
The integrated circuit was fabricated using 0.35µm CMOStechnology from Austria Micro Systems and consumes 280µAof DC current from a 3.3V supply. Figure 3 shows themicrography photo of the core circuit, which occupies an areaof approximately 95µm x 290µm. As a first measurementsetup, the chip was encapsulated in a C-SOP16 SMD packageand mounted over a printed circuit board where the electrodescould be easily attached.
Fig. 3. Micrography of the integrated circuit.
A. Circuit Characterization
To quantify the error imposed by the operational amplifieroffset, the pin Vc was swept and TIA input voltage wasmeasured. These measurements show that the offset voltageremains below 10mV for Vc ranging from 0.7V to 1.5Vand below 5mV if the range is limited to 0.9V and 1.4V.Due to mixers differential output, this offset is subsequently
−1.5
−1
−0.5
0
0.5
1
1.5
−40 −20 0 20 40
Dif
fere
nti
al O
utp
ut
[V]
Input Current [µA]
MeasurementIdeal
Calibrated
Fig. 4. Differential output voltage vs. input current.
canceled after having been processed, but can reduce themaximum current supplied/sinked by the TIA’s input once anoffset voltage at the input infers an offset current across theelectrodes.
The resistances of the output resistors were characterizedand the obtained average value was 23.544kΩ, which repre-sents an error of 5.44% of the designed value (24.9kΩ). Themismatch between the resistors from the same mixer is keptbetween 0.22% and 1.22% and imposes an offset voltage atthe mixer output that can be written as:
Voffset =Ibias
2(RL1 −RL2) (5)
Where for the resistance mismatch measured, this offsetremains between 2.1mV and 11.5mV at the mixers output.
Fig. 4 shows the linearity of the circuit by plotting the inputcurrent versus the differential output voltage. The solid linerepresents the ideal curve as it was given by Vout = Ix ·Rout,the dashed line represents the ideal curve with gain and offsetcalibrated and the points represent the measured samples.
The difference between the ideal and the calibrated curvesrelies mainly in two reasons: 1) offset created by the mismatchof transistors, and 2) gain error given by transconductancemismatch between the diode-connected transistor of the TIAand input transistors of the mixers. As the Vgs of thesetransistors sits on different voltage levels, it is a difficult taskto match their transconductance across all operating range. Inthe circuits measured the gain error remained between 10.5%and 11.5%.
After calibration the 1dB distortion points (P1dB) werelocated at -36.5µA and 45µA of input current, meaning thatthe safe range defined before, between -25µA and +25µA, stillvalid.
Another important characteristic of the circuit is its lowinput impedance, allowing the electrodes to be sensed withminimum distortion inside operating range. The measurementsshown that the input impedance remains lower than 100Ω forVc values below 1.3V.
B. Humidity MeasurementTo measure the humidity the circuit was placed inside a
Votsch VCL4010 climatic chamber, the quadrature and sinu-soidal signals were generated by two synchronized functionwave generators (Agilent 33220A) and the IQ outputs weremeasured by four Agilent 34401A multimeters. The wholesetup was controlled by Python scripting through RS-232, forthe climatic chamber, and GPIB, for the Agilent equipment.
0
1
2
3
4
5
6
7
8
0 1 2 3 4 5 6 7 8 9 10 11
ImY
(ω)
[µ
Ω−
1]
ReY(ω) [µΩ−1
]
10Hz
2.02MHz
630kHz
25 Rh%85 Rh%
Fig. 5. EIS of the electrodes for relative humidity of 25Rh% and 85Rh%.
Figure 5 shows the measurement results for the lowest andhighest values of measured relative humidity (25Rh% and85Rh%, respectively), at 27C. This EIS curve behavior canbe modeled by an RC circuit consisting of a resistor, Rs,in series with a resistor and a capacitor in parallel, Rair
and Cair, where Rs is composed of the electrodes wiringresistance, Rair is the resistance between the two electrodesand is proportional to air resistivity, and Cair is the electrodescapacitance, which is proportional to air permeability.
5.2
5.4
5.6
5.8
6
6.2
6.4
20 30 40 50 60 70 80 90 6.8
6.9
7
7.1
7.2
7.3
7.4
7.5
Re
Y(ω
) [
µΩ
−1]
ImY
(ω)
[µ
Ω−
1]
Relative Humidity [Rh%]
ReY(ω) at 630kHzImY(ω) at 630kHz
Fig. 6. ReY(ω) and ImY(ω) versus relative humidity for a 630kHz inputsignal.
The frequency was swept from 10Hz to 2.020MHz forevery value of relative humidity, and the frequency that shown
the best sensitivity is 630kHz, which is the highest value ofImY(ω) in all measurements. The ReY(ω) and ImY(ω)variation versus relative humidity for 630kHz is shown in Fig-ure 6, where the sensor relative humidity sensitivity achieved2.7nS/Rh%.
IV. CONCLUSION
The designed EIS sensor has proven to be suitable toaccurately measure the small variation of air resistivity andpermeability across the range from 25Rh% to 85Rh%. At thehigher frequencies a distortion in the EIS curve is noticeable,which is mainly due to the quality of the external generatedsignals and the low Power Supply Rejection Ratio (PSRR) ofthe circuit. It needs to be investigated on how to integrate thegeneration of the signals and how to improve the PSRR bymodifying the circuit topology. As a next step, the microfabri-cated electrodes and the chip attached to it could be integratedon the same glass substrate. This will reduce the influence ofparasitics and enhance the sensor readout even more.
ACKNOWLEDGMENT
The authors would like to thank to FAPESP for the devicefabrication, LNLS for the IDE fabrication and Instituto dePesquisas Eldorado for the well equipped laboratory wherethis whole work could be validated.
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