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7/31/2019 Full Adder Behav,Data, Stru
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HDL Based Design & Simulation Lab
Prachi parikh Page 1
EXPERIMENT:-3
ADDER CIRCUIT (HALF ADDER & FULL ADDER)
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EXPERIMENT:-3
AIM: - Adder Circuit (Half Adder & Full adder)
TOOLS USED: - Xilinx
ISE, Modelsim SE
VHDL CODE :-( Half Adder: ---Dataflow)
----------------------------------------------------------------------------------
-- Name: prachi V. parikh
-- Create Date: 14:08:08 09/20/2012
-- Design Name: dataflow
-- Module Name: hadder - dataflow
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadder is
Port (K: in STD_LOGIC;
L: in STD_LOGIC;
S: out STD_LOGIC;
C: out STD_LOGIC);
end hadder;
architecture dataflow of hadder is
beginC
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Synthesis Report:-
=====================================================================
* Final Report *
=====================================================================
Final ResultsRTL Top Level Output File Name : hadder.ngr
Top Level Output File Name : hadder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 4
Cell Usage:
# BELS : 2
# LUT2 : 2
# IO Buffers : 4
# IBUF : 2
# OBUF : 2
=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4
Number of Slices: 1 out of 1920 0%
Number of 4 input LUTs: 2 out of 3840 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 173 2%
Partition Resource Summary:
No Partitions were found in this design.
===================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:
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No asynchronous control signals found in this design
Timing Summary:
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.033ns
Timing Detail:
All values displayed in nanoseconds (ns)
=====================================================================
Timing constraint: Default path analysisTotal number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay: 9.033ns (Levels of Logic = 3)
Source: L (PAD)
Destination: C (PAD)
Data Path: L to C
Gate Net
Cell: in->out fanout Delay Delay Logical Name (Net Name)
----------------------------------------------------------------------------------------------
IBUF: I->O 2 0.821 1.216 L_IBUF (L_IBUF
LUT2:I0->O 1 0.551 0.801 C1 (C_OBUF)
OBUF: I->O 5.644 C_OBUF (C)
----------------------------------------------------------------------------------------------
Total 9.033ns (7.016ns logic, 2.017ns route)
(77.7% logic, 22.3% route)
=====================================================================
CPU: 8.69 / 10.31 s | Elapsed: 9.00 / 11.00 s
Total memory usage is 137624 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings: 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
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RTL Schematic:-
Technology Schematic:-
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Simulated Waveforms:-
VHDL CODE :-( Half Adder: ---Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadder is
Port (K: in STD_LOGIC;
L: in STD_LOGIC;S: out STD_LOGIC;
C: out STD_LOGIC);
end hadder;architecture Behavioral of hadder is
begin
P1: process (K, L)
beginif K='0' and L='0' then S
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Synthesis Report:-=====================================================================
* Final Report *=====================================================================
Final Results
RTL Top Level Output File Name : hadder.ngr
Top Level Output File Name : hadderOutput Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NODesign Statistics
# IOs : 4
Cell Usage:
# BELS : 2#LUT2 : 2
# IO Buffers : 4
# IBUF : 2
# OBUF : 2=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4
Number of Slices: 1 out of 1920 0%
Number of 4 input LUTs: 2 out of 3840 0%Number of IOs: 4
Number of bonded IOBs: 4 out of 173 2%
Partition Resource Summary:
No Partitions were found in this design.
=====================================================================TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this designAsynchronous Control Signals Information:
No asynchronous control signals found in this designTiming Summary:
Speed Grade: -4
Minimum period: No path foundMinimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
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Maximum combinational path delay: 9.033ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)=====================================================================
Timing constraint: Default path analysisTotal number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay: 9.033ns (Levels of Logic = 3)
Source: K (PAD)Destination: C (PAD)
Data Path: K to C
Gate Net
Cell: in->out fanout Delay Delay Logical Name (Net Name)--------------------------------------------------------------------------------------------
IBUF: I->O 2 0.821 1.216 K_IBUF (K_IBUF)
LUT2:I0->O 1 0.551 0.801 C1 (C_OBUF)OBUF: I->O 5.644 C_OBUF (C)--------------------------------------------------------------------------------------------
Total 9.033ns (7.016ns logic, 2.017ns route)
(77.7% logic, 22.3% route)
=====================================================================
CPU: 7.73 / 9.66 s | Elapsed: 8.00 / 10.00 s
Total memory usage is 137624 kilobytes
Number of errors : 0 ( 0 filtered)Number of warnings: 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL Schematic:-
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Technology Schematic:-
Simulated Waveforms:-
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VHDL CODE :-( Half Adder: ---structural)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadder is
Port (K: in STD_LOGIC;
L: in STD_LOGIC;
SUM: out STD_LOGIC;
CARRY: out STD_LOGIC);
end hadder;
architecture Structural of hadder is
component and71
Port (x: in STD_LOGIC;
y: in STD_LOGIC;
z: out STD_LOGIC);
end component;
component xor71
Port (x: in STD_LOGIC;
y: in STD_LOGIC;
z: out STD_LOGIC);
end component;
begin
D: and71 port map (K, L, CARRY);
E: xor71 port map (K, L, SUM);
end Structural;
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Synthesis Report:-=====================================================================
* Final Report *=====================================================================
Final Results
RTL Top Level Output File Name : hadder.ngr
Top Level Output File Name : hadderOutput Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NODesign Statistics
# IOs : 4
Cell Usage:
# BELS : 2# LUT2 : 2
# IO Buffers : 4
# IBUF : 2
# OBUF : 2=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4
Number of Slices: 1 out of 1920 0%Number of 4 input LUTs: 2 out of 3840 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 173 2%
Partition Resource Summary:
No Partitions were found in this design.=====================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this designAsynchronous Control Signals Information:
No asynchronous control signals found in this design
Timing Summary:
---------------Speed Grade: -4
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Minimum period: No path foundMinimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.033ns
Timing Detail:
All values displayed in nanoseconds (ns)=====================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2-------------------------------------------------------------------------
Delay: 9.033ns (Levels of Logic = 3)
Source: K (PAD)
Destination: CARRY (PAD)Data Path: K to CARRY
Gate Net
Cell: in->out fanout Delay Delay Logical Name (Net Name)-------------------------------------------------------------------------------------------IBUF: I->O 2 0.821 1.216 K_IBUF (K_IBUF)
LUT2:I0->O 1 0.551 0.801 D/z1 (CARRY_OBUF)
OBUF: I->O 5.644 CARRY_OBUF (CARRY)----------------------------------------------------------------------------------------
Total 9.033ns (7.016ns logic, 2.017ns route)
(77.7% logic, 22.3% route)====================================================================
CPU: 8.28 / 10.94 s | Elapsed: 8.00 / 11.00 s
Total memory usage is 137624 kilobytes
Number of errors : 0 ( 0 filtered)Number of warnings: 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL Schematic:-
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Technology Schematic:-
Simulated Waveforms:-
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VHDL CODE :-( Full Adder: ---Dataflow)
------------------------------------------------------------------------------------ Name: Prachi V. Parikh
-- Create Date: 23:17:12 09/21/2012
-- Design Name: dataflow-- Module Name: fadder - dataflow
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadder is
Port (K: in STD_LOGIC;
L: in STD_LOGIC;M: in STD_LOGIC;
N: inout STD_LOGIC;
SUM: out STD_LOGIC;CARRY: out STD_LOGIC);
end fadder;
architecture dataflow of fadder is
begin
N
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# LUT2 : 1# LUT3 : 2
# IO Buffers : 6
# IBUF : 3
# OBUF : 3=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4
Number of Slices: 2 out of 1920 0%Number of 4 input LUTs: 3 out of 3840 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 173 3%
Partition Resource Summary:
No Partitions were found in this design.
=====================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:No asynchronous control signals found in this design
Timing Summary:
---------------Speed Grade: -4
Minimum period: No path foundMinimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.063ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)=====================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 3Delay: 9.063ns (Levels of Logic = 3)
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Source: K (PAD)Destination: N (PAD)
Data Path: K to N
Gate Net
Cell: in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------------------------------------------------------------
IBUF: I->O 3 0.821 1.246 K_IBUF (K_IBUF)LUT2:I0->O 1 0.551 0.801 N1 (N_OBUF)OBUF: I->O 5.644 N_OBUF (N)
---------------------------------------------------------------------------------------------
Total 9.063ns (7.016ns logic, 2.047ns route)(77.4% logic, 22.6% route)
=====================================================================
CPU: 6.84 / 7.41 s | Elapsed: 7.00 / 8.00 s
Total memory usage is 136600 kilobytes
Number of errors : 0 ( 0 filtered)Number of warnings: 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)
RTL Schematic:-
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Technology Schematic:-
Simulated Waveforms:-
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VHDL CODE :-( Full Adder: ---Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadder is
Port (K: in STD_LOGIC;
L: in STD_LOGIC;
M: in STD_LOGIC;
SUM: out STD_LOGIC;
CARRY: out STD_LOGIC);
end fadder;
architecture Behavioral of fadder is
begin
p1: process (K, L, M)
begin
if K='0' and L='0' and M='0' then SUM
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SYNTHESIS REPORT:-=====================================================================
* Final Report *=====================================================================
Final Results
RTL Top Level Output File Name : fadder.ngr
Top Level Output File Name : fadderOutput Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NODesign Statistics
# IOs : 5
Cell Usage:
# BELS : 2# LUT3 : 2
# IO Buffers : 5
# IBUF : 3
# OBUF : 2=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4Number of Slices: 1 out of 1920 0%
Number of 4 input LUTs: 2 out of 3840 0%
Number of IOs: 5Number of bonded IOBs: 5 out of 173 2%
---------------------------
Partition Resource Summary:
No Partitions were found in this design.
=====================================================================TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
No clock signals found in this design
Asynchronous Control Signals Information:No asynchronous control signals found in this design
Timing Summary:---------------
Speed Grade: -4Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path foundMaximum combinational path delay: 9.033ns
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Timing Detail:All values displayed in nanoseconds (ns)
=====================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 2Delay: 9.033ns (Levels of Logic = 3)
Source: M (PAD)Destination: CARRY (PAD)Data Path: M to CARRY
Gate Net
Cell: in->out fanout Delay Delay Logical Name (Net Name)--------------------------------------------------------------------------------------------------------------
IBUF: I->O 2 0.821 1.216 M_IBUF (M_IBUF)
LUT3:I0->O 1 0.551 0.801 CARRY_mux00071 (CARRY_OBUF)
OBUF: I->O 5.644 CARRY_OBUF (CARRY)-------------------------------------------------------------------------------------------------------------
Total 9.033ns (7.016ns logic, 2.017ns route)
(77.7% logic, 22.3% route)=====================================================================CPU: 7.36 / 7.94 s | Elapsed: 7.00 / 8.00 s
Total memory usage is 137624 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings: 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)
RTL Schematic:-
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Technology Schematic:-
Simulated Waveforms:-
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VHDL CODE :-( Full Adder: ---Structural)
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadder is
Port (K: in STD_LOGIC;L: in STD_LOGIC;
M: in STD_LOGIC;
N: inout STD_LOGIC;
SUM: out STD_LOGIC;CARRY: out STD_LOGIC);
end fadder;
architecture structural of fadder iscomponent and71
Port (x: in STD_LOGIC;
y: in STD_LOGIC;z: out STD_LOGIC);
end component;
component xor71Port (x: in STD_LOGIC;
y: in STD_LOGIC;
z: out STD_LOGIC);
end component;
begin
D: xor71 port map (K, L, N);E: xor71 port map (N, M, SUM);
F: and71 port map (N, M, CARRY);
end structural;
SYNTHESIS REPORT:-=====================================================================
* Final Report *=====================================================================
Final Results
RTL Top Level Output File Name : fadder.ngrTop Level Output File Name : fadder
Output Format : NGC
Optimization Goal : SpeedKeep Hierarchy : NO
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Design Statistics# IOs : 6
Cell Usage:
# BELS : 3
# LUT2 : 1# LUT3 : 2
# IO Buffers : 6# IBUF : 3# OBUF : 3
=====================================================================
Device utilization summary:
Selected Device: 3s200ft256-4
Number of Slices: 2 out of 1920 0%
Number of 4 input LUTs: 3 out of 3840 0%Number of IOs: 6
Number of bonded IOBs: 6 out of 173 3%
---------------------------Partition Resource Summary:---------------------------
No Partitions were found in this design.
=====================================================================TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:No clock signals found in this design
Asynchronous Control Signals Information:No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path foundMaximum combinational path delay: 9.063ns
Timing Detail:--------------
All values displayed in nanoseconds (ns)
Timing constraint: Default path analysisTotal number of paths / destination ports: 8 / 3
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Delay: 9.063ns (Levels of Logic = 3)Source: K (PAD)
Destination: N (PAD)
Data Path: K to N
Gate NetCell: in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------IBUF: I->O 3 0.821 1.246 K_IBUF (K_IBUF)LUT2:I0->O 1 0.551 0.801 D/z1 (N_OBUF)
OBUF: I->O 5.644 N_OBUF (N)
----------------------------------------Total 9.063ns (7.016ns logic, 2.047ns route)
(77.4% logic, 22.6% route)
=====================================================================
CPU: 7.20 / 7.76 s | Elapsed: 7.00 / 7.00 s
Total memory usage is 137624 kilobytes
Number of errors : 0 ( 0 filtered)Number of warnings: 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)
RTL Schematic:-
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Technology Schematic:-
Simulated Waveforms:-
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Conclusion:-