FSQ311

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2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSQ0365,FSQ

0265,FSQ0165,FSQ321,F

SQ311

GreenModeFairchildPowerSwitch(FPS)

September 2007

FSQ0365, FSQ0265, FSQ0165, FSQ321, FSQ311Rev. 1.0.5

FPSTMis a trademark of Fairchild Semiconductor Corporation.

FSQ0365, FSQ0265, FSQ0165, FSQ321, FSQ311

Green Mode Fairchild Power Switch (FPS) forValley Switching Converter - Low EMI and High Efficiency

Features Optimized for Valley Switching (VSC)

Low EMI through Variable Frequency Control andInherent Frequency Modulation

High-Efficiency through Minimum Voltage Switching

Narrow Frequency Variation Range over Wide Loadand Input Voltage Variation

Advanced Burst-Mode Operation for Low StandbyPower Consumption

Pulse-by-Pulse Current Limit

Various Protection Functions: Overload Protection(OLP), Over-Voltage Protection (OVP), AbnormalOver-Current Protection (AOCP), Internal ThermalShutdown (TSD)

Under-Voltage Lockout (UVLO) with Hysteresis

Internal Start-up Circuit

Internal High-Voltage SenseFET (650V)

Built-in Soft-Start (15ms)

Applications

Power Supply for DVP Player and DVD Recorder,Set-Top Box

Adapter

Auxiliary Power Supply for PC, LCD TV, and PDP TV

Related Application Notes

AN-4137, AN-4141, AN-4147, AN-4150 (Flyback)

AN-4134 (Forward)

Description

A Valley Switching Converter generally shows lower EMI

and higher power conversion efficiency than a

conventional hard-switched converter with a fixed

switching frequency. The FSQ-series is an integrated

Pulse-Width Modulation (PWM) controller and

SenseFET specifically designed for valley switching

operation with minimal external components. The PWM

controller includes an integrated fixed-frequency

oscillator, Under-Voltage Lockout, Leading Edge

Blanking (LEB), optimized gate driver, internal soft-start,

temperature-compensated precise current sources for

loop compensation, and self-protection circuitry.

Compared with discrete MOSFET and PWM controller

solutions, the FSQ-series reduces total cost, component

count, size and weight; while simultaneously increasing

efficiency, productivity, and system reliability. This device

provides a basic platform that is well suited for cost-

effective designs of valley switching fly-back converters.

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FSQ0365, FSQ0265, FSQ0165, FSQ321, FSQ311 Rev. 1.0.5 2

Ordering Information

Notes:

1. The junction temperature can limit the maximum output power.

2. 230VACor 100/115VACwith doubler. The maximum power with CCM operation.

3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.

4. Maximum practical continuous power in an open-frame design at 50C ambient.

5. Pb-free package per JEDEC J-STD-020B.

Product

Number(5)PKG.

Operating

Temp.

Cur-

rent

Limit

RDS(ON)Max.

Maximum Output Power(1)

Replaces

Devices230VAC15%(2) 85-265VAC

Adapter(3) Open-Frame(4) Adapter(3) Open-Frame(4)

FSQ311 8-DIP-40 to +85C 0.6A 19 7W 10W 6W 8W

FSDL321

FSDM311FSQ311L 8-LSOP

FSQ321 8-DIP-40 to +85C 0.6A 19 8W 12W 7W 10W

FSDL321

FSDM311FSQ321L 8-LSOP

FSQ0165RN 8-DIP-40 to +85C 0.9A 10 10W 15W 9W 13W FSDL0165RN

FSQ0165RL 8-LSOP

FSQ0265RN 8-DIP-40 to +85C 1.2A 6 14W 20W 11W 16W

FSDM0265RN

FSDM0265RNBFSQ0265RL 8-LSOP

FSQ0365RN 8-DIP-40 to +85C 1.5A 4.5 17.5W 25W 13W 19W

FSDM0365RN

FSDM0365RNBFSQ0365RL 8-LSOP

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Typical Circuit

Figure 1. Typical Flyback Application

Internal Block Diagram

Figure 2. Functional Block Diagram

Vcc

GND

Drain

Sync

VO

PWM

Vfb

ACIN

Vstr

FSQ0365RN Rev.00

8V/12V

Vref

S

Q

Q

R

VCC Vref

Idelay IFB

VSD

Vovp

Sync

VOCPS

Q

Q

R

R

3R

VCCgood

Vcc Drain

Vfb

GND

AOCP

Gatedriver

VCCgood

LEB

200ns

PWM

VBurst

4

Sync

+

-

+

-0.7V/0.2V

2.5s timedelay

(1.1V)

Soft-

Start

6V

6V

0.35/0.55

+

-

OSC

Vstr

TSD

3

2 8765

FSQ0365RN Rev.00

1

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Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 GND SenseFET source terminal on primary side and internal control ground.

2 Vcc

Positive supply voltage input. Although connected to an auxiliary transformer winding, current

is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram

Section). It is not until VCCreaches the UVLO upper threshold (12V) that the internal start-up

switch opens and device power is supplied via the auxiliary transformer winding.

3 Vfb

The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA

current source connected internally while a capacitor and optocoupler are typically connected

externally. There is a time delay while charging external capacitor Cfb from 3V to 6V using an

internal 5A current source. This time delay prevents false triggering under transient condi-

tions but still allows the protection mechanism to operate under true overload conditions.

4 Sync

This pin is internally connected to the sync-detect comparator for valley switching. Typically the

voltage of the auxiliary winding is used as Sync input voltage and external resistors and capac-

itor are needed to make time delay to match valley point. The threshold of the internal sync

comparator is 0.7V/0.2V.

5 Vstr

This pin is connected to the rectified AC line voltage source. At start-up the internal switch sup-

plies internal bias and charges an external storage capacitor placed between the Vcc pin and

ground. Once the Vcc reaches 12V, the internal switch is opened.

6,7,8 Drain

The drain pins are designed to connect directly to the primary lead of the transformer and are

capable of switching a maximum of 700V. Minimizing the length of the trace connecting these

pins to the transformer will decrease leakage inductance.

GND

Vcc

Sync Vstr

8-DIP

Vfb

D

D

D

FSQ0365RN Rev.01

8-LSOPV

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Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only. TA= 25C, unless otherwise specified.

Notes:

6. Repetitive rating: Pulse width limited by maximum junction temperature.7. L=51mH, starting TJ=25C.

8. Meets JEDEC standards JESD22-A114 and JESD22-A115.

Thermal Impedance

Notes:

9. All items are tested with the standards JESD 51-2 and 51-10 (DIP).10. Free-standing, with no heat-sink, under natural convection.

11. Infinite cooling condition - refer to the SEMI G30-88.

12. Measured on the package top surface.

Symbol Characteristic Min. Max. Unit

VSTR VstrPin Voltage 500 V

VDS Drain Pin Voltage 650 V

VCC Supply Voltage 20 V

VFB Feedback Voltage Range -0.3 9.0 V

VSync Sync Pin Voltage Range -0.3 9.0 V

IDM Drain Current Pulsed(6)

FSQ0365 12

AFSQ0265 8

FSQ0165 4

FSQ321/311 1.5

EAS Single Pulsed Avalanche Energy(7)

FSQ0365 230

mJFSQ0265 140

FSQ0165 50

FSQ321/311 10

PD Total Power Dissipation 1.5 W

TJ Recommended Operating Junction Temperature -40 Internally limited C

TA Operating Ambient Temperature -40 85 C

TSTG Storage Temperature -55 150 C

ESDHuman Body Model(8) CLASS1 C

Machine Model(8) CLASS B

Symbol Parameter Value Unit

8-DIP(9)

JA(10) Junction-to-Ambient Thermal Resistance 80

C/WJC(11) Junction-to-Case Thermal Resistance 20

JT(12) Junction-to-Top Thermal Resistance 35

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Electrical Characteristics

TA= 25C unless otherwise specified.

Symbol Parameter Condition Min. Typ. Max. Unit

SenseFET Section

BVDSS Drain Source Breakdown Voltage VCC= 0V, ID= 100A 650 V

IDSS Zero-Gate-Voltage Drain Current VDS= 560V 100 A

RDS(ON)Drain-Source On-State

Resistance(13)

FSQ0365

TJ= 25C, ID= 0.5A

3.5 4.5

FSQ0265 5.0 6.0

FSQ0165 8.0 10.0

FSQ321/311 14.0 19.0

CSS Input Capacitance

FSQ0365

VGS= 0V, VDS= 25V, f = 1MHz

315

pFFSQ0265 550

FSQ0165 250

FSQ321/311 162

COSS Output Capacitance

FSQ0365


47

pF

FSQ0265 38

FSQ0165 25

FSQ321/311 18

CRSSReverse Transfer

Capacitance

FSQ0365


9.0

pFFSQ0265 17.0

FSQ0165 10.0

FSQ321/311 3.8

td(on) Turn-On Delay Time

FSQ0365

VDD= 350V, ID= 25mA

11.2

nsFSQ0265 20.0

FSQ0165 12.0

FSQ321/311 9.5

tr Rise Time

FSQ0365

VDD= 350V, ID= 25mA

34

nsFSQ0265 15

FSQ0165 4

FSQ321/311 19

td(off) Turn-Off Delay Time

FSQ0365

VDD= 350V, ID= 25mA

28.2

nsFSQ0265 55.0

FSQ0165 30.0

FSQ321/311 33.0

tf Fall Time

FSQ0365

VDD= 350V, ID= 25mA

32

nsFSQ0265 25

FSQ0165 10

FSQ321/311 42

Control Section

tON.MAX1 Maximum On Time1 All but Q321 TJ= 25C 10.5 12.0 13.5 s

tON.MAX2 Maximum On Time2 Q321 TJ= 25C 6.35 7.06 7.77 s

tB1 Blanking Time1 All but Q321 13.2 15.0 16.8 s

tB2 Blanking Time2 Q321 7.5 8.2 s

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Electrical Characteristics (Continued)

TA= 25C unless otherwise specified.

Notes:

13. Pulse test: Pulse-Width=300s, duty=2%

14. Though guaranteed, it is not 100% tested in production.

15. Propagation delay in the control IC.

16. Includes gate turn-on time.

Symbol Parameter Condition Min. Typ. Max. Unit

tW Detection Time Window TJ= 25C, Vsync= 0V 3.0 s

fS1 Initial Switching Freq.1 All but Q321 50.5 55.6 61.7 kHz

fS2 Initial Switching Freq.2 Q321 84.0 89.3 95.2 kHz

fS Switching Frequency Variation(14) -25C < TJ< 85C 5 10 %

IFB Feedback Source Current VFB= 0V 700 900 1100 A

DMIN Minimum Duty Cycle VFB= 0V 0 %

VSTARTUVLO Threshold Voltage After turn-on

11 12 13 V

VSTOP 7 8 9 V

tS/S1 Internal Soft-Start Time1 All but Q321 With free-running frequency 15 ms

tS/S2 Internal Soft-Start Time2 Q321 With free-running frequency 10 ms

Burst Mode Section

VBURH

Burst-Mode Voltage TJ= 25C, tPD= 200ns(15)

0.45 0.55 0.65 V

VBURL 0.25 0.35 0.45 V

VBUR(HYS) 200 mV

Protection Section

ILIM Peak Current Limit

FSQ0365 TJ= 25C, di/dt = 240mA/s 1.32 1.50 1.68

A

FSQ0265 TJ= 25C, di/dt = 200mA/s 1.06 1.20 1.34

FSQ0165 TJ= 25C, di/dt = 175mA/s 0.8 0.9 1.0

FSQ321 TJ= 25C, di/dt = 125mA/s 0.53 0.60 0.67

FSQ311 TJ= 25C, di/dt = 112mA/s 0.53 0.60 0.67

VSD Shutdown Feedback Voltage VCC= 15V 5.5 6.0 6.5 V

IDELAY Shutdown Delay Current VFB= 5V 4 5 6 A

tLEB Leading-Edge Blanking Time(14) 200 ns

VOVP Over-Voltage Protection VCC= 15V, VFB= 2V 5.5 6.0 6.5 V

tOVP Over-Voltage Protection Blanking Time 2 3 4 s

TSD Thermal Shutdown Temperature(14) 125 140 155 C

Sync Section

VSHSync Threshold Voltage

0.55 0.70 0.85 V

VSL 0.14 0.20 0.26 V

tSync Sync Delay Time(14)(16) 300 ns

Total Device Section

IOP Oper. Supply Current (Control Part Only) VCC= 15V 1 3 5 mA

ISTART Start CurrentVCC= VSTART- 0.1V

(before VCCreaches VSTART)270 360 450 A

ICH Start-up Charging Current VCC= 0V, VSTR= min. 40V 0.65 0.85 1.00 mA

VSTR Minimum VSTRSupply Voltage 26 V

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Comparison Between FSDM0x65RNB and FSQ-Series

Function FSDM0x65RNB FSQ-Series FSQ-Series Advantages

Operation methodConstant frequency

PWM

Valley switching

operation

Improved efficiency by valley switching

Reduced EMI noise

EMI reductionFrequency

modulation

Valley switching &inherent frequency

modulation

Reduce EMI noise by two ways

Burst-mode operation Fixed burst peak Advanced burst-mode

Improved standby power by valley switch-ing also in burst-mode

Because the current peak during burstoperation is dependent on VFB, it is easierto solve audible noise

Protection AOCP Improved reliability through precise abnor-

mal over-current protection

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Typical Performance Characteristics

These characteristic graphs are normalized at TA= 25C.

Figure 4. Operating Supply Current (IOP) vs. TA Figure 5. UVLO Start Threshold Voltage (VSTART)

vs. TA

Figure 6. UVLO Stop Threshold Voltage (VSTOP)

vs. TA

Figure 7. Start-up Charging Current (ICH) vs. TA

Figure 8. Initial Switching Frequency (fS) vs. TA Figure 9. Maximum On Time (tON.MAX) vs. TA

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 125

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]-25 0 25 50 75 100 125

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Norm

alized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Norm

alized

Temperature [C]

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Typical Performance Characteristics (Continued)These characteristic graphs are normalized at TA= 25C.

Figure 10. Blanking Time (tB) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA

Figure 12. Shutdown Delay Current (IDELAY) vs. TA Figure 13. Burst-Mode High Threshold Voltage

(Vburh) vs. TA

Figure 14. Burst-Mode Low Threshold Voltage

(Vburl) vs. TA

Figure 15. Peak Current Limit (ILIM) vs. TA

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

N

ormalized

Temperature [C]

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Typical Performance Characteristics (Continued)These characteristic graphs are normalized at TA= 25C.

Figure 16. Sync High Threshold Voltage (VSH) vs. TA Figure 17. Sync Low Threshold Voltage (VSL) vs. TA

Figure 18. Shutdown Feedback Voltage (VSD) vs. TA Figure 19. Over-Voltage Protection (VOP) vs. TA

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

-25 0 25 50 75 100 1250.0

0.2

0.4

0.6

0.8

1.0

1.2

Normalized

Temperature [C]

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Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the

external capacitor (Ca) connected to the Vcc pin, as

illustrated in Figure 20. When VCCreaches 12V, the FPS

begins switching and the internal high-voltage current

source is disabled. The FPS continues its normalswitching operation and the power is supplied from the

auxiliary transformer winding unless VCCgoes below the

stop voltage of 8V.

Figure 20. Start-up Circuit

2. Feedback Control: FPS employs current mode

control, as shown in Figure 21. An opto-coupler (such as

the FOD817A) and shunt regulator (such as the KA431)are typically used to implement the feedback network.

Comparing the feedback voltage with the voltage across

the RSENSE resistor makes it possible to control the

switching duty cycle. When the reference pin voltage of

the shunt regulator exceeds the internal reference

voltage of 2.5V, the opto-coupler LED current increases,

thus pulling down the feedback voltage and reducing the

duty cycle. This event typically happens when the input

voltage is increased or the output load is decreased.

2.1 Pulse-by-Pulse Current Limit: Because current

mode control is employed, the peak current through the

SenseFET is limited by the inverting input of PWM

comparator (VFB*), as shown in Figure 21. Assuming

that the 0.9mA current source flows only through the

internal resistor (3R + R = 2.8k), the cathode voltage of

diode D2 is about 2.5V. Since D1 is blocked when the

feedback voltage (VFB) exceeds 2.5V, the maximum

voltage of the cathode of D2 is clamped at this voltage,

thus clamping VFB*. Therefore, the peak value of the

current through the SenseFET is limited.

2.2 Leading Edge Blanking (LEB):At the instant the

internal SenseFET is turned on, a high-current spike

usually occurs through the SenseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the Rsenseresistor would lead to incorrect feedback operation in the

current mode PWM control. To counter this effect, the

FPS employs a leading edge blanking (LEB) circuit. Thiscircuit inhibits the PWM comparator for a short time

(tLEB) after the SenseFET is turned on.

Figure 21. Pulse-Width-Modulation (PWM) Circuit

3. Synchronization:The FSQ-series employs a valley

switching technique to minimize the switching noise and

loss. The basic waveforms of the valley switching

converter are shown in Figure 22. To minimize the

MOSFET's switching loss, the MOSFET should be

turned on when the drain voltage reaches its minimum

value, as shown in Figure 22. The minimum drain

voltage is indirectly detected by monitoring the VCC

winding voltage, as shown in Figure 22.

Figure 22. Valley Resonant Switching Waveforms

8V/12V

Vref

Internal

Bias

VCC Vstr

ICH

VCC

good

VDC

Ca

FSQ0365RN Rev.00

2 5

3 OSC

VCC

Vref

Idelay I

FB

VSD

R

3R

Gate

driver

OLP

D1 D2

+

VFB*

-

VFB

KA431

CB

VO

FOD817A

Rsense

SenseFET

FSQ0365RN Rev. 00

VDC

VRO

VRO

Vds

tF

0.7V

Vsync

300ns Delay

0.2V

ONON

Vovp

(6V)

FSQ0365RN Rev.00

MOSFET Gate

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4. Protection Circuits: The FSQ-series has several

self-protective functions, such as Overload Protection

(OLP), Abnormal Over-Current protection (AOCP), Over-

Voltage Protection (OVP), and Thermal Shutdown

(TSD). All the protections are implemented as auto-

restart mode. Once the fault condition is detected,

switching is terminated and the SenseFET remains off.

This causes VCC to fall. When VCC falls down to theUnder-Voltage Lockout (UVLO) stop voltage of 8V, the

protection is reset and start-up circuit charges VCCcapacitor. When the VCC reaches the start voltage of

12V, the FSQ-series resumes normal operation. If the

fault condition is not removed, the SenseFET remains off

and VCCdrops to stop voltage again. In this manner, the

auto-restart can alternately enable and disable the

switching of the power SenseFET until the fault condition

is eliminated. Because these protection circuits are fully

integrated into the IC without external components, the

reliability is improved without increasing cost.

Figure 23. Auto Restart Protection Waveforms

4.1 Overload Protection (OLP):Overload is defined as

the load current exceeding its normal level due to an

unexpected abnormal event. In this situation, the

protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in the normal

operation, the overload protection circuit can be

triggered during the load transition. To avoid this

undesired operation, the overload protection circuit is

designed to trigger only after a specified time to

determine whether it is a transient situation or a true

overload situation. Because of the pulse-by-pulse

current limit capability, the maximum peak current

through the Sense FET is limited, and therefore the

maximum input power is restricted with a given input

voltage. If the output consumes more than this maximum

power, the output voltage (VO) decreases below the set

voltage. This reduces the current through the opto-

coupler LED, which also reduces the opto-coupler

transistor current, thus increasing the feedback voltage

(VFB). If VFB exceeds 2.8V, D1 is blocked and the 5A

current source starts to charge CB slowly up to VCC. In

this condition, VFBcontinues increasing until it reaches

6V, when the switching operation is terminated, as

shown in Figure 24. The delay time for shutdown is the

time required to charge CB from 2.8V to 6V with 5A. A

20 ~ 50ms delay time is typical for most applications.

Figure 24. Overload Protection

4.2 Abnormal Over-Current Protection (AOCP):When

the secondary rectifier diodes or the transformer pins are

shorted, a steep current with extremely high-di/dt can

flow through the SenseFET during the LEB time. Even

though the FSQ-series has OLP (Overload Protection), it

is not enough to protect the FSQ-series in that abnormal

case, since severe current stress is imposed on the

SenseFET until OLP triggers. The FSQ-series has an

internal AOCP (Abnormal Over-Current Protection)

circuit as shown in Figure 25. When the gate turn-on

signal is applied to the power SenseFET, the AOCP

block is enabled and monitors the current through the

sensing resistor. The voltage across the resistor is

compared with a preset AOCP level. If the sensing

resistor voltage is greater than the AOCP level, the set

signal is applied to the latch, resulting in the shutdown of

the SMPS.

Figure 25. Abnormal Over-Current Protection

Fault

situation

8V

12V

VCC

VDS

t

Fault

occurs Faultremoved

Normal

operation

Normal

operation

Power

on

FSQ0365RN Rev. 00

VFB

t

2.8V

6.0V

Overload protection

t12

= CFB

*(6.0-2.8)/Idelay

t1

t2

FSQ0365RN Rev.00

1

S

Q

Q

R

OSC

R

3R

GND

Gatedriver

LEB200ns

PWM

+

-V

OCP

AOCP

Rsense

FSQ0365RN Rev.00

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4.3 Over-Voltage Protection (OVP): If the secondary

side feedback circuit malfunctions or a solder defect

causes an opening in the feedback path, the current

through the opto-coupler transistor becomes almost

zero. Then, VFB climbs up in a similar manner to the

overload situation, forcing the preset maximum current

to be supplied to the SMPS until the overload protection

triggers. Because more energy than required is providedto the output, the output voltage may exceed the rated

voltage before the overload protection triggers, resulting

in the breakdown of the devices in the secondary side.

To prevent this situation, an OVP circuit is employed. In

general, the peak voltage of the sync signal is

proportional to the output voltage and the FSQ-series

uses a sync signal instead of directly monitoring the

output voltage. If the sync signal exceeds 6V, an OVP is

triggered, shutting down the SMPS. To avoid undesired

triggering of OVP during normal operation, the peak

voltage of the sync signal should be designed below 6V.

4.4 Thermal Shutdown (TSD):The SenseFET and thecontrol IC are built in one package. This makes it easy

for the control IC to detect the abnormal over

temperature of the SenseFET. If the temperature

exceeds ~150C, the thermal shutdown triggers.

5. Soft-Start:The FPS has an internal soft-start circuit

that increases PWM comparator inverting input voltage

with the SenseFET current slowly after it starts up. The

typical soft-start time is 15ms, The pulse width to the

power switching device is progressively increased to

establish the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention ofsmoothly establishing the required output voltage. This

mode helps prevent transformer saturation and reduces

stress on the secondary diode during startup.

6. Burst Operation: To minimize power dissipation in

standby mode, the FPS enters burst-mode operation. As

the load decreases, the feedback voltage decreases. As

shown in Figure 26, the device automatically enters

burst-mode when the feedback voltage drops below

VBURL (350mV). At this point, switching stops and the

output voltages start to drop at a rate dependent on

standby current load. This causes the feedback voltage

to rise. Once it passes VBURH (550mV), switching

resumes. The feedback voltage then falls and the

process repeats. Burst-mode operation alternately

enables and disables switching of the power SenseFET,

thereby reducing switching loss in standby mode.

Figure 26. Waveforms of Burst Operation

7. Switching Frequency Limit: To minimize switching

loss and EMI (Electromagnetic Interference), the

MOSFET turns on when the drain voltage reaches its

minimum value in valley switching operation. However,

this causes switching frequency to increases at light load

conditions. As the load decreases, the peak drain current

diminishes and the switching frequency increases. This

results in severe switching losses at light-load condition,as well as intermittent switching and audible noise.

Because of these problems, the valley switching

converter topology has limitations in a wide range of

applications.

To overcome this problem, FSQ-series employs a

frequency-limit function, as shown in Figures 27 and 28.

Once the SenseFET is turned on, the next turn-on is

prohibited during the blanking time (tB). After the

blanking time, the controller finds the valley within the

detection time window (tW) and turns on the MOSFET, as

shown in Figures 27 and 28 (Cases A, B, and C). If no

valley is found during tW, the internal SenseFET is forced

to turn on at the end of tW (Case D). Therefore, ourdevices have a minimum switching frequency of 55kHz

and a maximum switching frequency of 67kHz, as shown

in Figure 28.

VFB

VDS

0.35V

0.55V

IDS

VO

VO

set

timeSwitchingdisabled

t1 t2 t3

Switchingdisabled t4

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Figure 27. Valley Switching with Limited Frequency

Figure 28. Switching Frequency Range

tsmax=18s

tsmax=18s

tB=15s

ts

tB=15s

ts

ts

IDSIDS

IDSIDS

A

B

C

DtW

=3s

tB=15s

tB=15s

IDS

IDS

IDS

IDS

FSQ0365RN Rev. 00

55kHz

67kHz

59kHz

Burst

mode

Constantfrequency

D

CBA

PO

When the resonant period is 2s

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Typical Application Circuit of FSQ0365RN

Features

High efficiency ( >77% at universal input)

Low standby mode power consumption (

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2. Transformer

Figure 30. Transformer Schematic Diagram of FSQ0365RN

3. Winding Specification

4. Electrical Characteristics

5. Core & Bobbin

Core: EER2828 (Ae=86.66mm2)

Bobbin: EER2828

No Pin (sf) Wire Turns Winding Method

Np/2 3 2 0.25 1 50 Center Solenoid Winding

Insulation: Polyester Tape t = 0.050mm, 2 Layers

N3.4V 9 8 0.33 2 4 Center Solenoid Winding


N5V 6 9 0.33 1 2 Center Solenoid Winding


Na 4 5 0.25 1 16 Center Solenoid Winding






Np/2 2 1 0.25 1 50 Center Solenoid Winding


Pin Specification Remarks

Inductance 1 - 3 1.4mH 10% 100kHz, 1V

Leakage 1 - 3 25H Max. Short all other pins

EER2828

N12V

1

6

7

8

9

10

11

12

N16V

N5.1V

N3.4V

Np/2

Na

2

3

4

5

Np/2

N16V

N12V

Na

N5.1V

N3.4V

Np/2

Np/2

6mm 3mm

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6. Demo Board Part List

Part Value Note Part Value Note

Resistor Inductor

R102 56k 1W L201 10H

R103 5 1/2W L202 10H

R104 12k 1/4W L203 4.9H

R105 100k 1/4W L204 4.9H

R106 6.2k 1/4W Diode

R107 6.2k 1/4W D101 IN4007

R108 62 1W D102 IN4004

R201 510 1/4W ZD101 1N4746A

R202 1k 1/4W D103 1N4148

R203 6.2k 1/4W D201 UF4003

R204 20k 1/4W D202 UF4003

R205 6k 1/4W D203 SB360

Capacitor D204 SB360

C101 100nF/275VAC Box Capacitor

C102 100nF/275VAC Box Capacitor IC

C103 33F/400V Electrolytic Capacitor IC101 FSQ0365RN FPS

C104 10nF/630V Film Capacitor IC201 KA431 (TL431) Voltage reference

C105 47nF/50V Mono Capacitor IC202 FOD817A Opto-coupler

C106 100nF/50V SMD (1206) Fuse

C107 22F/50V Electrolytic Capacitor Fuse 2A/250V

C110 33pF/50V Ceramic Capacitor NTC

C201 470F/35V Electrolytic Capacitor RT101 5D-9C202 470F/35V Electrolytic Capacitor Bridge Diode

C203 470F/35V Electrolytic Capacitor BD101 2KBP06M2N257 Bridge Diode

C204 470F/35V Electrolytic Capacitor Line Filter

C205 1000F/10V Electrolytic Capacitor LF101 40mH

C206 1000F/10V Electrolytic Capacitor Transformer

C207 1000F/10V Electrolytic Capacitor T101

C208 1000F/10V Electrolytic Capacitor Varistor

C209 100nF /50V Ceramic Capacitor TNR 10D471K

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Typical Application Circuit of FSQ311

Features

High efficiency ( >70% at universal input)

Low standby mode power consumption (

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2. Transformer

Figure 32. Transformer Schematic Diagram of FSQ311

3. Winding Specification

4. Electrical Characteristics

5. Core & Bobbin

Core: EE1927 (Ae=23.4mm2)

Bobbin: EE1927

No Pin (sf) Wire Turns Winding Method

Np/2 3 2 0.2 1 111 Solenoid Winding, 2 Layers


Shield 1 open 0.1 2 Shield winding

Insulation: Polyester Tape t = 0.025mm, 1 Layer



N3.3V 9 8 0.2 3 10 Center Solenoid Winding


N12V 10 11 0.1 1 30 Solenoid Winding

N-12V 11 12 0.1 3 33 Solenoid Winding


Shield 1 open 0.1 2 Shield winding


NVCCV 5 6 0.1 1 36 Center Solenoid Winding


Np/2 2 1 0.2 1 111 Solenoid Winding, 2 Layers


Pin Specification RemarksInductance 1 - 3 2.1mH 10% 66kHz, 1V

Leakage 1 - 3 100H Max. Short all other pins

EE1927

1Np/2

NVCC

2

3

5

6

Np/2

N5V

N3.3V

N12V

N-12V12

11

10

9

8

7

3

2

11 1012 11

6 5

2

1

Bottom of bobbin

`

3mm 3mm

Shield winding(0.1~0.15)

Lp/2(0.2)

N5V(0.2,3parallel)

N3.3V(0.2,3parallel)

N12V & N-12V(0.1~0.15)

NVcc(0.1~0.15)

Lp/2(0.2)

TAPE 1T

TAPE 2T

TAPE 1T

TAPE 1T

TAPE 1T

TAPE 2T

TAPE 2T

TAPE 4T

8 8 8 7 7 7

8 8 8 9 9 9

11

11

TAPE 2TShield winding

(0.1~0.15)

TAPE 1T

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6. Demo Board Part List

Part Value Note Part Value Note

Resistor Inductor

R2 100k 1/4W L2 660H

ZR1 1.2k 1/4W L1 4.7H

R4 5 1/2W L3 4.7H

R5 12k 1/4W L5 4.7H

R7 6.2k 1/4W L6 4.7H

R11 6.2k 1/4W Diode

RS5 150k 2W D2,3,4,5 IN4007

RS6 200 1W D8 IN4004

R6 510 1/4W D10 1N4148

R8 1k 1/4W ZD1 1N4746A

R12 8k 1/4W DS1 1N4007

R10 6.2k 1/4W, 1% D1 UF4003

R13 6k 1/4W, 1% D4 UF4003

Capacitor D7 SB360

C6 10F/400V Electrolytic D9 SB360

C7 10F/400V Electrolytic IC

C17 47nF/50V Ceramic U1 FSQ311 FPS

C104 100nF/50V SMD(1206) U2 KA431 (TL431) Voltage reference

C14 22F/50V Electrolytic U3 FOD817A Opto-coupler

C18 33pF/50V Ceramic Fuse

CS5 6.8nF/680V Film Fuse 2A/250V

C2 100F/35V Electrolytic NTCC3 100F/35V Electrolytic RT1 5D-9

C4 100F/35V Electrolytic Transformer

C5 100F/35V Electrolytic T1 EE1927 Bridge Diode

C11 680F/10V Electrolytic Ferrite bead

C12 680F/10V Electrolytic FB1

C15 680F/10V Electrolytic

C16 680F/10V Electrolytic

C19 68nF/50V Ceramic

C1 4.7nF/375VAC Ceramic

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Package Dimensions

Figure 33. 8-Lead, Dual In-Line Package(DIP)

5.08 MAX

0.33 MIN

2.54

7.62

0.56

0.3551.651.27

3.6833.20

3.603.00

6.676.096

9.839.00

7.62

9.9577.87

0.3560.20

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PERASME Y14.5M-1994

8.2557.61

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

(0.56)

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Package Dimensions (Continued)

Figure 34. 8-Lead, LSOP Package

MKT-MLSOP08ArevA

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GreenModeFairc

hildPowerSwitch(FPS)

Documents

FSQ311