From Digital to Analogue and Forth

8/6/2019 From Digital to Analogue and Forth

1/68

J. Belleman - CERNFrom analog to digital CAS, June 2007

1

From analog to digital

and back again...

DSP

Digital Signal Processor

ADC

Analog to Digital Converter

DAC

Digital to Analog Converter

amplifier

Power

Physical system

(Chariot with inverted pendulum)

Analog

regulator


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2 What does an ADC do?

An ADC converts a continuously variable signal, a voltageor a current, into a sequence of numbers, represented bylogic levels on a group of wires.

Analog to Digital Converter

Ain

D0

D1

D2

D3

ADC


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3

Quantization replaces a range ofcontinuous values by a set of discreteones.

Usually the number of levels is a powerof 2.

The difference between the original signaland the discrete representation is thequantization error

q(x)

x

Am

plitude quantization


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4 Amplitude quantization

Original signal

Error

A

A

Quantized (n bits)

2A2n

q

Power in original signal:

Quantized to n bits, one quantum is:

Maximum quantization error:

q

2

A2n with p 1

q

Power in quantization error:

PsA

2

T0

T

sin2 t dt

A2

2

P q 2

q 2

p2 dA

222 n

3

Thus SNRP

s

P1.522 n

In dB:

q2 A

2

nA2n1

10log10Ps

P 1.766.02 n


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5 Time quantization or sampling

u(t)

w(t)

g(t) = u(t)w(t)

Ts

Multiplication of the signal by a train of

impulses w(t) with period Ts (= 1/Fs):g tu tw t

g tu t

n

tnTs

Fourier transform ofw(t):

W f

w t ej 2 f t dt

W f n

ej 2 n f Ts12

n1

cos2 n f Ts n

fn

Ts

fTs

2

1.5

1

0.5

0

0.5

1

1.5

2

0.5 0 0.5 1 1.5

g t n

u nTstnTs


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6 Time quantization or sampling

W( f )

U( f )

G( f )

0 f

Fs

The spectrum of the sampled signalis the convolution ofU(f) and W(f)

G fU fW f

UW f d

G f n

U fn

Ts

After sampling, the signal spectrum

repeats for all multiples ofFs

G f

U n

fn

Ts d

G f n

U fn

Ts

d


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7 Nyquist

If the sampling rate Fs is less than twice the signal bandwidth, the spectralimages overlap. The avoid this, the following condition must be fulfilled:

This is the Nyquist criterion

One way this condition can be fulfilled is by filtering the analogue signalprior to digitizing it, using what is called an anti-aliasing filter. Since brick-wall filters cannot be made, the sampling rate should usually be quite a bitgreater than twice the signal bandwidth.

F(f)

G(f)

0 f

H(f)

Fs

Fs2BW


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8

Each of the images in the spectrum of the sampled signal contains all

the information needed to reconstruct the original. They are aliases.

We might reconstruct the original signal with a filter that rejectseverything except the original frequency band. After filtering, the

spectrum is exactly that of the original signal, in other words, noinformation is lost. We have recovered the original signal exactly.

This is Shannon's theorem

Reconstruction of the original signal

U (f)

G(f)

0 f

H(f)

r


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9 Reconstruction of the original signal

Filter the baseband using a rectangular filterH(f). The filter time-

domain response is the inverse Fourier transform of its frequency-domain shape:

h t1 H f

H fej2 f t df

Fs 2

Fs 2

ej2 f t

dfFs

sin Fs t

Fs t

urt n

u nTsFssin Fs tnTs

Fs tnTs

urtg th t

urt

n

u nTsh t d

urt n

u nTsh tnTs

Convolution of filter with sample stream:

2 20

1


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10 Frequency conversion & sub-sampling

w(t)

g(t) = u(t)w(t)u(t)

Ts

W( f )

U( f )

G( f )

0 f

0

0

Note that exactly the same spectrum

results for any signal frequency band

displaced by mFs(for integer m)

This goes by the name ofsub-sampling

G f

U mFs

W f d

G f n

U fn

Ts

mFs

G f n

U fmn

Ts

G f n

U f

n

Ts


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11

U (f)

G(f)

0 f

H(f)

Fs

r

Frequency conversion & sub-sampling

We could also choose a different spectral image to (re)construct the signal:

First work out the time-domainrepresentation of the filter:

H f1 for Fsf 32Fs

H f0 everywhere else

h t 1 H f

H fej2 f td

h t

32

Fs

3

2Fs

ej2 f t

df

Fs

Fs

ej2 f t

df

h t3 Fs sinc 3 t Fs2 Fs sinc 2 t Fs

1

1

2

3


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12

urt n

u nTs3 Fs sinc 3tnTs Fs2 Fs sinc 2 tnTs Fs

Frequency conversion & sub-sampling

Then convolve the sample streamwith the filter function:

urtgth t

urt

g h t d

urt n

u nTsh tnTs

urt

n

u nTsh t d


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13

1949: C. Shannon : Communication in the presence of noise

1915: E.T. Whittaker : Interpolation theory

1933: V.A. Kotelnikov : Carrying capacity of the ether

1928: H. Nyquist : Telegraph transmission theory

Some history

Detailed demonstration that band-limited signals can be represented by a sum of sinc functions, apparentlyindependently from Nyquist and Whittaker.

Classic! Deals with signal distortion in transmission channels like undersea cables, which were a hot subject,at the time.

Classic! Gives transmission capacity of a channel as a function of bandwidth and signal to noise ratio. Thesampling theorem is dealt with in section II.

Couldn't get my hands on that one. Everyone refers to him, so I mention him as well.

Other names: R.V.L Hartley, J.M. Whittaker, C-J. de la Valle Poussin, ...


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14 Practical signal reconstruction

Although mathematically Dirac deltas, brick-wall filters and infinitesums are quite nice to handle, in real electronic circuitry, you can'thave them.

The Dirac is replaced by an (almost) rectangular pulse of onesampling period duration, and filters are described by finitepolynomials, with finite-slope band edges. So, the output is heldconstant during each sampling period, which is functionally called a

zero-order hold, and a low-pass filter smooths over the steps.

ZOH Filter


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15 Practical signal reconstruction

As a consequence, the reconstructed signal spectrum is convolvedwith a sinc(f/F

s) function and some energy from adjacent spectral

images leaks into the desired band. Note that at the Nyquist

frequency, FN=Fs/2, the response is down by 3.9dB.If this is a problem, the reconstruction filter may be designed tocompensate. (You can also pre-compensate in the digital domain.)

s

s

-3.9dB

FN

f/F

sinc(f/F )

dB

-20dB/decade

-40

-35

-30

-25

-20

-15

-10

-5

0

0.1 1 10

HZOH

f1e

j 2 f Ts

j 2 fT

se

j f Ts sinc f T

s

x

( )x

T0

1


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16 Spectrum of quantization error

For 'large enough' and 'busy enough' signals, the quantization error is arandom variable with a flat distribution.

Quantization noise is white and spread out evenly over 0


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17 Spurious Free Dynamic Range (SFDR)

Unfortunately, quantization noise isn't always white: Simple ratios between F

inand F

scause some of the

quantization noise power to concentrate in discrete

spectral lines ADC non-linearities cause harmonics of the input

signal

Spurs appear in the spectrum:dBFS

FN

SFDR

12 bit ADC8k point FFT

140

120

100

80

60

40

20

0

0 500 1000 1500 2000 2500 3000 3500 4000

SFDR is the distance betweenthe input signal and thegreatest spur.

A little bit of dither can help toreduce spurs.

(Dither is the intentional injection of a little bit of noise.)


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18

Non-linearity creates harmonics

AD872A FFT plot ,fin=1 MHz, -0.5dBFS

0 5 MHz

THD is the rms sum of the first 6 harmonicscompared to the input signal, in dB

Total Harmonic Distortion (THD)


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19 Differential Non-Linearity (DNL)

In real ADCs, the quantization function isn't perfectly uniform

For an input signal with a uniform distribution,the distribution of output values is no longer

uniform.The DNL measures the normalized error of thenominal size of each quantization step.

AD9432 12-bit 105MS/s pipeline ADC

q(x)

x

missing

code

Missing codes

Non-monotonicity


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20 Integral Non-Linearity (INL)

INL measures the deviation of the ADC characteristic froma straight line through the end points (or sometimes from aleast squares fit)

AD9432 12-bit 105MS/s pipeline ADC

ADC

under test

comparator

Digital

Metrology

grade

voltmeter

Set

value

Measured

Value

Integrator

up/down

FS

+FS

input

output

Linearity error

Best fit straight line

Measured data


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21

SNRPs

P1.522 n

Effective Number Of Bits (ENOB):

Apply a nearly full-scale sinusoidal signal.Measure P

, as the rms sum over all frequencies,

ignoring DC and the first five harmonics, and

solve for n:

If you choose to also add in all harmonics into

the calculation ofP, you would get the SINAD.

(SIgnal over Noise-And-Distortion)(Which looks a little bit worse, of course)

SNR and SINAD are usually expressed in dBc or dBFS


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22 Inter-Modulation Distortion

Non-linearity also causes inter-modulation distortion. (Creating sumand difference frequencies from two applied tonesf

imd=nf

1mf

2.)

AD9432, IMD FFT plot

f1 f2 f1f2

f2f1

2 2

IMD is the rms sum of the inter-modulation products comparedto the rms sum of the inputsignals (usually in dB).

The order of an IMD productis |n|+|m|

23


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23 Clock jitter

t+ t

u(t+ t)

t

u(t)

Importance of clock jitterdepends on rate of changeof analogue input signal

A clock timing error tyields an

amplitude error:

U d u tdt t

This is a severe condition!

dBFS

FN

12 bit ADC

8k point FFT

140

120

100

80

60

40

20

0

0 500 1000 1500 2000 2500 3000 3500 4000

24


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24

t1

d u t

dt 2n

The effect of clock jitter

Tolerable jitter:

Ex: Suppose we digitize a 100MHz sinusoid to 10 bits:

d u t

dt2 108 cos2 108 t

t1

2 1082101.6 ps

u tsin2 108 t

A good quartz or ceramic resonatoroscillator is needed

So at the steepest slope:


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26 Cl k jitt li it SNR d f


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26 Clock jitter limits vs. SNR andfin

Even using the best clock, the resolution reaches a limit. Forexample, for an actual 12-bit ADC, the ENOB vs. F

inplot

might look like this:

ENOB

fin Hz

100ps

10ps

1ps

100fs

0

2

4

6

8

10

12

1k 10k 100k 1M 10M 100M 1G

27 T i l jitt f l k


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27

RC and logic gateoscillators

LC oscillators

Pierce oscillatorGood.Usually better than 1ps

FairJitter 10 - 100ps

PoorJitter >100ps

R

C

V+

shaper

limiter

V+

X shaper

limiter

Typical jitter specs of common clock sources

28 Oscillator jitter & phase noise


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28 Oscillator jitter & phase noise

L(f)

dB

offset Hz

180

170

160

150

140

130

120

10 100 1k 10k 100k

SSB phase noise of an oscillator

Upconverted thermal, schottky and 1/f noise

trms T02 0

S f4sin2 fdf

The term

T0

2 converts phase into time

S f is the spectral density of the phase noise

sin2 f is a weighting function

(For low frequencies ofS, the phase can't drift very far,

when = n/f, the contribution cancels, and there are

maxima in between.)

is the time between two events (Usually =T0)

(Function of Fourier frequencyfand sum

of both sidebands)

29 Clock jitter


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29 Clock jitter

Ground noise between clock source and ADC aggravates jitter

Decision level

Excellent FPGA

(Noisy)

ADC

source

clock

Don't route clocks through FPGAs!

ADC

Vnoise

Vclock

Noise may be due to magnetic interference or common impedancecoupling. Possible remedy: Differential clock.

(Complex logic circuits cause all sorts of interference)

Very goodclock source

Carefully filtered power supplies

AinADC

FF

Q D

FPGA

complicated

logic

But if you must, then resynchronizewith the original clean clock

30 Clock jitter summary


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30 Clock jitter summary

ADCs (and DACs too!) need good quality clock sources Digital electronics is not optimized for low crosstalk PLLs in FPGAs usually have *very* poor jitter specs

Treat your clock oscillator like a sensitive analogue circuit

Filter and bypass clock generation & distribution power supply extracarefully

Keep PCB layout tight and compact, minimize loop areas Refer clock source to the same GND as the ADC Do not route an ADC clock through an FPGA Don't use left-over gates in clock buffer package for other purposes

31 Data formats


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Data formats

1111 1111 max/2...

0...

0000 0000 -max/2

0111 1111 max/2 -1...

0000 0000 011111 111 -1

....

1000 0000 -max/2

1111 1111 max

...0000 0000 0

Straight binary

Offset binary

Two's complement

Note: To convert offset binary into 2's complement,

simply invert the most significant ADC bit.

32 Data formats


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Data formats

2500

2000

1500

1000

500

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

3000

3500

4000

4500

You were expecting this:

but you got this:

Reason: The ADC delivers2's complement numbers andthe sign bit is not in the rightplace.

33 Data formats


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s a a a a a a a a a a a

0 0 0 0 s a a a a a a a a a a a

Data formats

The sign bit isn't in the right place:


s s s s s a a a a a a a a a a a

Apply sign extension:


s a a a a a a a a a a a 0 0 0 0

or logical left shift:

a = (a^0x800)-2048;

a


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Data formats

BCD and display driver outputs. Handy for stand-aloneinstruments, panel meters, hand-held multi-meters.

Gray code: Only one bit changes between adjacent values.No glitches. Resolver disks. Angular and linear transducers.

a b c d e f g a b c d e f g a b c d e f g

inh

inl Intersil or Maxim/Dallas ICL7106

a

b

c

gf

e

d

35 Signal integrity


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S g a teg ty

... or how to get your signal digitized cleanly:

Interference (comes from elsewhere) and noise (inherent in the circuit)

Coupling paths: Common impedance coupling(Use generously dimensioned conductors or a star layout)

Inductive coupling(Keep loop areas small and put distance between them)

Capacitive coupling(Keep high-Z nodes and nodes with high dE/dt far apart, or put grounded shields betweenthem)

Zp

V+

Circuit 1 Circuit 2

Zp

V+

Circuit 1 Circuit 2

B B B

I

V

Ip

Vp

pI

shieldCp

Z

Cp1 Cp2

Z

36 Signal conditioning


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g g

R f

R i

sample

input

ADCBuffer amplifier adapts signal to ADC andprevents sampler kickbackRC circuit at ADC input isolates amplifierfrom ADC input capacitance

ADCInRG

R1

R1

R2

R2

R3

R3

Instrumentation amplifier: Goodcommon mode rejection, high gain,but only at low frequency

ADC

V+

V

Rt

ADC

V+

V

Rt

Baluns and transformers: Good

common mode rejection at highfrequencies

37 Signal conditioning


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g g

Single-ended to differential conversion(Often used for high-performance orlow voltage ADCs)

R

R

R

R

input

ADC

V+

V-

Baluns and transformers can also be used forthis.

Or use monolithic differential buffer amplifiers

(ADA4941, AD8351, LT6411, THS4503, etc.)

38 Input signal conditioning


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p g g

Summary:

Adapting signal range to ADC input range (Scaling & level shifting) Conversion between single-ended and differential signals Protecting the ADC input from overload Terminate long cables into their characteristic impedance... ...or, to the contrary, provide a high impedance to avoid loading the

source

Rejecting interference Filtering out-of-band frequencies (Anti-alias filter, noise reduction) Holding input constant while conversion takes place

39 ADC types


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Other architectures:

Mixed forms (E.g. flash with SA, or flash with -) Tracking ADC Voltage-to-frequency converters

Architecture Speed Resolution Linearity Applications

Flash Very fast (GS/s) Poor (8 bits) Poor Oscilloscopes

Transient recorders

Successive

approximation

Fast (MS/s) Fair (14 bits) Fair DSP, video, digital

receivers, instrumentation

- Slow (kS/s) Excellent (24 bits) Excellent Process control, audio,weight, pressure,

temperature measurement

Dual-slope

Integration

Very slow

(S/s)

Very good (18 bits) Very good Bench-top and hand-held

measuring instruments,

battery powered devices

40 The ADC landscape


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Dualslope integrationSigmaDelta

Successive approximationPipelineFlash

0

4

8

12

16

20

24

1 10 100 1k 10k 100k 1M 10M 100M 1G

Resolution[

bits]

Conversion rate Hz

MAX105

AD7621

AD7942

ADS574

ADS7826

ADS7827

ADS5547

ADS5463

AD9211

ADS1210

ADS1212

ADS1230 ADS1250

ADS1100 ADS1602

ICL7137

ICL7107TC7109

ADS1225

ADS1201

ADS5220

MAX104ADC083000

AD7631

AD7641

41 The successive approximation ADC


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Iin

Successive approximation

register

DAC

Comparator

Clock

Start

D0 D7

R

Input

RDY

IDAC

Digital

outputsSequence of operation:

Compare input with halfscale, keep if greater.

Add one quarter and

compare, keep if inputgreater.

Add 1/8 etc...

Usually clocked or strobedSerial data interfaceOften fixed conversion rate

Sometimes poor DNL

FS

bits

00 1 2 3 4

0.5

SAR ADC binary decision tree picture

42 Example of a SAR ADC: AD7474


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12-bit, 1 MS/s, serial interface SAR ADC

SOT23-6(1.6 x 2.9mm)

Input sampler (Cs=30pF)

Serial interface timing

43 The flash ADC


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-

+

-

+

-

+

-

+

-

+

-

+

-

+

Encoder

D0

D1

D2

Output

R

R

R

R

R

R

R/2

Comparators

R/2

Ain

Vref

Strobe

A resistor divider chain creates allpossible decision levels from a

single reference. 2n-1 comparators compare each level

with the input signal. Digital logic converts "thermometer"

code into binary. Sensitive to 'sparkle' codes Metastability Input capacitance

Usually 8 bits, rarely more than 10

Flash ADCs are the fastest:

44 Example of a flash ADC: MAX104


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192-contact BGA

8-bit, 1 GS/s flash ADC

50 differential inputs

250 mV input range

Metastability error rate 10-16

Differential PECL outputsDe-multiplexerNeeds 3 supply voltages+/-5 V and 3.3V

Many GND and Supply pins

25 mm

Pd = 5.25 WENOB = 7.5 bitsBW

in= 2.2 GHz

45 Mixed architecture ADCs


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Segmented or pipelined ADC: Sample rate comparable to flash ADCs, but with

several clock periods of latency. Resolution comparable to successive

approximation architecture.

Combining and error correcting logicTiming

12RDY

Clock

VinT/H

ADC DAC

G

4

T/H

timing ADC DAC

G

5

T/H

timing

ADC

5

46 Examples of a pipelined ADC: LTC2242

12 bi 250 S/ 5 i li A C


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12-bit, 250 MS/s, 5-stage pipeline ADCDifferential LVDS orde-multiplexed outputs2pF sampling capacitorDifferential analogue

input, BW 1.2 GHz

9 mm

Single-ended to differential conversion

47 The effect of oversampling


47/68


Increase sample rate:! Quantization noise is spread over a larger BW.Numerically low-pass filter the sample stream:! Out-of-band quantization noise power is removed.

Conclusion:! SNR gets better by 3dB/octave of oversampling rate.Dither may be necessary for very quiet ADCs.

FsF

N

F

N

Fs

Oversampling

and

iltering

Nyquist rate

Quantization

noise

Filter curve

Removed

noise

48 The / ADC


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ComparatorVin Digital

lowpass

filter +

Output

Clock1 FS

decimation

n

DtoA

Average duty cycle of comparator output reflectsinput value.Digital low-pass decimation filter trades sample ratefor resolution.

Good DNL, good resolution, slow.

49 The / ADC


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For the input: YX

1s1

For the noise:Y

Q

s

s1

1

s

X

Q

Y

Noise shaping!

Pretend that quantizer contributes random uncorrelated noise:

YQ

YX

Log(f)

Log(A)Decimation filtercutoff

Input signal is low-pass filteredQuantization noise is high-pass filtered

Decimation filter rejects high frequency! Resolution is improved

50 The / ADC


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Higher order loops and noise shaping, E.g., a 2nd order modulator:

Vin 1

s

1

s

Comparator

Output

Clock

Digital

filter

low-pass

DAC1 FS

decimating

For the input:

For the quantization noise:

Y

X

1

s

2

s1Y

Q

s2

s2s1

1

j

j

Y

Q

Y

X

dB

Decimation

filter cutoff

40

30

20

10

0

0.1 1 1

Decimating filter rejects noise

51 / ADC ailments


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Side tones, idling patterns, birdies

Modulator

output

Integrator

For some input values, the / modulator can produce repeating patterns

with repetition rates well below the sampling frequency These may leak though the decimation filter, causing a side tone or

'birdie'

Possible remedies include using higher order modulators anddither, to randomize things

52 Example of a - ADC: ADS1610


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Programmable, instrumentation ADC

12-16 bits, depending on filter settings

Input conditioningCircuit model of inputs

ADS1610 block diagram

53 Example of a - ADC: ADS1610


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Programmable, instrumentation ADC

12-16 bits, depending on filter settings

54 The dual slope integration ADC


54/68


Output

Counter

Clock

E

IRef

Input Iin

CComparator

Ucap

Integrating I RefIntegrating I in

Time

Counter runningT1

Integrate input during T1

Then:Integrate reference untilzero is reached, whilecounting clock pulses

Final count is proportional to input

Sometimes the signal source is inherently a pulsed current source(Photomultiplier)Variants: Time to Digital Converter (TDC)

Can be built for low power operation,

good for battery power equipment(Multimeters etc.)Integration time often chosen to rejectpower line interference

Excellent DNL

55 Example of a dual slope integrating ADC: ICL7106

Di tl d i LCD di l


55/68


Directly drives an LCD display

200 mV full scaleConversion time 300 msConsumes 1 mA @ 9 V

56 Example of a dual slope integrating ADC: ICL7106


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Analogue section of ICL7106

57 Voltage-to-Frequency converters


57/68


comparator

VinFout

-Vref

CiRi

Cf

Low-costSlow!Signal easy to transmit over large distancesVery good linearity

Input voltage is integrated onto CiA fixed-size packet of charge is

removed each time the switchconnects Cf to the input.

Applications:

Process controlEasy to use as integrating converter (Just add a counter)In combination with F-to-V converter: Cheap isolation amplifier

58 Example of a V-to-F converter: LM331


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8-pin DIPLinearity 0.003%Fmax 10 kHz

59 Special converters


59/68


Non-linear converters, A-law, -law, used in telephony.

Digital potentiometers (DS1669, MAX5438, AD5259, etc.

Digital output sensors, temperature, acceleration (AD7414, AD16006)Capacitance-to-digital converters (AD7745)

out

in

A-law compression curve

60 DAC architectures


60/68


Mixed architectures:

Segmented DAC

Interpolating DAC

Variants:

Multiplying DACs

Current or voltage output Differential or single-ended

Architecture

Kelvin-Varley divider Accurate, monotonous. Mainly as building block in integrated DACs

Thermometer DAC Monotonous. Limited number of bits

Binary weighted ladder Very common, but subject to glitches

R-2R ladder Widely used. Not very power efficient

- Linear, accurate, but complex.

61 Kelvin-Varley divider


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400

400

Vref

10k 2k 400

The ancestor of all DACs Still rivals the best modern DACs Available as rack mounted units

(Expensive!) Used as sub-circuit in IC DACs Variable Z

out: Buffer amplifier needed

Example: Fluke 720ALinearity, resolution : 10-7

Input resistance : 100 k , 0.005%

62 'Thermometer' DAC


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I I I

Iout

Iout

DecodeN

2N

N2 equal switched current sources

Inherently monotonic No glitches Limited number of bits (2N current sources!) Used as a sub-circuit in segmented DACs

63 Binary weighted DACVref

V


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Binary weighted resistor DAC:

8R

Iout

4R 2R R

LSB MSB

Iout2

Vref

R N

2n

Number of bits nApplied input valueN

Example: THS5641, 8 bit, 100 MS/s, 35 ns settling time

64 R-2R Ladder

Very common architecture


64/68


Vref

2R 2R 2R 2R

RRR

R

RVout

MSBLSB

VoutVrefN

2n

y

Uses only two resistor values Voltage or current output Not very power efficient Often as multiplying DAC

Voltage output R-2R DAC

2R 2R 2R 2R

RRR

R

R

MSBLSB

Vref

Iout

IoutCurrent output R-2R DAC

Example: AD5445, 12 bit current output,

20.4 MS/s, 80 ns settling time

Reference input response vs. frequency and code

65 PWM DAC


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Pulse Width Modulation Inherently linear

Limited resolution Often used in -controller chips Applications: Motor control

N

0

Cklowpass

filter

Vout

Comparator

Comparator

Counter

66 Segmented DACs

C bi i f h hi


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Combination of other architectures, tooptimize speed, linearity, SFDR, glitchenergy, etc.Common for high performance DACs usedin instrumentation and communicationequipment.

Vref

VoutR R R

R 2R 2R 2R

A=1

Combining a Kelvin divider with an R2R ladder

Example: AD9753, (12 bit, 300 MS/s)combines two thermometer (5 and 4 bits)sections and a binary weighted stage (3 bits).

AD9753 block diagram

67 - DAC

modulator


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kFsFs

N N N MSB

Digital logic

Vout

Analogue

Lowpass filter

modulator

Interpolatingfilter z

1

1

kFs

Inherently linear Complex modulator entirely digital Usually has a 1-bit DAC, sometimes multi-bit Large oversampling ratio eases output filter design

Example: AD1955 audio DACUpdate rate 192 kHz, SNR 120 dB

68 Conclusions


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There are ADCs and DACs for almost any imaginable application Performance is ever getting better Prices keep going down (15 years ago, a 12 bit 10 MS/s ADC cost 1 k$. Now it's around 10 $)

Digital is here to stay!

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From Digital to Analogue and Forth