Dominique Gigi CMSweek 6 June 2003

1. Overview2. Block-diagram

- FRL - Transmitter mezzanine

3. Test setup4. Options

- 8 configurations- Backplane IO- PCI >>> PCI-x

5. Conclusions

Dominique Gigi CMSweek 6 June 2003

Dominique Gigi CMSweek 6 June 2003

PCI connector 64-bit

FRL Function

IN_1

IN_2

IN_3

IN_4

FPGA

Compact PCI32-bit 33MHz

Memory4Mbytes

Commercial Optical LinkMyrinet Lanai X

Compact PCI Back-plane

64kB

64kB

64kB

64kB

64b@100MHz

PCI 64b @ 66 or

PCI-x 64b @ 100MHz

64b @ 66 or 100MHz

Bridge

FPGA

Dominique Gigi CMSweek 6 June 2003

SL

ink6

4 pr

otoc

olAltera

ACEX

LVDS

LVDS

1 switch to choose the frequencyGenerate 3 frequencies:-40MHz from 10 to 15 meters-60MHz from 5 to 10 meters-80MHz <= 5 meters

Dominique Gigi CMSweek 6 June 2003

PC

PCI to CompactPCI

Spy mode (Event_ID# 1 to 1024)

Acquisition (64b-66MHz)

FED emulator

Myrinet protocol emulator

FRL

LVDS 640MB/s

Dominique Gigi CMSweek 6 June 2003

HTWAIT WAITEvent(t) Event(t-1)Event(t+1)

Event_IDEvent_size (bytes)BX_idSource#Time (x100ns) before next event

FED_emu1(GIII)

HTWAIT WAITEvent(t) Event(t-1)Event(t+1)

FED_emu2(GIII)

From 1 to 2 M event descriptorsUsing SDRAM memory

64kB

64kB

Myr_protocol_emu(GIII)

Host_PC

PCI to CPCI link

PCI

64b@66M

Hz

FRL

ZBTmemory

Bridge

FED-kit

H

T

Source#Event_IDPacket#reserved

Pack. sizereserved

FRL_Myrinet protocol

H

Packet size

H

T

PC memory

WC

_E0

WC

_E1

Spy mode

Data block size

LVDS

LVDS

FRLFPGA

Block0Block1Block2Block3Block4Block5Block6Block7Block8Block9

Blockn

H

H T

H T

H

FED1FED2

Dominique Gigi CMSweek 6 June 2003

Add[2..0]

111

110

101

100

011

010

001

000 (configuration by default POWER ON)

Bus to FPGAconfiguration

Signal to reconfigure FPGA

Accessed throughPCI Bridge configuration

NB: Bridge design (EEPROM) and FRL (FLASH) designs can be downloaded through the PCI Bridge configuration.

FRL with Input

FRL diagnostic

FRL (Evt generator)

FRL (Evt memory)

128 ms to load a design from Flash to FPGA

Flash memory

Dominique Gigi CMSweek 6 June 2003

Compact PCI backplane

Lemo

Ethernet

• 16 IO’s FRL• 15 IO’s Bridge• 5 v• 3.3v• -12v• +12v• GND

It’s not a bus each FRL has its individual pins

CompactPCI bus32-bit@33MHz

Dominique Gigi CMSweek 6 June 2003

Bridge Convert

PCI access (32-bit@33MHz)to

PCI-x access (64-bit@100MHz)

PCI-x bus64-bit100 MHz

-Access to the LanaiX configuration

-Pending data transfer

AD[63..0]FRAMEIRDYTRDY

AD[63..0]FRAMEIRDYTRDY

Addr Data

Addr DataAttr

Dominique Gigi CMSweek 6 June 2003

4 points to control:•Inputs (Connectors, FIFO,LVDS,FPGA)

•PCI bus •ZBT memory (data, address, control)

•JTAG

•One PC controls 16 FRLs (CompactPCI backplane)•GIII generates events and receives them through PCI to control data and header registers report errors•ZBT is tested through the SPY mode application•JTAG is tested with JAM-Player (adapted by Christoph) access the JTAG chain through PCI bus

Dominique Gigi CMSweek 6 June 2003

1. PCI-x protocol is tested (without data transfer; single access)

2. The 2 Inputs were debugged

3. ZBT memory access (64b@100MHz)

4. Start the setup implementation for test production

5. Pending• transfer data with PCI-x protocol to Myrinet LanaiX• merge function (logic – no hardware) • CRC implementation (FED_emu + check inside FRL)