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Retrospective Theses and Dissertations

1987

Frequency to Voltage Signal Conditioner Circuit Design Frequency to Voltage Signal Conditioner Circuit Design

Pamela Ann Nelson University of Central Florida

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FREQUENCY TO VOLTAGE SIGNAL CONDITIONER CIRCUIT DESIGN

BY

PAMELA ANN NELSON B.S., Milwaukee School Of Engineering, 1979

RESEARCH REPORT

Submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering

in the Graduate Studies Program of the College of Engineering University of Central Florida

Orlando, Florida

Fall Term 1987

ABSTRACT

The following report explains the design of a

frequency to voltage converter circuit using a charge pump.

In general, it may be considered a black box which accepts

a O to 2 kHz frequency signal in, and outputs a Oto 10

volt DC level.

An additional feature of this circuit is the detection

of digital direction signal. A "logic high" direction

signal will give Oto 10 volts out; a "logic low" direction

signal will give Oto -10 volts.

A voltage regulator is also available to power an

off-board frequency sensor.

TABLE OF CONTENTS

INTRODUCTION

DESIGN . . . . . . . . . . . . Design Specification . . . . . ........ .

Inputs . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . Temperature Drift Accuracy Requirements Response Time Requirements ......... . Power Requirements . . . . . . . . . . . .. .

Schedule . . . . . . . . . . . . . . . . . . . . . . Design Guidelines ....... .

Design Practices .....•..... Components . . • • • • . ... Circuits . . . . . • . . . . . . . Boards . • . . . . . . . . . . . . . . · Design Review . . . . . ..... Test . . . . . . . . . . . . . . . . .

Design Implementation . . . . ..... . Theory . . . . . . . . . . . . . . . . . .

IMPLEMENTATION Schematic Parts List .... Analysis ....•.

Worst Case Tolerance Analysis Overall Worst Case Tolerance .

Worst Case Temperature Analysis .... Ove·rall Worst Case Temperature .

Compromises . . . . . ...... .

RESULTS . .... . Predicted Results Actual Test Results

SUMMARY

. . . . . . . . . . . . . . .

. . . . . . . . . . . . .

APPENDIX A . . . . . .. · · · · • • · · • · List of References .....•.

Other Souces Consulted .........•.•

iii

1

2 2 2 2 3 3 3 4 5 5 5 6 6 6 6 7 9

17 17 18 19 19 20 20 20 23

25 25 27

29

30 30 30

INTRODUCTION

A frequency to voltage converter (FVC) will provide an

output voltage proportional to frequency which is

independent of the input voltage or other input parameters.

Applications for the FVC circuit range from simple

speed switch for anti-pollution control functions in

automobiles or a tape recorder shut off, to motor speed

controls in industrial or military equipment. The most

common application of the FVC is in interfacing with

magnetic pickups, as in performing speed monitoring.

The FVC function can be designed using a one shot

circuit, or a charge pump, or a complete FVC integrated

circuit.

This particular design will use the charge pump

circuit, chosen for its flexibility and accuracy. It shall

be used as a RPM signal conditioner to measure the speed of

a ships engine. It will become a Standard Electronic

Module for the Navy to use in various ships applications in

the future.

DESIGN

The design specification, schedule, guidelines,

implementation and theory are explained in this section.

Design Specification

A frequency to voltage converter board shall be

designed which will contain a frequency signal conversion

and conditioning circuit and output drive circuit. The

environmental requirements are:

* Temperature range Oto 70 degrees C.

* Humidity Oto 90% non-condensing

Inputs

The board shall receive a frequency of Oto 2,000 Hz

with a 40/60% duty cycle. It shall also receive a logic

signal (Direction) equivalent to clockwise (logic "l") or

counterclockwise (logic "0").

Outputs

The board will output Oto +/-10 VDC, corresponding to

the 0 to 2,000 Hz input frequency and direction. The

output drive current will be 5 mA maximum. The accuracy

required is specified in Table 1 at 25 DEG C.

2

TABLE 1

ACCURACY REQUIREMENTS

FREQUENCY RANGE ACCURACY RIPPLE P-P COMMENT (HERTZ) (% FULL SCALE) (% FULL SCALE)

0 - 20 20 - 30 30 - 230

230 - 1200 1200 - 2000

0.5 0.5 0.3 1.0

1.4 1.2 0.5 0.5

140 mv max 140 mv max

Temperature Drift Accuracy Requirements

The temperature drift shall be+/- 1.0% of full scale

for temperature change of Oto 70 degrees C in addition to

the initial tolerance specification.

Response Time Requirements

The signal output shall rise to within one time

constant of its final value within 60 milliseconds of a

step application of an input pulse train to the sensor

electronics.

Power Requirements

The circuit shall be powered from +15 voe, -15 voe,

and +5 voe with +/-5% tolerance on each supply. The

circuit power consumption shall be less than 2 watts.

3

Schedule

A design schedule is a tool for the designer to keep

the product development cycle flowing and a way to measure

productivity and cost. Table 2 shows a task schedule for

the frequency to voltage converter design.

TABLE 2

DESIGN CYCLE SCHEDULE

TASK COMPLETION DATES

Preliminary Design Spec .... 9/ 4/87 Block Diagram .......•. 9/11/87 Schematic . . . . ... 9/25/87 Parts List ............ 10/ 2/87 Gather Parts ...•......• 10/ 9/87 Build Circuit . . . . . • 10/16/87 Test Design . . . . . . . 10/23/87 Complete Design Document ..... 10/30/87 Research Report Review ...... 11/ 6/87 Research Report Revise . 11/10/87 Research Report Presentation .•. 11/13/87 Research Report Revise ...... 11/27/87 Turn in Research Report ...... 12/ 4/87

4

* *

* * * *

*

*

*

*

Design Guidelines

Design Practices

Consider safety to the user. Know the electronic parts and their limitations.

Complete a worst case tolerance analysis. Complete a temperature verification analysis. Complete a power supply verification analysis.

Guard against voltage overload and excessive current. Consider Electrostatic Discharge (ESD). Consider Electromagnetic Interference (EMI). Interface with Reliability Engineering, to improve system reliability and effect of faults on system. Interface with Test Engineering, to assure an adequate number of test points are provided. Design for testability. Be aware, Kaufman [1] equations calculate propagation delay of 1.5 ns/ft for direct and cable wiring. Minimize maintenance time (MTTR) by providing fault indications, fault detection and isolation. Update documentation to reflect the latest circuit revision.

Components

* Choose components with second sources. * Derate components at worst case temperatures. Examples

are listed below: Fixed Resistors: 50% of rated wattage, 80% of rated voltage Variable Resistors: 50% of rated wattage, 70% of rated current, 80% of rated voltage Capacitors: 50% of rated voltage, 70% of rated current Diodes: 60% max of rated reverse voltage, 50% of rated forward current Micro-circuits: T-junction 100 C max, T-ambient 75 C max, 75% of operating frequency

Digital: 80% max of rated output current Linear: 70% max of rated bias voltage, 75% of rated output current

5

* *

*

*

*

*

Circuits

Standard designs should be used wherever possible. Protect equipment and I/0 to prevent damage from unexpected operating conditions (transients, shorts, etc.). Consider power up and power down conditions. Decouple power supplies on to board with filter capacitors for both high and low frequencies. 100 uF tantalum and 0.1 uF ceramic capacitors are recommended for each supply. Use a minimum of a 0.1 uF decoupling capacitor for every three ICs. All signals on and off a board will be buffered (i.e., a single gate or single op amp interface). Built-In-Test (BIT) must be designed into the circuit for fault detection and board-level fault isolation. Minimize BIT circuits to < 10% BIT circuits for total board.

Boards

* A design document will be written for each board. * Position parts so they are easily accessible for

test. * Position parts so that heat radiating components do

not cause heating in excess of specification for safe operation.

* Position I/0 resistors and ICs close to the connectors.

Design Review

* A minimum of two internal design reviews are required per board, one before bread board test, and one among the design team to be scheduled during design effort.

* Representatives from engineering, manufacturing, reliability, test and system will attend a design review before the design goes to drafting.

Test

* Test circuitry to all specified requirements. * Test all configurations under all conditions.

6

Design Implementation

The frequency to voltage converter circuit contains

four major functions, as shown in Figure 1 .

.freq_,n CHARGE

BUFFER 01:!Il-'ES::~ ' PUMP /'

1.,.16 I ta.ge_out

vo I ta.qe_r·e +·_c,ut. / ' - JOLTAGE

" REG.

d, r·ect. , on_, n

Figure 1. Block Diagram

A buffer will receive the frequency signal. A buffer

is chosen with hysteresis and good noise immunity (i.e.,

good common mode noise rejection). It shall accept signals

from approximately 100 mv to several volts in amplitude.

The buffer squares up the signal as well as rejecting some

noise on the input signal.

The buffered frequency signal shall control a charge

pump circuit. A Double-Pole-Double-Throw (DPDT) analog

switch shall switch a voltage reference to a capacitor for

charging, and switch the charged capacitor to the input of

an amplifier for discharging. The switch is chosen for low

leakage and steady on resistance. The capacitor is chosen

for low leakage.

7

8

Discharging current flows into the summing junction of

an operational amplifier circuit, which in turn charges a

feedback capacitor. The voltage level on the output of the

op amp corresponds to · the number of times the charge

capacitor discharges and the closed loop gain of the

amplifier. The op amp is chosen for accuracy with high

input impedance and low leakage.

A filter is used to smooth out the ripple voltage

caused by the charging and discharging capacitor. The

filter must have a time constant within the time delay

constraints of the system.

An inverting amplifier and a non-inverting amplifier

shall receive the converted, filtered signal. The output

of these unity gain amplifiers shall be switched to the

output drive stage by an analog switch controlled by the

direction input signal. A voltage follower shall drive the

signal off the board. These op amps are chosen for

accuracy, low drift, and drive capability.

A voltage reference supplies accurate current to the

charge pump. This reference, VREF, outputs +10 voe with a

maximum tolerance of+/- 0.5%. A voltage regulator is

available to power a sensor. It shall be driven from the

+15 volt supply, and it shall output +12 volts with a

maximum tolerance of+/- 5%.

Theory

The frequency signal shall control an analog switch,

which connects a voltage reference to a capacitor, or

connects the capacitor to an amplifier circuit. See the

charge pump circuit in Figure 2. While the frequency

signal is low (0 volts), the switch connects the VREF to

Cl; while the frequency signal is high (5 volts), the

switch connects the Cl to the amplifier circuit.

The input frequency is converted to a voltage level by

a charge pump circuit. When a given amount of charge (Q)

is transferred at a given rate (frequency) there is a known

amount of current flow (I).

frequency_,n

VRET

ANFLOG DPST

SWITCH

Figure 2. Charge Pump Circuit

9

10

The switch resistance variation shall have one-tenth

the effect on the total resistance variation if Rl and R2

are chosen to be ten times Rsw. The analog switches have a

nominal on-resistance of 75 ohms. Therefore, a 1 k ohm

resistor is picked for R2 (RNC55H1001DS). Where "H" is 50

ppm/ C temperature variant, "D" is 0.5% tolerance, and "S"

is 0.001%/1,000 hour failure rate.

after Cl is calculated.

Rl shall be chosen

Rl > (10 X 75 = 750)

Rl = 1,000 ohms

It takes ten times the R2Cl time constant to discharge

the capacitor down to 0.45 mv, which is 99.9955% discharged

according to Mazda (2). The capacitor must be fully

discharged before the input frequency switches to charge

the capacitor again. The switch time is the reciprocal of

2 times the maximum input frequency. The capacitor value

is chosen for a maximum frequency of 2 kHz. The switch

resistance must be included with R2 in these calculations.

t ---

Vcap = VREF e R2Cl Mazda (2)

Vcap = 10 -10

= 0.45 mv e

1 = 10 X R2Cl Mazda (21

2 Freq

1 (2 x Freq max) >

10 X (R2Cl)

4,000 >

Cl <

1

(10) X (1,000 + 75) X (Cl)

1

(4,000) X (10) X (1,075)

11

Cl < 24,096 pF

A capacitor of value 18,000 pF (CCR06CG183BS) is

chosen.

for 0.1%.

The "CG" stands for 30 ppm/C and the "B" stands

VREF is a +10 volt reference with a tight tolerance of

+/-0.5%. Rl is chosen to limit inrush current flow,

however RlCl must have a time constant that is

one-twentieth the period of maximum operating frequency.

Therefore, a 1 k ohm resistor is picked for Rl

(RNC55Hl001DS).

1 RlCl < = 25 us

20 X 2000 Hz

Rl < 1389

These values of Rl and Cl charge the capacitor to

10.00 volts in 0.18 millisecond. R2 and Cl discharge the

capacitor to 6E-11 volts at the maximum frequency of 2 kHz.

Given the R2 and Cl chosen, this circuit could operate up

to 5 kHz with an increased error of 0.3 mv due to remaining

discharge voltage.

circuit gain.

This error would be mul~iplied by the

12

The duty cycle of the input frequency must provide for

at least 0.19 milliseconds of discharge times. A 2 kHz

maximum input frequency has a 0.5 millisecond period. A

50% duty cycle gives the capacitor 0.25 ms to discharge. A

36/64% duty cycle gives the capacitor 0.19 ms to discharge.

Any input frequency with worse than 36% duty cycle will add

error to the circuit.

The capacitor charge with respect to time is:

C = Q

V

Vcap = VREF e

I =

t

RCl

dQ

dT

Mazda [2)

A charge (Q) is transferred at a given rate (dT) to

provide a current. With the components (C • 1.BE-8, VREF =

10), Q ranges from 1.BE-7 to O coulombs. A maximum

frequency of 2 kHz corresponds to a rate of dT = 0.5 ms.

Since the capacitor will have enough time to fully

discharge, dQ = 1.SE-7. Therefore the current (I) will be

0.36 mA using the equation above for 2 kHz input. R3 and

R4 in the feedback loop of the amplifier are selected to

cause a 10.00 volt output with this current (0.36 mA). R3

+ R4 calculate to 27,778 ohms. This value is verified in

the following pages. See Table 3 for the voltage, charge,

and current values though the a discharge cycle.

VOLTAGE ( V)

10 9 8 7 6 5 4 3 2 1

TABLE 3

DISCHARGING CAPACITOR CURRENT

CHARGE TIME (COULOMB) (USEC)

1. 8 0E-07 0 1. 62E-07 2.04 1.44E-07 4.32 l.26E-07 6.90 1. 08E-07 9.88 0.90E-07 13.41 0.72E-07 17.73 0.54E-07 23.30 0.36E-07 31.14 0.lSE-07 44.56

At 1000 hertz input frequency,

13

CURRENT (MA)

8.824 7.895 6.977 5.844 5.099 4.167 3.230 2.296 1.340 0.001

the capacitor

discharges 20 times in 20 milliseconds. At 100 hertz, the

capacitor discharges twice in 20 ms. The waveforms are

shown in Figure 3. The current flows into the summing

junction of the integrating amplifier circuit, which in

turn charges the feedback capacitor.

20 mS

10 ms 20 mS

Figure 3. Discharging Voltage Verses Time

14

The average voltage on the capacitor can be

calculated. The integral of the voltage signal over the

discharge period divided by the time period gives the

average voltage on the capacitor.

lORCl Vcap-= F int(

0

t

VREF e RCl ) dt [volts x seconds]

Vcap s (VREF x RCl) - (VREF x RCl x e-10 ) x F

[ 2 1

"F" is the frequency of the input signal in hertz, and

"R" is (R2 + Rsw) in ohms. The equation is integrated from

(0 to lORCl) which is the maximum time constant of the

discharging capacitor circuit.

VREF is 10 volts, and R is (1075) ohms, and Cl is

18,000 pF. Therefore, the average voltage on the capacitor

is:

-10 = [(10 X 1075 X 18E-9) - (10 X 1075 X 18E-9)e ] X F -= (0.0001935 - 8.78E-9) X F = (0.00019349) X F = (0.001935 X 2,000 Hz)

Vcap = 0.387 v

The amplifier circuit must bring this voltage to 10

volts for a full scale output. See the amplifier circuit

in Figure 4.

Rsw

(0.387 x GAIN) c +10.0 volts GAIN ~ 25.8398 v/v

-(R4+R3) AMPLIFIER GAIN =

(R4+R3)

1,075

(R2+Rsw)

= 25.8398

(R4+R3) = 27,778 ohms

R2

Figure 4. Amplifier Circuit

15

Mazda (2)

A standard value for R3 is 26,700 ohms (RNC55H2672DS)

where "D" is 0.5% tolerance and "H" stands for 50 ppm/ C.

R4 shall be a 2K potentiometer (RJR26HW202S) to adjust

(R4+R3) to 27,778 ohms. "W" is the terminal type, printed

circuit pins in this case. C2 is used for filtering. A

1.0 uF (M39014/02-1419) is a standard value giving a time

constant of 27.8 ms.

RC= 1.0 uF x 27,778 = 27.8 ms Mazda [3]

16

The active filter amplifier stage buffers and filters

the signal. R6 and R7 shall be 20 k resistors

(RNC55H2002BS, where "B" is 0.1% tolerance). C3 is chosen

1.0 uF (M39014/02-1419) to give a response time of:

RC= 1.0 uF x 20,000 = 20 ms

C3

Figure 5. Filter Circuit

An inverting amplifier changes the Oto +10 voe signal

to a Oto -10 voe signal. The non-inverted signal and the

inverted signal are switched by the Direction signal

controlling an analog switch. The output is buffered using

a voltage follower.

IMPLEMENTATION

The schematic, parts list, analysis and

sections explain the design implementation.

VOLTAGE: RE:ClJLATCR

·HS_LJo Its_, n

d, r,u:~t, on_, n

ANPLOG SWJTCH

Schematic

RB

compromises

C!I

LJoltagg_out

Figure 6. Frequency to Voltage Converter Schematic '

17

18

Parts List

The circuit parts are listed in Table 4 to Military

Specifications, and at the highest reliability available.

The circuit board, connector and cabling do not show up on

this parts list. The power supplies and packaging are also

assumed to be standard equipment.

IDENTIFICATION NO

OP400 MM54HCT14J HI-508 DG303A AD581 LM120 RNC55Hl001DS RNC55H2672DS RNC55H2002BS RJR26HW202S JANTX1N5553 CCR06CG183BS M39014/02-1419 M39014/02-1350 M39003/01-8188

TABLE 4

PARTS LIST

DESCRIPTION

Quad OP AMP Buffer Analog Switch Analog Switch Voltage Reference Voltage Regulator Resistor, 1 K Resistor, 26.7 K Resistor, 20 K Resistor, variable Diode Capacitor, 18,000 Capacitor, 1.0 uF Capacitor, 0.1 uF Capacitor, 6.8 uF

QUANTITY

1 1 1 1 1 1 2 1 4

2 K 1 2

pF 1 2 6 3

19

Analysis

Circuit Analysis includes tolerance, temperature,

timing, and power calculations. Table 5 lists the

component specifications to aid the worst case tolerance

and temperature analysis.

PART

VREF Rl,R2 Rsw R3 R4 R5,R6, R7,R8, Cl F

TABLE 5

COMPONENT SPECIFICATIONS

NOMINAL TOLERANCE

10 V 5 mv 1 k 0.5%

75 ohms 10 ohms 26.7 k 0.5%

2 k N/A 20 k 0.1% 20 k 0.1%

18,000 pF 0.1% 2,000

TEMPERATURE

10 ppm/°C 50 ppm/°C

5 ohms 50 ppm/°C 50 ppm/°C 50 ppm/°C 50 ppm/°C 30 ppm/°C

Worst Case Tolerance Analysis:

Vcap = (VREF) X (Cl) X (Rl+Rsw) X (F)

Ideally Vcap s 0.387 volts

Vcap • 10.005 x 1.8018E-8 x (1005+85) x 2000

Max Tel. Vcap = 0.393 volts

Max-Ideal x 100 - +1.55% tolerance error.

Ideal

The error is multiplied by the gain of the circuit. Ideal gain: (R3 + R4). 27,778 so R4 is set at 1078 ohms.

27,778/1075 s 25.84 v/v

Tolerance: 27,912/1090 - 25.607 v/y which is -0.90% tolerance error

The filters give error in the gain also:

20 K resistors give +0.2% error for 0.1% tolerance.

Overall Worst Case Tolerance:

Tel. Vout • Vcap x Gainl x Gain2 = 0.393 X 25.607 X 1.002 = 10.0837 V

Ideal Vout = 10.0 v so tolerance gives 0.84% error.

The potentiometer adjusts out this total tolerance error.

Worst Case Temperature Analysis:

10 ppm/ C x 45 C = 0.045% 30 ppm/ C x 45 C = 0.135% 50 ppm/ C x 45 C = 0.225%

Vcap = (VREF) X (Cl) X (Rl+Rsw) X (F)

Ideal Vcap = 0.387 volts

Temp. Vcap = 10.0045 x 1.8024E-8 x (1002+80) x 2000

Temp. vcap = 0.390 or +0.77% temperature error.

The error is multiplied by the gain of circuit.

20

Ideal gain: R3 + R4 - 27,778 so R4 is set at 1078 ohms.

Temperature: 27840/1082 = 25.723 v/v which is -0.45% error

The filters give error in gain also:

20 K resistors give +0.45% error for 50 ppm/°C temp. coef.

Overall Worst Case Temperature:

Temp. Vout - vcap x Gainl x Gain2 • (0.390) X (25.723) X (1.0045) • 10.077

Ideal Vout - 10.0 v so temperature gives 0.77% error.

21 TABLE 6

WORST CASE ERROR SUMMARY

CIRCUIT TOLERANCE TEMPERATURE DRIFT

Charge Pump = 0.011 +/- 0.77% Amplifier = adjusted out -0.45% Filter Amp = adjusted out +0.45% Inverting Amp = adjusted out 0.09% or Non-Inv Amp = 0.001 0.001% Voltage Follower(2) = 0.001 0.001%

Totals = 0.013% 0.86%

Table 7 gives a summary of the functional delays

throughout the circuit. The total delay through the

circuit comes to approximately 48 ms, which is well within

the requirement of 60 ms. Table 8 breaks ou~ the power

consumption per device and totals to less than 1 watt.

FUNCTION

Input Buffer Charge Pump

TABLE 7

RESPONSE TIME SUMMARY

TIME DELAY

= 38 ns max. = 36 us + 1 pulse = 27.Sms

of Freq. Amplifier Components Filter Amplifier = 20 ms (ripple-reducing) Inverting/Non-Inv Amp = 66 us Output Driver = 66 us

Total 48 ms

IDENTIFICATION NO

OP400 MM54HCT14J HI-508 DG303A AD581 LM120 RNC55H1001DS RNC55H2672DS RNC55H2002BS

TABLE 8

POWER REQUIREMENTS

DESCRIPTION

Quad OP AMP Buffer Analog Switch Analog Switch Voltage Reference Voltage Regulator Resistor, 1 K Resistor, 26.7 K Resistor, 20 K

TOTAL POWER CONSUMPTION<

22

POWER

18.1 mA 1.0 mA 1.0 mA 1.0 mA 5.0 mA

15.0 mA 10.0 mA

5.0 mA 5.0 mA

1 WATT

23

Compromises

Throughout the design several compromises were made

for the purpose of cost, schedule, and circuit performance.

The input buffer gives minimal noise rejection. If

this circuit is to accept a frequency signal in a noisy

environment it may be necessary to change the input buffer

to a differential amplifier with input filtering and

voltage protecting diodes. Each application must be

examined for its affects on the circuit.

I chose to use discrete components for the charge pump

circuit rather than use an integrated circuit to perform

the frequency to voltage conversion. Typically the F/V

Converter IC consists of more than just the charge pump.

Some include frequency input conditioners, sample and hold

circuits, and zero crossover detectors. They require

external components to adjust the input frequency range and

ripple filtering. For this research report it was better

for analysis purposes to fully examine the discrete charge

pump, rather than a particular FVC IC. Component

availability was also an issue in this decision.

The values of Rl and Cl may be changed, and the gain

adjusted to accept inputs up to 100 kHz. A counter/divider

device could be included on the circuit front-end to accept

24

frequency inputs greater than 100 kHz. If board space,

application, and cost justifies this additional circuitry

see Kashoro (4) for more details.

It takes time to filter out ripple. For applications

which require faster response time, the RC filter can be

decreased, but the ripple output will increase. An AC

coupled differential amplifier filter as explained by

Grenlund [SJ could be used in addition to the active low

pass filter. The active filter AC couples the signal to

the positive input of the differential amplifier, and

brings the signal directly into the negative input of the

differential amplifier. The difference between the signals

is merely the ripple riding on top on the voltage level

waveform. Ideally this signal is subtracted, but with op

amp errors and capacitor limitations, some of the ripple

remains as explained by Pease (6). The capacitor value

creates the cutoff frequency; therefore the low end

frequencies are still by-passed by the filter, and the

ripple remains.

cost.

Circuit accuracy may be improved with a sacrifice to

Tighter tolerance and temperature stable components

are more costly.

RESULTS

The predicted results as well as the actual test

results verify the FVC design.

Predicted Results

Error due to duty cycle is predicted as follows:

Vcap x GAIN = Vout

delta Vcap x GAIN = ERROR

t

(0.0001935)e 0.00001935 X 25.84

Any "t" greater than l0RC is considered error free.

At 2000 hertz the time period is 0.5 millisecond.

DUTY CYCLE

50/50

TABLE 9

DUTY CYCLE ERROR

CHARGE/DISCHARGE TIME

0.25 ms I 0.25 ms

OUTPUT

0

ERROR

mv 60/40 0.30 ms I 0.20 ms 0.84 mv 70/30 0.35 ms I 0.15 ms 11 mv 80/20 0.40 ms I 0.10 ms 147 . mv 90/10 0.45 ms I 0.05 ms 1950 mv 95/ 5 0.475ms I 0.025ms 7099 mv

25

26

The input buffer provides hysteresis, which affects

the duty cycle. The amount of hysteresis may vary from 0.5

to 1.5 volts. The duty cycle time depends on the rise and

fall time of the input signal. If the input frequency has

a duty cycle of 40/60%, and a rise and fall time of 50 ns,

the duty cycle would change by only 15 ns. The input

frequency with rise and fall times of 0.2 ms, could change

the duty cycle by 0.067 ms causing as much as 11 mv of

error on the output. For input frequency signals with this

much signal distortion, it is recommended to use a

differential amplifier with filter as the input stage,

rather than the buffer.

Ripple is expected on the output

amplifier stage after the charge pump.

dominant at low frequencies.

of the first

This ripple is

The charge capacitor fully charges and fully

discharges, but there is a delay before the capacitor is

switched to the VREF for another charge. At this time the

filter capacitor in the feedback loop of the amplifier

circuit discharges. This second capacitor is part of an RC

filter, with a response time of 27 ms. The low frequency

ripple is not filtered. Therefore, the charging and

discharging of the capacitor is seen at the output. In

order for the filter to work at lower frequencies, the

filter time constant would need to be increased.

FREQ IN CALC

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Actual Test Results

VOUT

V

V

V

V

V

V

V

V

V

V

V

V

V

V

TABLE 10

TEST RESULTS

MEAS VOUT

V

V

V

V

V

V

V

V

V

V

RIPPLE

mv

mv

mv

mv

mv

mv

mV

mv

mv

mv

mv

mV

mv

mv

27

DC ERROR

mv

mv

mv

mv

mv

mv

mv

mv

mV

mv

mv

mv

mV

mv

28

The test results show the circuit meets the accuracy

specifications. Table 11 relates the test results to the

specification for accuracy.

TABLE 11

TEST RESULTS VERSES REQUIREMENTS

SPEED RANGE ACCURACY RIPPLE P-P SPEC/MEASURED SPEC/MEASURED

(HERTZ) % OF FULL SCALE) % OF FULL SCALE)

0 - 20 2 mv 90 mv 20 - 30 50 mv 2 mv 140 mv 40 mv 30 - 230 50 mV 2 mv 120 mV 40 mv

300 - 600 11 mv 3 mv 50 mv 5 mv 600 - 1200 30 mv 3 mv 50 mv 5 mv

1200 - 2000 100 mv 4 mv 50 mv 3 mv

Temperature tests should be done on Printed Circuit

Boards, and the results documented. Table 12 shows the

expected accuracy results with 0.86% temperature drift.

TABLE 12

EXPECTED RESULTS THROUGH TEMPERATURE

SPEED RANGE ACCURACY (HERTZ) SPEC/EXPECTED

0 - 20 0.1 mv 20 - 30 so mv 1. 3 mV 30 - 230 so mv 9.9 mV

230 - 1200 30 mV 51. 6 mv 1200 - 2000 100 mv 86.0 mV

SUMMARY

The design, implementation, and results presented in

this report indicate that the charge pump frequency to

voltage converter offers a solution to various FVC

applications.

The small DC errors in the test results are due to the

0.013% tolerance error as calculated in the Analysis

section, and from the looser tolerance components used in

the lab circuit.

The circuit works as required for the speed monitoring

of ship engines. Using the high reliability components

with tight temperature coefficients on a printed circuit

board with conformal coating, the design is assured through

the environment specified also.

29

APPENDIX A

LIST OF REFERENCES

[1] Milton Kaufman and Arthur H.Seidman, Handbook of Electronics Calculations. (New York: McGraw-Hill, 1979), p 2/3-2/15.

[2] F. Mazda, ed., Electronics En~ineer's Reference Book. (Boston: Butterworth & Co., 198 ), p 13/4-13/7.

[3] F. Mazda, ed., Electronics En~ineer's Reference Book. (Boston: Butterworth & Co., 198 ), p 5/12-5/13.

[4] E.M. Kashoro, A Wideband Freguency-to-Volta1e Converter. (Louisville, KY.: University of Louisvi le, 1985), p 1-4.

(5) Wesley Grenlund, Remove F/V-converter ripple. (EDN February 20, 1979), p 157.

[6] Robert A. Pease, V/F-Converter ICs Handle Frequency-To-Voltage Needs. (EDN March 20, 1979), p 109-116.

Other Sources Consulted

Engineering Staff of Analog Devices. Nonlinear Circuits Handbook (desi nin with analo function modules an IC's . Norwoo, Mass.: Ana og Devices, Inc. 1976 2nd ed.

Engineering staff of Intersil. Data Ac§uisition Handbook. Cupertino, ca.: Intersil Inc., 19 0.

Halkias, Christos c. Ph.D. and Millman, Jacob PH.D. Inte rated Electronics (analo and di ital circuits an systems . New Yor : McGraw-Hi Inc.,

Pease, Robert. "Application Note 210." In Linear Applications Handbook 1980. Santa Clara, ca.: National Semiconductor, 1979.

30

Terry, Fran. "Linear Brief 45." In Linear Applications Handbook 1980. Santa Clara, Ca.: National Semiconductor, 1979.

31