3. Basic building blocks

Analog Design for CMOS VLSI Systems

Franco Maloberti

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks1

Inverter with active loadIt is the simplest gain stage. The dc gain is given by theslope of the transfer characteristics.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks2

Small signal analysis

At low frequency:

€

C1 = Cgs1 + Cgs1,ov

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C2 = Cgd1 + Cgd1,ov

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C3 = Cdb1 + Cdb2

+

+ Cgd2 + Cgd 2,ov + CL

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Av =Vout

Vin

=−gm1

gds1 + gds2

€

gm = 2µCox

WL

ID

€

gds = λID

€

Av = −

2µCox

WL

1

λn + λp( ) ID

with

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks3

The dc gain increases as the square root of the biascurrent is decreases. This holds until the devices enter thesubthreshold region

In subthreshold the dc gain becomes independent of thebiasing current:

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gm =ID

nkTq

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Av = −1

λn + λp( )n kTq

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks4

At high frequency: Miller's theorem is applied to C2

The output total capacitance is C2 + C3 The output resistance is 1 / (gds1 + gds2) The transfer function has one pole

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ωp =gds1 + gds2

C2 + C3

=λn + λp( )IDC2 + C3

The unity gain frequency increases as the square root ofthe bias current.

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fT =1

2πωp Av (0) =

12π

gm1

C2 + C3

=1

2π

2µ1Cox

WL

C2 + C3

ID

Due to the Miller's theorem the input capacitancebecomes: Cin = C1 + C2(1 – Av), if |Av| >> 1 it can be asignificant load for the stage driving it.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks5

Example

Simulate an inverter with active load (VDD = 5 V) as thefollowing figure with BSIM3 Models. Find the dc gain andunity gain frequency.

The achieved gain is about 47 dB, the unity gain frequency is around500 MHz, and the phase margin is 87 degrees.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks6

CascodeThe cascode gain stage is used to attenuate the Millereffect on node 1.

The bias voltage VB keepsM1 in the saturation region.

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VB > Vsat,1 +VGS2 = Vsat,1 +VTh,n +Vsat,2 =

= VTh,n +I1

2µnCox

WL

1

+I1

2µnCox

WL

2

€

VB < Vout,min −Vsat,2 +VGS2 = Vout,min +VTh,n

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks7

Small signal analysis

For low frequency, neglecting gds1 and gds2:

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C1 = Cgs1 + Cgs1,ov

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C2 = Cgd1 + Cgd1,ov

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C3 = Cgd2 + Cgd2,ov + Cgd 3 + Cgd3,ov + Cdb2 + Cdb3 + CL

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Av =Vout

Vin

= −gm1

gds3

€

gm1vin = −gm2v1 = −gds3vout

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C4 = Cgs2 + Cgs2,ov + Cdb1 + Csb2

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A1 =V1

Vin

= −gm1

gm2

The Miller effect is significantly reduced if gm1 ≈ gm2.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks8

At high frequency:The circuit has two nodes: the output and node 1. The capacitance at the output is C3 The output impedance is 1 / gds3 (neglecting the

impedance at the drain of M2) The capacitance at the node 1 is (C2 + C4) The impedance at the node 1 is 1 / gm2

The pole associated to the output node is:

The pole associated to the node 1 is:

where ζ = 1 + rds3 / rds2

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fp,1 =1

2π

1τ1

=1

2π

gm22 /ζ

gm1(C2 + C4) + gm2C2

€

fp,out =1

2π

1τout

=1

2π gds3

C3

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks9

since gm >> gds, fp,out is dominant.

The gain-bandwidth product is:

This condition can be fulfilledby increasing CL.

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gm1

C3

<gm2 /ζ

(C2 + C4) + C2 gm1 / gm2

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fT = fp,dom Av =1

2π gm1

C3

If a good phase margin is needed, it must be:

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks10

Impedance at the drain of M2

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vx =ix

gds1

+ix + gm2vs2

gds2

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vs2 =ix

gds1

€

rd2 =vx

ix

= rds1 + rds2 1+gm2

gds1

≅ rds1gm2rds2

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks11

Impedance at the node 1,r1:

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vx = rds3ix + rds2(ix −gm2vx )

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rs2 =1

gm2

1+rds3

rds2

=

ζgm2

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks12

Cascode with cascode loadTransconductance gain stages.

The gain is increased by increasing gm or rout.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks13

In the improved version the transconductance of M1 isincreased by the factor:

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IM 4 + IM5

IM 4

VB1 and VB2 must keep M1and M4 out the triode region

VB1 > Vsat,1 + VGS2

VB2 < VDD – Vsat,4 – VGS3

The figure plots the foldedstructure useful if we need torise the voltage of the sourceof M1.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks14

Small signal analysis

The output impedance is (conventional version):

(for the improved and folded version rds1 must be replacedwith rds1 // rds5)

The dc gain is:

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rout =rds1gm2rds2( ) rds4gm3rds3( )rds1gm2rds2 + rds4gm3rds3

The circuit has three nodes:

output node

source of M2

source of M3

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Av = −gm1

rds1gm2rds2( ) rds 4gm3rds3( )rds1gm2rds2 + rds4gm3rds3

≅12

gmrds( )2

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks15

The transfer function will have three poles. The dominantone is the output pole

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fp,out =1

2π

1routCout

€

f2 =1

2π

1r2C2

€

f3 =1

2π

1r3C3

Cout, C2, C3 capacitances incident on nodes 1, 2, 3.

At low frequency:

€

rout =rds1gm2rds2( ) rds4gm3rds3( )rds1gm2rds2 + rds4gm3rds3

€

r2 =1

gm2

1+rds4gm3rds3

rds2

// rds1

€

r3 =1

gm3

1+rds1gm2rds2

rds3

// rds 4

€

rout >> r2, r3

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks16

At high frequency:

€

r2 ≅1

gm2

Output swing:

The output swing is limited by the conditions for which oneof the transistors of the stage is brought out of saturation

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Vout,max = VB2 +VGS3 −Vsat3

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r3 ≅1

gm3

€

Vout,min = VB1 +VGS2 −Vsat2

VB1 and VB2 must keep M1, M4, and M5 out of the trioderegion.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks17

Example

Simulate the folded cascode amplifier, shown in the following figure,with VDD = 3.5 V. Use the BSIM3V2 models to find the gain and thephase from input to output and from input to node 2.

We observe that the gain and the phase plots of the output show a 20dB roll-off with a good phase margin (60 degrees). The low frequencygain is 77 dB and the unity gain frequency is around 80 MHz. Thebehavior of the gain from the input to node 2 is interesting: above thedominant pole, it holds 14 dB, just 2 dB more than the expected valuegm1/gm2. At low freq. goes to 34 dB.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks18

Differential stage

M1, M2 in saturation with (W/L)1 = (W/L)2

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I1 =µCox

2WL

1

VGS1 −VTh( )2

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I2 =µCox

2WL

2

VGS2 −VTh( )2

€

VGS1 = VGS0 +vin

2

€

VGS2 = VGS0 −vin

2

assume:

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks19

The output variable is the differential current:

since the bias current can be expressed as:

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ΔI = I1 − I2 =µCox

2WL

1

vin VGS0 −VTh( )

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ISS = I1 + I2 =µCox

2WL

1

VGS0 −VTh( )2

€

ΔI = vin µCox

WL

1

ISSit results:

€

Δi = vingmfor small signals:

with a common mode signal:

€

iCM =gmvCM

1+ 2gmr1≅

vin

2r1

€

CMRR =idiCM

≅ 2gmri

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks20

Example

Verify the equation

Consider an n-channel differential pair with (W/L)=100 and ISS=100 µA.

The transconductance transfer function is fairly linear over a widerange of the input signal. It starts to saturate only when the input signalapproaches the overdrive voltage of the differential pair (75 mV).

€

ΔI = vin µCox

WL

1

ISS

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks21

Source followerUsed as buffer or as dc-level shifter

at low frequency:

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gds1 + gds2( )vout + gmb1vout −gm1vgs1 = 0

hence:

€

Av =vout

vin

=gm1

gm1 + gds1 + gds2 + gmb1

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks22

If gm1 >> gds1 + gds2 + gmb1 then Av ≈ 1

at high frequency:

where: Cout = CL + Cgd2 + Cgd2ov + Cdb2 + Csb1

C1 = Cgs1 + Cgs1ovThe output impedance is obtained by applying a testsource vx at the output node.

ix = (gds1 + gds2 + gmb1 + gm1) vxhence:

The output is not symmetrical. For n-channel input device

Vout-max = VDD – VGS1 Vout-min = Vsat2

€

rout =1

gm1 + gds1 + gds2 + gmb1

≅1

gm1

€

Av (s) ≅C1

C1 + Cout

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks23

Example

Simulate the large signal behavior and derive the dc small signalvoltage gain. IB = 0.1 mA and VDD = 3.3 V.

The output voltage, practically, follows the input shifted by VGS.However due to the body effect, the value of VGS is not constant; it risesfrom 713 mV to 1.13 V. Therefore the input-output characteristic is not1 but 0.81. The figure shows also the dc gain: its value ranges from0.74 to 0.86 quite well match as theoretical results.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks24

Level shifterEssential for NMOS circuits, useful for CMOS circuits

High-impedance level shift

Low-impedance, or "battery", level shift

High input impedances:

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks25

Body effect neglected

Threshold voltage variation effect (∆VTh ≈ ± 150 mV)

Input and output swing limitation

Level shift threshold-independent:

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ΔV = VGS =2LkW

I +VTh = Vov +VTh

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ΔV =2k

LW

1

I1 − I2( ) − LW

2

I2

(assuming M1 in saturation and neglecting λ)usually ∆V < VTh

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks26

Low Impedance:

It behaves like a voltage source

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ΔV = VDS =2L

kWI +VTh

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ΔV = VGS1 +VGS2 = VTh1 +VTh2 +2LkW

1

I1 +2LkW

2

I2b)

a)

a) rout = 1 / gmb) affected by twicevoltage thresholdvariation

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks27

Improved output stagesSource follower with local feedback:

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ix = gm1 + gds2( )vx + gm4v2

€

Rout =1

gm1 1+ gm4rds3( ) + gds2

€

v2 = gm1rds3vx

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks28

With resistive load, the drop voltage across the outputresistance determines:

VGS1 > VGS3, VGS2 < VGS4, I2 = I1 – Iout

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V12 = VGS3 +VGS4 = VTh,n +VTh,p + I5 2L3

µnW3Cox

+2L4

µpW4Cox

Class AB push-pull:

€

WL

1

= kWL

3

€

WL

2

= kWL

4

With RL = 0VGS1 ≈ VGS3, VGS2 ≈ VGS4, I1 = I2 = kI5

The output conductance isgm = gm1 + gm2

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks29

For a given load I2 → 0; the output conductance becomesgout = gm1

In general an output stage has the following equivalentcircuit:

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Rout = Rout0 1+α1Iout +α2Iout2 +K( )

It determines harmonic distortion.

Analog Design for CMOS VLSI SystemsFranco Maloberti

3. Basic building blocks30

€

Vg1 ≅Vg2

Class AB push-pull with gain stage:

if it is verified the condition:

€

1gm4

+1

gm5

<< rds6