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Session FP 16: Paper 16.6
Fractal Capacitors
Hirad Samavati, Ali Hajimiri, Arvin R. Shahani,
Gitty N. Nasserbakht1, Thomas H. Lee
Stanford University, Stanford, CA
1Texas Instruments, Dallas, TX
Demand for linear capacitors
Area efficiency
Improvement with process scaling
Reduction of bottom-plate capacitance
Motivation
Traditional CapacitorsGate Capacitance:
Junction Capacitance:
High capacitance per unit areaNonlinearRequires DC bias voltageLow breakdown voltageMedium Q
Highly nonlinearRequires DC bias voltageSensitive to process variationsLow QLarge temperature variation
Metal to Metal / Poly Capacitance:LinearHigh QSmall temperature variationLow capacitance per unit area
Fractal Capacitor
3-D representation of a fractal capacitor using a single metal layer.
Quasi fractal geometries can be utilized to increase capacitance per unit area.
Reduction of the Bottom-Plate Capacitance
First Terminal
First Terminal
Substrate
Second Terminal
Second Terminal
Area is smaller.
Some of the field lines terminate on the adjacentplate instead of the substrate.
Scaling
Unlike conventional parallel-plate structures, thecapacitance per unit area increases as the processtechnologies scale.
Other Advantages
Lateral flux capacitors shift the burden of matchingaway from oxide thickness to lithography.
The effect of systematic lithography offset is reduceddue to pseudo-random nature of the structure.
Capacitance density can be traded for lower seriesresistance.
LGFCLayout Generator for Fractal Capacitors
LGFCField
Tech. File
Fractal
User
Layout
Report
CSolver Ls & rs
CAD Tool
Input
Lib.
Fractal Construction: An Example
An Initiator A GeneratorN=8, r=1/4, D=log(N)/log(1/r)=1.5M =4
Choose an “initiator.”
Replace each segment of the initiator by a “generator.”
Continue recursively.
Capacitance Estimation
w: Minimum width of the metal.
s: Minimum spacing between two adjacent strips.
A: Area of the fractal capacitance.
K: Proportionality factor that depends on the family offractals being used.
D: Fractal dimension.
Clateral K A( )D
w s+( )D 1–--------------------------------- t×=
t: Thickness of the metal layers.
Boost Factor vs. Lateral Spacing
0.1110
Minimum horizontal spacing (µm)
0.0
5.0
10.0
15.0
20.0C
tota
l/ C
para
llel
D=1.8D=1.6
0.6
Fabricatedfractal
2.3
Vertical metal spacing=0.8 µm
Area=24000 µm2
Metal thickness=0.8 µm
High-frequency two-port measurements
Measurements
108 109 1010
Frequency (Hz)
10-2
10-1
100M
agni
tude
of Y
12 (
siem
ens)
Measurements
Best-Fit RLC Model
+
fres = 3.7 GHz
5.4pF 5.5pF 5.6pFCapacitance
0
1
2
3
4
5
6N
umbe
r of
dic
e
Central sites
Capacitance distribution across the wafer
Measurements
m=5.5pFσ=83fF
σcentral=9.4fF (0.2%)
Measurements
There is a good agreement between the measurements(5.5pF mean) and the simulations (5.4pF).
90% of the measured series inductance is due toconnecting stubs.
About 80% of the series resistance can be attributedto vias and connecting stubs.
Both series resistance and inductance are dominatedby non fundamental mechanisms.
The overall improvement over a standard parallelplate capacitor is a factor of 2.3.