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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
FPGAs for Reconfigurable 5G and Beyond Wireless
Communication
Dr. Milos Milosavljevic Senior Lecturer in Digital Communications and Electronics
www.herts.ac.uk NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Outline
FPGAs for a new paradigm
shift in networks
High-speed back/front-
hauling research
activities at UH
Examples of a few FPGA
developments for high-speed
comms.
Future of FPGAs for 5G
2
NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Centralised baseband processing to serve many hundreds or thousands of remote radios
Front/backhauling capacity will increase significantly
5G will also exploit software defined network (SDN) capabilities resulting in more software centric architecture
5G Needs FPGAs
Source: Lund University
3
NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Next Generation Back- and Front-hauling for 5G
KIT
4
NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Software Definable Transceivers for Future Networks
GTX Transceiver Interface Clock Distribution
SMA SMA SMA
XC6VLX550T
DAC
(2.5, 1Gbps, 14bit)
Embedded Processor DDR3 Memory Interface
Ethernet
SDRAM
DAC
(2.5, 1Gbps, 14bit)
ADC
(2.5Gbps, 8bit)
ADC
(2.5Gbps, 8bit)
TX
RX
Data Flash 100/1000 Eth DDR3 SDRAM
Ethernet SFP Module
SFP Module
• Development board used for fast prototyping new
algorithms
• High speed ADC/DAC provided through the FMC
connectors
• IP Cores development for DSPs
and MAC blocks
• The target is to achieve very fast bidirectional real-time transmission
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
FPGA based Transceivers
6
NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
• All required high performance IP cores have been developed
– FFT / IFFT
– CORDIC
– Equalizer
– Divider
– Correlator
• A synchronization mechanism for the ONUs has been developed
– Implementation of Schmidl & Cox Sync detection
– Local and sampling oscillator are phase locked to OLT oscillators
IP Core Development
Component Max. Frequency LUTs used
ONU – Sync 266.8 MHz 62304 (25% of 380T) ONU - FFT 32 583.0 MHz 18079 (7% of 380T) ONU - RX Total 215.1 MHz 103389 (42% of 380T) ONU - TX Total 231.5 MHz 20917 (8% of 380T) OLT - Sync 360.5 MHz 3433 (0% of 565T) OLT - FFT 256 561.7 MHz 121748 (33% of 565T) OLT - RX Total 360.5 MHz 130070 (36% of 565T) OLT - TX Total 436.5 MHz 115711 (32% of 565T)
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Developed FPGA IP Cores
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Developed FPGA IP Cores (cont.)
Stage 1
64
butterflies
Stage 2
16
butterflies
Stage 3
16
butterflies
Stage 4
16
butterflies
M
U
X
D
E
M
U
X
256
twiddle
factor
mult.
64
twiddle
factor
mult.
64
twiddle
factor
mult.
SINE
LUT
Phase Register
Set Value
+
+90°
SINE
LUT
DAC DAC
NCO
DDS
Sine
Output
Cosine
Output
Complex
Multiplier
Multiplier
Adder
*-1
Complex
Adder
Re & Im
16x 12 bit
CORDICTrigger
FSMACCU
Delay
40 Samples
Delay
120 Samples *-1
*-1
Multiplier
Multiplier
Multiplier
Right
Shift
by 1Adder ACCU
Delay
120 Samples*-1
Sync
Pulse
Phase
Offset
Re & Im
16x 24 bit
16x 24 bit
FFT
Synchronisation
NCO
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
General Board Design
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Complete Testbed with FPGAs
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
VHDL Simulation with ModelSim
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
100Gbit/s Transmission
DAC I
DAC II
90°
FPGA I
FPGA II
Clk
Clk
Register Access
Data
Data
φ
Register AccessReal-Time OFDM
Transmitter
Offline Processing
Re-sample
WindowSync.
FFTPhase Corr.
DecodingAmpl.Corr.
PC
Offline OFDM Receiver Agilent N4391A
EDFA28 GHz
a)
b)
c)
d)
SC 27
SC 51
-3 -1 1 3
-3
-1
1
3
Q
I
-3 -1 1 3
-3
-1
1
3
Q
I
-12 -8 -4 0 4 8 12
1E-5
1E-4
1E-3
0,01
Mag
nit
ud
e [
dB
m]
Frequency [GHz]
0 10 20 30 40 504
6
8
10
12
14
16
18
E
VM
[%
]
Subcarrier
~ 10-3
~ 10-2
Type Parameter
Symbol duration 12.8 ns / 78.125 MHz
Cyclic suffix 1/4
OLT sample rate 25 GS/s
OLT FFT size 256 points
OLT symbol size 320 samples
ONU sample rate 3.125 GS/s
ONU FFT size 32 points
ONU symbol size 40 samples
Symbols per frame 8250
Frame duration 105.6 µs / 9.4697
KHz
KIT
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Dynamic Resource Management on FPGAs
Spec
tral
gr
ou
p 0
…
Spec
tra
l gr
ou
p 1
Spec
tral
gr
ou
p 1
3
Syn
c
Phas
e R
ef.
time
Co
ntr
ol
(a): ACCORDANCE Frame
…
Dataav
aila
ble
su
bca
rrie
rs
ONU 5 ONU 3
ONU 10
ONU 0
ONU 2
ONU 20
ONU 13
………
105.6 μs
Sync-Flags 1
Frame ID and flags 1
Control Data 22
CRC16 2
Message type
ONU ID
1
Message content
1
20
(b): Control Block
Pkt Delimiter4
Pkt Length2
Pkt Type1
Pkt Number1
VC Pkt Pad VC Pkt Pad… …
Header Payload
(c): Virtual Channel (VC)
Eth. Frame Eth. Frame
• Allowing the FPGA modify the IP
cores dynamically depending on the
demand on the network
• Embedded Leon 3 processor
with Linux controls the IP cores
and the MAC unit
• C implementation of dynamic
MAC successfully demonstrated
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
Alternative 5G Fronthauling Solutions
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
FPGAs for Software Defined Networks (SDN)
• The FPGAs at RRH and BBU create CPRI
data which is dynamically compressed
before Ethernet encapsulation takes place
• Different networks topologies and SDN
applications can be programmed using
Mininet within a Linux environment to test
different scenarios.
• NetFPGAs can be used for implementing
OpenFLow Switches providing at least
100Gbps connectivity with Xilinx Virtex-7
690T FPGA N. Zilberman, Y. Audzevich, G. A. Covington, and A. W. Moore, ‘‘NetFPGA
SUME: Toward 100 Gbps as research commodity,’’ IEEE Micro, no. 5, pp. 32–
41, Sep./Oct. 2014.
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NMI FPGA Network: "Safety, Certification & Security“ - 19th May 2016
FPGAs will be used for prototyping 5G
wireless infrastructure over the next few years
With more serial transceivers, DSP slices, block RAMs, DLLs, PCIe interfaces, and other
blocks, the FPGA’s hardware penalty for re-
programmability continues to diminish
It is likely the 5G wireless infrastructure
OEMs will bet on programmability to
reduce design risk and speed time to market
As we look to 2020 for widespread 5G
deployment, it is likely that most OEMs will sell production equipment based on FPGAs and All
Programmable SoCs
The hardware complexity of 5G’s
physical layer is just too challenging to
guarantee that ASIC implementations will
be free of severe hardware bugs
Future of FGPAs for 5G
17