Fpga Hardware

8/18/2019 Fpga Hardware

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Field-programmable gate array

"FPGA" redirects here. It is not to be confused with Flip-chip pin grid array.

A FPGA from Altera

A field-programmable gate array (FPGA) is an integrated circuit designed to be

configured by a customer or a designer after manufacturinghence "field-

programmable". !he FPGA configuration is generally specified using a hardware

description language (#$)% similar to that used for an application-specific integrated

circuit (A&I') (circuit diagrams were preiously used to specify the configuration% as

they were for A&I's% but this is increasingly rare).

'ontemporary FPGAs hae large resources of logic gates and A* bloc+s to

implement comple, digital computations. As FPGA designs employ ery fast Is and

bidirectional data buses it becomes a challenge to erify correct timing of alid data

within setup time and hold time. Floor planning enables resources allocation within

FPGA to meet these time constraints. /01 FPGAs can be used to implement any logical

function that an A&I' could perform. !he ability to update the functionality after

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shipping% partial re-configuration of a portion of the design /21 and the low non-recurring

engineering costs relatie to an A&I' design (notwithstanding the generally higher unit

cost)% offer adantages for many applications./31

FPGA from Xilinx

FPGAs contain programmable logic components called "logic bloc+s"% and a hierarchy

of reconfigurable interconnects that allow the bloc+s to be "wired together"somewhat

li+e many (changeable) logic gates that can be inter-wired in (many) different

configurations. $ogic bloc+s can be configured to perform comple, combinational

functions% or merely simple logic gates li+e A4# and 5. In most FPGAs% the logic

bloc+s also include memory elements% which may be simple flip-flops or more complete

bloc+s of memory./31

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&ome FPGAs hae analog features in addition to digital functions. !he most common

analog feature is programmable slew rate and drie strength on each output pin%

allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring

unacceptably% and to set stronger% faster rates on heaily loaded pins on high-speed

channels that would otherwise run too slowly./61/71 Another relatiely common analog

feature is differential comparators on input pins designed to be connected to differential

signaling channels. A few "mi,ed signal FPGAs" hae integrated peripheral analog-to-

digital conerters (A#'s) and digital-to-analog conerters (#A's) with analog signal

conditioning bloc+s allowing them to operate as a system-on-a-chip.

/81

&uch deices blur

the line between an FPGA% which carries digital ones and 9eros on its internal

programmable interconnect fabric% and field-programmable analog array (FPAA)% which

carries analog alues on its internal programmable interconnect fabric.

Background Study

!he FPGA industry sprouted from programmable read-only memory (P*) and

programmable logic deices (P$#s). P*s and P$#s both had the option of being

programmed in batches in a factory or in the field (field programmable). oweer

programmable logic was hard-wired between logic gates. /:1

In the late 0;arfare #epartment funded an e,periment

proposed by &tee 'asselman to deelop a computer that would implement 8==%===

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reprogrammable gates. 'asselman was successful and a patent related to the system

was issued in 0;;2./:1

&ome of the industry?s foundational concepts and technologies for programmable logic

arrays% gates% and logic bloc+s are founded in patents awarded to #aid >. Page and

$u@erne . Peterson in 0;


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A recent trend has been to ta+e the coarse-grained architectural approach a step further

by combining the logic bloc+s and interconnects of traditional FPGAs with embedded

microprocessors and related peripherals to form a complete "system on a

programmable chip". !his wor+ mirrors the architecture by on Perlof and ana Potash

of urroughs Adanced &ystems Group which combined a reconfigurable 'PC

architecture on a single chip called the &26. !hat wor+ was done in 0;


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FPGA with a separate 'PC chip leads to a lower parts cost% a smaller system% and

higher reliability since most failures in modern electronics occur on P's in the

connections between chips instead of within the chips themseles. /071/081/0:1/0


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• 0;here preiously a

design may hae included 8 to 0= A&I's% the same design can now be achieed using

only one FPGA./231

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A 5ilin, ynD-:=== All Programmable &ystem on a 'hip.

Adantages include the ability to re-program in the field to fi, bugs% and may include a

shorter time to mar+et and lower non-recurring engineering costs. @endors can also

ta+e a middle road by deeloping their hardware on ordinary FPGAs% but manufacture

their final ersion as an A&I' so that it can no longer be modified after the design has

been committed.

5ilin, claims that seeral mar+et and technology dynamics are changing the

A&I'FPGA paradigm

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• Integrated circuit costs are rising aggressiely

• A&I' comple,ity has lengthened deelopment time

• M# resources and headcount are decreasing

• eenue losses for slow time-to-mar+et are increasing

• Financial constraints in a poor economy are driing low-cost technologies

!hese trends ma+e FPGAs a better alternatie than A&I's for a larger number of

higher-olume applications than they hae been historically used for% to which the

company attributes the growing number of FPGA design starts (see istory). /261

&ome FPGAs hae the capability of partial re-configuration that lets one portion of the

deice be re-programmed while other portions continue running.

!omplex programmable logic devices "!P#$%

!he primary differences between 'P$#s (comple, programmable logic deices) and

FPGAs are architectural. A 'P$# has a somewhat restrictie structure consisting of one

or more programmable sum-of-products logic arrays feeding a relatiely small number

of cloc+ed registers. !he result of this is less fle,ibility% with the adantage of more

predictable timing delays and a higher logic-to-interconnect ratio. !he FPGA

architectures% on the other hand% are dominated by interconnect. !his ma+es them far

more fle,ible (in terms of the range of designs that are practical for implementation

within them) but also far more comple, to design for.

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In practice% the distinction between FPGAs and 'P$#s is often one of si9e as FPGAs

are usually much larger in terms of resources than 'P$#s. !ypically only FPGAHs

contain more comple, embedded functions such as adders% multipliers% memory% and

serdes. Another common distinction is that 'P$#s contain embedded flash to store their

configuration while FPGAs usually% but not always% reDuire an e,ternal nonolatile

memory.

Security considerations

>ith respect to security% FPGAs hae both adantages and disadantages as compared

to A&I's or secure microprocessors. FPGAsH fle,ibility ma+es malicious modifications

during fabrication a lower ris+./271 Preiously% for many FPGAs% the design bitstream is

e,posed while the FPGA loads it from e,ternal memory (typically on eery power-on).

All maNor FPGA endors now offer a spectrum of security solutions to designers such as

bitstream encryption and authentication. For e,ample% Altera and 5ilin, offer AE& (up to

278 bit) encryption for bitstreams stored in an e,ternal flash memory.

FPGAs that store their configuration internally in nonolatile flash memory% such as

*icrosemiHs ProAsic 3 or $atticeHs 5P2 programmable deices% do not e,pose the

bitstream and do not need encryption. In addition% flash memory for $C! proides &EC

protection for space applications./clarification needed1

Applications

Applications of FPGAs include digital signal processing% software-defined radio% A&I'

prototyping% medical imaging% computer ision% speech recognition% cryptography%

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bioinformatics% computer hardware emulation% radio astronomy% metal detection and a

growing range of other areas.

FPGAs originally began as competitors to 'P$#s and competed in a similar space% that

of glue logic for P's. As their si9e% capabilities% and speed increased% they began to

ta+e oer larger and larger functions to the state where some are now mar+eted as full

systems on chips (&o'). Particularly with the introduction of dedicated multipliers into

FPGA architectures in the late 0;;=s% applications which had traditionally been the sole

resere of #&Ps began to incorporate FPGAs instead. /281/2:1

!raditionally% FPGAs hae been resered for specific ertical applications where the

olume of production is small. For these low-olume applications% the premium that

companies pay in hardware costs per unit for a programmable chip is more affordable

than the deelopment resources spent on creating an A&I' for a low-olume

application. !oday% new cost and performance dynamics hae broadened the range of

iable applications.

!ommon FPGA Applications&

• Aerospace and #efense

o Aionics#-276

o 'ommunications

o *issiles M *unitions

o &ecure &olutions

http://en.wikipedia.org/wiki/Bioinformaticshttp://en.wikipedia.org/wiki/Hardware_emulationhttp://en.wikipedia.org/wiki/Radio_astronomyhttp://en.wikipedia.org/wiki/Radio_astronomyhttp://en.wikipedia.org/wiki/Radio_astronomyhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/Glue_logichttp://en.wikipedia.org/wiki/Glue_logichttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/System-on-a-chiphttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-26http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-27http://en.wikipedia.org/wiki/Vertical_applicationhttp://en.wikipedia.org/wiki/Bioinformaticshttp://en.wikipedia.org/wiki/Hardware_emulationhttp://en.wikipedia.org/wiki/Radio_astronomyhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/Glue_logichttp://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/System-on-a-chiphttp://en.wikipedia.org/wiki/Digital_signal_processorhttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-26http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-27http://en.wikipedia.org/wiki/Vertical_application


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o &pace

A&I' Prototyping

Audio

o 'onnectiity &olutions

o Portable Electronics

o adio

o #igital &ignal Processing (#&P)

Automotie

o igh esolution @ideo

o Image Processing

o @ehicle 4etwor+ing and 'onnectiity

o Automotie Infotainment

roadcast

o eal-!ime @ideo Engine

o EdgeOA*

o Encoders

o #isplays


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o &witches and outers

'onsumer Electronics

o #igital #isplays

o #igital 'ameras

o *ulti-function Printers

o Portable Electronics

o &et-top o,es

#istributed *onetary &ystems

o !ransaction erification

o it'oin *ining

#ata 'enter

o &erers

o &ecurity

o outers

o &witches

o

Gateways

o $oad alancing

igh Performance 'omputing


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o &erers

o &uper 'omputers

o &IGI4! &ystems

o igh-end A#A&

o igh-end eam Forming &ystems

o #ata *ining &ystems

Industrial

o Industrial Imaging

o Industrial 4etwor+ing

o *otor 'ontrol

*edical

o Cltrasound

o '! &canner

o *I

o 5-ray

o PE!

o &urgical &ystems

&ecurity


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o &ecure &olutions

o Image Processing

@ideo M Image Processing

o igh esolution @ideo

o @ideo er IP Gateway

o #igital #isplays


>ired 'ommunications

o ptical !ransport 4etwor+s

o 4etwor+ Processing

o 'onnectiity Interfaces

>ireless 'ommunications

o aseband

o 'onnectiity Interfaces

o *obile ac+haul

o adio

Arc'itecture


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!he most common FPGA architecture/31 consists of an array of logic bloc+s (called

'onfigurable $ogic loc+% '$% or $ogic Array loc+% $A% depending on endor)% I

pads% and routing channels. Generally% all the routing channels hae the same width

(number of wires). *ultiple I pads may fit into the height of one row or the width of

one column in the array.

An application circuit must be mapped into an FPGA with adeDuate resources. >hile

the number of '$s$As and Is reDuired is easily determined from the design% the

number of routing trac+s needed may ary considerably een among designs with the

same amount of logic. For e,ample% a crossbar switch reDuires much more routing than

a systolic array with the same gate count. &ince unused routing trac+s increase the cost

(and decrease the performance) of the part without proiding any benefit% FPGA

manufacturers try to proide Nust enough trac+s so that most designs that will fit in terms

of $oo+up tables ($C!s) and Is can be routed. !his is determined by estimates such

as those deried from entHs rule or by e,periments with e,isting designs.

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Simplified example illustration of a logic cell

In general% a logic bloc+ ('$ or $A) consists of a few logical cells (called A$*% $E%

&lice etc.). A typical cell consists of a 6-input $C!% a Full adder (FA) and a #-type flip-

flop% as shown below. !he $C!s are in this figure split into two 3-input $C!s. In normal

mode those are combined into a 6-input $C! through the left mu,. In arithmetic mode%

their outputs are fed to the FA. !he selection of mode is programmed into the middle

multiple,er. !he output can be either synchronous or asynchronous% depending on the

programming of the mu, to the right% in the figure e,ample. In practice% entire or parts of

the FA are put as functions into the $C!s in order to sae space. /2


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#ogic block pin locations

&ince cloc+ signals (and often other high-fan-out signals) are normally routed ia

special-purpose dedicated routing networ+s (i.e. global buffers) in commercial FPGAs%

they and other signals are separately managed.

For this e,ample architecture% the locations of the FPGA logic bloc+ pins are shown to

the right.

Each input is accessible from one side of the logic bloc+% while the output pin can

connect to routing wires in both the channel to the right and the channel below the logic

bloc+.

Each logic bloc+ output pin can connect to any of the wiring segments in the channels

adNacent to it.

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&imilarly% an I pad can connect to any one of the wiring segments in the channel

adNacent to it. For e,ample% an I pad at the top of the chip can connect to any of the

> wires (where > is the channel width) in the hori9ontal channel immediately below it.

Generally% the FPGA routing is unsegmented. !hat is% each wiring segment spans only

one logic bloc+ before it terminates in a switch bo,. y turning on some of the

programmable switches within a switch bo,% longer paths can be constructed. For

higher speed interconnect% some FPGA architectures use longer routing lines that span

multiple logic bloc+s.

S(itc' box topology

>heneer a ertical and a hori9ontal channel intersect% there is a switch bo,. In this

architecture% when a wire enters a switch bo,% there are three programmable switches

that allow it to connect to three other wires in adNacent channel segments. !he pattern%

or topology% of switches used in this architecture is the planar or domain-based switch

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bo, topology. In this switch bo, topology% a wire in trac+ number one connects only to

wires in trac+ number one in adNacent channel segments% wires in trac+ number 2

connect only to other wires in trac+ number 2 and so on. !he figure on the right

illustrates the connections in a switch bo,.

*odern FPGA families e,pand upon the aboe capabilities to include higher leel

functionality fi,ed into the silicon. aing these common functions embedded into the

silicon reduces the area reDuired and gies those functions increased speed compared

to building them from primities. E,amples of these include multipliers% generic #&P

bloc+s% embedded processors% high speed I logic and embedded memories.

FPGAs are also widely used for systems alidation including pre-silicon alidation% post-

silicon alidation% and firmware deelopment. !his allows chip companies to alidate

their design before the chip is produced in the factory% reducing the time-to-mar+et.

!o shrin+ the si9e and power consumption of FPGAs% endors such as !abula and 5ilin,

hae introduced new 3# or stac+ed architectures./321/331 Following the introduction of its

2< nm :-series FPGAs% 5ilin, reealed that seeral of the highest-density parts in those

FPGA product lines will be constructed using multiple dies in one pac+age% employing

technology deeloped for 3# construction and stac+ed-die assemblies. !he technology

stac+s seeral (three or four) actie FPGA dice side-by-side on a silicon interposer B a

single piece of silicon that carries passie interconnect. /331/361

FPGA design and programming

http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-32http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-lawrence-33http://en.wikipedia.org/wiki/Interposerhttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-lawrence-33http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-34http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-32http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-lawrence-33http://en.wikipedia.org/wiki/Interposerhttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-lawrence-33http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-34


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!o define the behaior of the FPGA% the user proides a hardware description language

(#$) or a schematic design. !he #$ form is more suited to wor+ with large structures

because itHs possible to Nust specify them numerically rather than haing to draw eery

piece by hand. oweer% schematic entry can allow for easier isualisation of a design.

!hen% using an electronic design automation tool% a technology-mapped netlist is

generated. !he netlist can then be fitted to the actual FPGA architecture using a

process called place-and-route% usually performed by the FPGA companyHs proprietary

place-and-route software. !he user will alidate the map% place and route results ia

timing analysis% simulation% and other erification methodologies. nce the design and

alidation process is complete% the binary file generated (also using the FPGA

companyHs proprietary software) is used to (re)configure the FPGA. !his file is

transferred to the FPGA'P$# ia a serial interface (!AG) or to an e,ternal memory

deice li+e an EEP*.

!he most common #$s are @#$ and @erilog% although in an attempt to reduce the

comple,ity of designing in #$s% which hae been compared to the eDuialent of

assembly languages% there are moes to raise the abstraction leel through the

introduction of alternatie languages. 4ational InstrumentsH $ab@IE> graphical

programming language (sometimes referred to as "G") has an FPGA add-in module

aailable to target and program FPGA hardware.

!o simplify the design of comple, systems in FPGAs% there e,ist libraries of predefined

comple, functions and circuits that hae been tested and optimi9ed to speed up the

design process. !hese predefined circuits are commonly called IP cores% and are

http://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Schematichttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Netlisthttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Timing_analysishttp://en.wikipedia.org/wiki/Simulationhttp://en.wikipedia.org/wiki/Verification_and_validationhttp://en.wikipedia.org/wiki/Serial_communicationhttp://en.wikipedia.org/wiki/Joint_Test_Action_Grouphttp://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/Assembly_languagehttp://en.wikipedia.org/wiki/Hardware_description_language#HDL_and_programming_languageshttp://en.wikipedia.org/wiki/National_Instrumentshttp://en.wikipedia.org/wiki/National_Instrumentshttp://en.wikipedia.org/wiki/LabVIEWhttp://en.wikipedia.org/wiki/Semiconductor_intellectual_property_corehttp://en.wikipedia.org/wiki/Hardware_description_languagehttp://en.wikipedia.org/wiki/Schematichttp://en.wikipedia.org/wiki/Electronic_design_automationhttp://en.wikipedia.org/wiki/Netlisthttp://en.wikipedia.org/wiki/Place_and_routehttp://en.wikipedia.org/wiki/Timing_analysishttp://en.wikipedia.org/wiki/Simulationhttp://en.wikipedia.org/wiki/Verification_and_validationhttp://en.wikipedia.org/wiki/Serial_communicationhttp://en.wikipedia.org/wiki/Joint_Test_Action_Grouphttp://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/Assembly_languagehttp://en.wikipedia.org/wiki/Hardware_description_language#HDL_and_programming_languageshttp://en.wikipedia.org/wiki/National_Instrumentshttp://en.wikipedia.org/wiki/LabVIEWhttp://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core


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aailable from FPGA endors and third-party IP suppliers (rarely free% and typically

released under proprietary licenses). ther predefined circuits are aailable from

deeloper communities such as pen'ores (typically released under free and open

source licenses such as the GP$% or similar license)% and other sources.

In a typical design flow% an FPGA application deeloper will simulate the design at

multiple stages throughout the design process. Initially the !$ description in @#$ or

@erilog is simulated by creating test benches to simulate the system and obsere

results. !hen% after the synthesis engine has mapped the design to a netlist% the netlist

is translated to a gate leel description where simulation is repeated to confirm the

synthesis proceeded without errors. Finally the design is laid out in the FPGA at which

point propagation delays can be added and the simulation run again with these alues

bac+-annotated onto the netlist.

Basic process tec'nology types

• &A* - based on static memory technology. In-system programmable and re-

programmable. eDuires e,ternal boot deices. '*&. 'urrently in use.

• Antifuse - ne-time programmable. '*&.

• P* - Programmable ead-nly *emory technology. ne-time programmable

because of plastic pac+aging. bsolete.

• EP* - Erasable Programmable ead-nly *emory technology. ne-time

programmable but with window% can be erased with ultraiolet (C@) light. '*&.

bsolete.

http://en.wikipedia.org/wiki/OpenCoreshttp://en.wikipedia.org/wiki/Free_and_open_source_softwarehttp://en.wikipedia.org/wiki/Free_and_open_source_softwarehttp://en.wikipedia.org/wiki/GNU_General_Public_Licensehttp://en.wikipedia.org/wiki/BSD_licensehttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_Random_Access_Memoryhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Antifusehttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/OpenCoreshttp://en.wikipedia.org/wiki/Free_and_open_source_softwarehttp://en.wikipedia.org/wiki/Free_and_open_source_softwarehttp://en.wikipedia.org/wiki/GNU_General_Public_Licensehttp://en.wikipedia.org/wiki/BSD_licensehttp://en.wikipedia.org/wiki/Register_transfer_levelhttp://en.wikipedia.org/wiki/VHDLhttp://en.wikipedia.org/wiki/Veriloghttp://en.wikipedia.org/wiki/Logic_synthesishttp://en.wikipedia.org/wiki/Static_Random_Access_Memoryhttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Antifusehttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/EPROM


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• EEP* - Electrically Erasable Programmable ead-nly *emory technology.

'an be erased% een in plastic pac+ages. &ome but not all EEP* deices can

be in-system programmed. '*&.

• Flash - Flash-erase EP* technology. 'an be erased% een in plastic

pac+ages. &ome but not all flash deices can be in-system programmed. Csually%

a flash cell is smaller than an eDuialent EEP* cell and is therefore less

e,pensie to manufacture. '*&.

• Fuse - ne-time programmable. ipolar. bsolete.

Ma)or manufacturers

5ilin, and Altera are the current FPGA mar+et leaders and long-time industry rials. /371

!ogether% they control oer indows and $inu, design software which proides

limited sets of deices.

ther competitors include $attice &emiconductor (&A* based with integrated

configuration flash% instant-on% low power% lie reconfiguration)% Actel (now *icrosemi%

antifuse% flash-based% mi,ed-signal)% &iliconlue !echnologies (e,tremely low power

&A*-based FPGAs with optional integrated nonolatile configuration memoryQ

acDuired by $attice in 2=00)% Achroni, (&A* based% 0.7 G9 fabric speed)% and

Ouic+$ogic (handheld focused '&&P% no general purpose FPGAs).

http://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Fuse_(electrical)http://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Alterahttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-35http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-36http://en.wikipedia.org/wiki/Microsoft_Windowshttp://en.wikipedia.org/wiki/Linuxhttp://en.wikipedia.org/wiki/Lattice_Semiconductorhttp://en.wikipedia.org/wiki/Actelhttp://en.wikipedia.org/wiki/Microsemihttp://en.wikipedia.org/wiki/SiliconBlue_Technologieshttp://en.wikipedia.org/wiki/Achronixhttp://en.wikipedia.org/w/index.php?title=QuickLogic&action=edit&redlink=1http://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Fuse_(electrical)http://en.wikipedia.org/wiki/Xilinxhttp://en.wikipedia.org/wiki/Alterahttp://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-35http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_note-36http://en.wikipedia.org/wiki/Microsoft_Windowshttp://en.wikipedia.org/wiki/Linuxhttp://en.wikipedia.org/wiki/Lattice_Semiconductorhttp://en.wikipedia.org/wiki/Actelhttp://en.wikipedia.org/wiki/Microsemihttp://en.wikipedia.org/wiki/SiliconBlue_Technologieshttp://en.wikipedia.org/wiki/Achronixhttp://en.wikipedia.org/w/index.php?title=QuickLogic&action=edit&redlink=1


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In *arch 2=0=% !abula announced their FPGA technology that uses time-multiple,ed

logic and interconnect that claims potential cost saings for high-density applications.

Field-programmable gate arrays (FPGAs) arried in 0;


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the interconnect scheme. In turn% the logic cells and interconnection scheme determine

the design of the input and output circuits as well as the programming scheme.

FPGAs offer all of the features needed to implement most comple, designs.

'loc+ management is facilitated by on-chip P$$ (phase-loc+ed loop) or #$$ (delay-

loc+ed loop) circuitry. #edicated memory bloc+s can be configured as basic single-port

A*s% *s% FIFs% or 'A*s. #ata processing% as embodied in the deices? logic

fabric% aries widely. !he ability to lin+ the FPGA with bac+planes% high-speed buses%

and memories is afforded by support for arious single ended and differential I

standards. Also found on today?s FPGAs are system-building resources such as high

speed serial Is% arithmetic modules% embedded processors% and large amounts of

memory.


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FPGA *+,

!he highest capacity general purpose logic chips aailable today are the

traditional gate arrays sometimes referred to as *as+-Programmable Gate Arrays

(*PGAs). *PGAs consist of an array of pre-fabricated transistors that can be

customi9ed into the user?s logic circuit by connecting the transistors with custom wires.

'ustomi9ation is performed during chip fabrication by specifying the metal interconnect%

and this means that in order for a user to employ an *PGA a large setup cost is


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inoled and manufacturing time is long. Although *PGAs are clearly not FP#s% they

are mentioned here because they motiated the design of the user-programmable

eDuialent Field-Programmable Gate Arrays (FPGAs). $i+e *PGAs% FPGAs comprise

an array of uncommitted circuit elements% called logic bloc+s% and interconnect

resources% but FPGA configuration is performed through programming by the end user.

An illustration of a typical FPGA architecture appears below figure. As the only type of

FP# that supports ery high logic capacity% FPGAs hae been responsible for a maNor

shift in the way digital circuits are designed.


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!ommercially Available FPGAs&

As one of the largest growing segments of the semiconductor industry%

the FPGA mar+et-place is olatile. As such% the pool of companies inoled changes

rapidly and it is somewhat difficult to say which products will be the most significant

when the industry reaches a stable state. For this reason% and to proide a more

focused discussion% we will not mention all of the FPGA manufacturers that currently

e,ist% but will instead focus on those companies whose products are in widespread use

at this time. In describing each deice we will list its capacity% nominally in 2-input 4A4#

gates as gien by the endor. Gate count is an especially contentious issue in the FPGA

industry% and so the numbers gien in this paper for all manufacturers should not be

ta+en too seriously. >ags hae ta+en to calling them RdogS gates% in reference to the

traditional ratio between human and dog years.

!here are two basic categories of FPGAs on the mar+et today

0. &A*-based FPGAs and

2. antifuse-based FPGAs.

In the first category% 5ilin, and Altera are the leading manufacturers in terms of number

of users% with the maNor competitor being A!M!. For antifuse-based products% Actel%

Ouic+logic and 'ypress% and 5ilin, competing offer products.


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SAM based FPGA&

!he basic structure of 5ilin, FPGAs is array-based% meaning that each chip

comprises a two dimensional array of logic bloc+s that can be interconnected ia

hori9ontal and ertical routing channels.

Spartan ./ family&

!he &partanT-3E family of Field-Programmable Gate Arrays (FPGAs) is

specifically designed to meet the needs of high olume% cost-sensitie consumer

electronic applications. !he fie-member family offers densities ranging from 0==%=== to

0.8 million system gates. !he &partan-3E family builds on the success of the earlier

&partan-3 family by increasing the amount of logic per I% significantly reducing the

cost per logic cell. 4ew features improe system performance and reduce the cost of

configuration. !hese &partan-3E FPGA enhancements% combined with adanced ;= nm

process technology% delier more functionality and bandwidth per dollar than was

preiously possible% setting new standards in the programmable logic industry. ecause

of their e,ceptionally low cost% &partan-3E FPGAs are ideally suited to a wide range of

consumer electronics applications% including broadband access% home networ+ing%

displayproNection% and digital teleision eDuipment. !he &partan-3E family is a superior

alternatie to mas+ programmed A&I's. FPGAs aoid the high initial cost% the lengthy

deelopment cycles% and the inherent infle,ibility of conentional A&I's. Also% FPGA


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programmability permits design upgrades in the field with no hardware replacement

necessary% an impossibility with A&I's.

Features&

U @ery low cost% high-performance logic solution for high-olume% consumer-oriented

applications.

U Proen adanced ;=-nanometer process technology

U *ulti-oltage% multi-standard &elect I interface pins

- Cp to 3:8 I pins or 078 differential signal pairs

- $@'*&% $@!!$% &!$% and &&!$ single-ended


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Arc'itectural 0vervie(&

Spartan ./ Arc'itecture&

!he &partan-3E family architecture consists of fie fundamental programmable

functional elements


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U 'onfigurable $ogic loc+s ('$s) contain fle,ible $oo+-Cp !ables ($C!s) that

implement logic plus storage elements used as flip-flops or latches. '$s perform a

wide ariety of logical functions as well as store data.

U Inputoutput loc+s (Is) control the flow of data between the I pins and the

internal logic of the deice. Each I supports bidirectional data flow plus 3-state

operation. &upports a ariety of signal standards% including four high-performance

differential standards. #ouble #ata-ate (##) registers are included.

U loc+ A* proides data storage in the form of 0

Documents

Fpga Hardware