FPGA-Based Speed Control IC for PMSM

2476 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 6, NOVEMBER 2007

FPGA-Based Speed Control IC for PMSMDrive With Adaptive Fuzzy Control

Ying-Shieh Kung, Member, IEEE, and Ming-Hung Tsai

Abstract—The new generation of field programmable gatearray (FPGA) technologies enables an embedded processor intel-lectual property (IP) and an application IP to be integrated into asystem-on-a-programmable-chip (SoPC) developing environment.Therefore, this study presents a speed control integrated circuit(IC) for permanent magnet synchronous motor (PMSM) driveunder this SoPC environment. First, the mathematic model ofPMSM is defined and the vector control used in the current loopof PMSM drive is explained. Then, an adaptive fuzzy controlleradopted to cope with the dynamic uncertainty and external loadeffect in the speed loop of PMSM drive is proposed. After that, anFPGA-based speed control IC is designed to realize the controllers.The proposed speed control IC has two IPs, a Nios II embeddedprocessor IP and an application IP. The Nios II processor isused to develop the adaptive fuzzy controller in software due tothe complicated control algorithm and low sampling frequencycontrol (speed control: 2 kHz). The designed application IP isutilized to implement the current vector controller in hardwareowing to the requirement for high sampling frequency control(current loop: 16 kHz, pulsewidth modulation circuit: 4–8 MHz)but simple computation. Finally, an experimental system is set upand some experimental results are demonstrated.

Index Terms—Field programmable gate arrays (FPGAs), fuzzycontrol, permanent magnet motors, synchronous motor drives,system-on-a-programmable-chip (SoPC).

I. INTRODUCTION

OWING to the advantages of the superior power density,high performance in motion control—fast response

and better accuracy, permanent magnet synchronous motors(PMSM) have used in many automation control fields as anactuators [1]. But in industrial applications, there are many un-certainties, such as system parameter uncertainty, external loaddisturbance, friction force, unmodeled uncertainty, etc. whichalways diminish the performance quality of the pre-design ofthe motor driving system. To cope with this problem, in recentyears, many intelligent control techniques [2]–[5], such asfuzzy control, neural networks control, adaptive fuzzy controland other control method, have been developed and applied tothe speed control of servo motor drives to obtain high operatingperformance. A high-performance motor control system should

Manuscript received September 7, 2006; revised February 18, 2007. Recom-mended for publication by Associate Editor A. Emadi.

Y.-S. Kung is with the Department of Electrical Engineering, SouthernTaiwan University, Tainan 710, Taiwan, R.O.C. (e-mail: [email protected]).

M.-H. Tsai is with the Institute of Mechatronic Science and Technology,Southern Taiwan University, Tainan 710, Taiwan, R.O.C. (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2007.909185

have a fast dynamic response to adjustments in its controlparameters, so that the motor outputs that influenced by the dis-turbances can recover to their original status as soon as possible[6]. However, the execution of a neural network or adaptivefuzzy control requires many computations, so implementationof these highly complex control algorithms depend on the PCsystems in most studies [3], [7]. In recent years, the fixed-pointdigital signal processor (DSP) and field programmable gatearray (FPGA) also provide a possible solution in this issue[8], [9]. Comparing with FPGA, although the aforementionedintelligent control technique using DSP provides a flexibleskill, it suffers from a long period of development and exhaustsmany resources of the CPU [9].

Nowadays, due to the progress of VLSI technology, theFPGA has brought more attention before. The advantages ofthe FPGA include their programmable hard-wired feature, fasttime-to-market, shorter design cycle, embedding processor,low power consumption and higher density for the implemen-tation of the digital system [10]. FPGA provides a compromisebetween the special-purpose application specified integratedcircuit (ASIC) hardware and general-purpose processors [11].Hence, many practical applications in inverter [12], [13] andmotor control [9], [14]–[17] have been studied. Tzou [12]and Zhou [13], respectively, gave an FPGA realization of thespace-vector pulsewidth modulation (PWM) for three-phaseinverters. Zhou [9] proposed an FPGA-realization of a speedservo controller of PMSM. A PI controller was adopted in speedloop of PMSM drive. Takshashi [14] utilized an FPGA to im-plement a complete ac servo controller. An application specificstandard product (ASSP) created to reduce the gate count wasconsidered in this study. Fang [16] adopted an FPGA-basedchip to design the conceptual core of sliding mode controlstrategy for PMSM. Lin [17] presented a fuzzy sliding-modecontrol for a linear induction motor drive based on FPGA. Thefuzzy sliding-mode controller with fuzzy inference mechanismto adapt the system uncertainty in real-time is proposed inthis paper. However, the above researches studied the servocontrol system of inverter or ac motor only by FPGA hardwareimplementation with the simple computation algorithm.

Embedded processor IP and application IP can nowbe developed and downloaded into FPGA to constructa system-on-a-programmable-chip (SoPC) environment[18]–[20], allowing the user to design a SoPC module bymixing hardware and software in one FPGA chip. The circuitsrequired with fast processing but simple computation aresuitable to be implemented by hardware in FPGA, and thehighly complicated control algorithm with heavy computation

0885-8993/$25.00 © 2007 IEEE

KUNG AND TSAI: FPGA-BASED SPEED CONTROL IC 2477

Fig. 1. Internal architecture of FPGA-based speed control IC for PMSM drive.

can be realized by software in FPGA. With the results ofthe software/hardware co-design function increase the pro-grammable, flexibility of the designed digital system, reducethe development time and enhance the system performance.Our previous works [21]–[23] have successfully applied theSoPC technology to the servo system of PMSM drive, robotarm, and – table.

To exploit the advantages, this study presents a fully digitalspeed control integrated circuit (IC) for PMSM drive based onthe new-generation FPGA technology, as in Fig. 1. The pro-posed motion control IC has two IPs, a Nios II embedded pro-cessor IP and an application IP. The Nios embedded processorIP is adopted to implement the adaptive fuzzy control functionsusing software, and the application IP is used to realize the cur-rent vector control with hardware. Besides, a finite state machine(FSM) method is also considered to reduce the logic elements(LEs) usage of FPGA in this paper. Hence, all functionalities,which are based on software/hardware co-design, required tobuild a fully digital servo control for PMSM drive can be in-tegrated in one FPGA chip. The FPGA chip employed hereinis an Altera Cyclone EP1C20 with 20 060 LEs, maximum 301user I/O pins, 294 912 b of RAM, and a Nios II embedded pro-cessor. The processor has a 32-b configurable CPU core, 16 Mbyte Flash memory, 1 M byte SRAM and 16 M byte SDRAM.Finally, an experimental system included by an FPGA experi-mental board, an inverter and a PMSM, is set up to verify thecorrectness and effectiveness of the FPGA-based speed controlIC.

II. SYSTEM DESCRIPTION OF PMSM DRIVE

AND ITS DESIGN METHODOLOGY

The internal architecture of the proposed FPGA-based servosystem for the PMSM drive is shown in Fig. 1. The adaptivefuzzy control in the speed loop is developed in software usingthe Nios II embedded processor. The current vector control

scheme for PMSM is implemented by hardware in FPGA. Thedetailed theoretical description follows.

A. Mathematical Model of PMSM

The mathematical model of a typical PMSM is described, intwo-axis - synchronous rotating reference frame, as follows[1]:

(1)

(2)

where are the and axis voltages; are the andaxis currents, is the phase winding resistance; are the

and axis inductance; is the electrical angular speed;is the permanent magnet flux linkage. The current control of aPMSM drive is based on vector control approach, such that ifis controlled to 0 in Fig. 1, the PMSM is decoupled. Therefore,the developed electromagnetic torque can be simplified to [1]

(3)

with

(4)

Considering the mechanical load, the dynamic equation ofPMSM can be written as follows [1]:

(5)

where and are the number of polepairs, the rotor speed, the motor toque, the torque constant, theinertial value, the damping ratio and the load toque, respectively.


Fig. 2. Block diagram of internal circuit of an FPGA-based speed control IC.

The dashed rectangular area of Fig. 1 shows the configurationof the current loop of the PMSM drive, including two PI con-trollers, coordinate transformations of Clark, Modified inverseClark, Park, inverse Park, SVPWM, pulse signal detection of theencoder and other element. Vector control (with set to zero inFig. 1) in the current loop of the PMSM drive, decouples thenonlinear and coupled characteristics of PMSM. Accordingly,controlling the torque of PMSM is only need to control the cur-rent in the direction of -axis. The formulations about the trans-formations among the stationary frame, the stationary

- frame and the synchronously rotating frame in Fig. 1refer to [5].

In Fig. 1, two digital PI controllers are presented in the currentloop of PMSM and the formulations are as follows:

(6)

(7)

(8)

(9)

where represents axis or axis and is the error be-tween current command and measured current. Thoseare P controller gain and I controller gain, respectively. The

are the output of P controller only, I con-troller only and the PI controller, respectively.

Fig. 3. Main program and ISR for adaptive fuzzy control in Nios II processor.

B. Adaptive Fuzzy Controller in Speed Control Loop

The solid rectangular area in Fig. 1 presents the structure ofan adaptive fuzzy controller for PMSM drive. It consists of afuzzy controller, a reference model and an adjusting mechanism.Detailed description is as follows.

1) Fuzzy Controller: Generally speaking, P controller inseries connection with fuzzy system belongs to a PD typefuzzy controller, but PI controller in series connection withfuzzy system belongs to a PID type fuzzy controller whichis adopted in our proposed system in Fig. 1. The latter one


Fig. 4. Designed CCCT circuit in Fig. 2 by using parallel processing method.

has more flexible and less steady state error than the formerone. The fuzzy controller in this study uses singleton fuzzifier,triangular membership function, product-inference rule andcentral average defuzzifier method [24]. In Fig. 1, the trackingerror and the error change are defined by

(10)

(11)

and represents the output of the fuzzy controller. The isthe output of the reference model. The design procedure of thefuzzy controller is as follows.

1) Take and as the input and output vari-able of fuzzy controller, and define their linguist values as

based on the symmetrical triangular member-ship function

when (12)

where is the input value; is the output value;are mean and width of the triangular function;are the gains of error and error change.

2) Select the initial fuzzy control rules by referring to the dy-namic response characteristics [4], such as

IF is and is THEN is

(13)

There are seven fuzzy sets for each linguist valueand 49 fuzzy control rules are designed

for the two inputs and one output fuzzy system. Therefore,is 49 in (13).

3) Construct the fuzzy system, , by using the sin-gleton fuzzifier, product-inference rule, and central averagedefuzzifier method. Therefore, (13) is replaced with thefollowing expression: [25]

(14)

The are adjustable parameters. In imple-mentation, the adjustable ranges for each parameter islimited between and .

2) Reference Model: Second order system is taken as thereference model in adaptive fuzzy controller in Fig. 1, and itcan be expressed as

(15)

where is natural frequency and is damping ratio.


Fig. 5. Designed CCCT circuit in Fig. 2 by using FSM method.

Applying the bilinear transformation, the continuous modelin (15) can be transformed to a discrete model by

(16)

the is back shift operator and and are theparameters of the discrete model. Furthermore, the differenceequation is written as

(17)

3) Parameter Adjusting Mechanism: The gradient descentmethod is used to derive the fuzzy control law in Fig. 1. The pri-mary purpose of adjusting the parameters of the fuzzy controlleris to minimize the square error (instantaneous cost function) be-tween the rotor speed and the output of the reference model. Theinstantaneous cost function is defined by

(18)

and the parameters of are adjusted according to

(19)

where represents learning rate. The formulations for the ad-justment of the parameters of the fuzzy controller are derived,by initially, assume to be zero in (5), and taking Laplacetransformation of (3) and (5)

(20)

Next, the bilinear transformation is used to derive the followingdifference equation of PMSM drive system

(21)

where is a back-shift operator and is the sampling period.Additionally, in Fig. 1, the current command, is formulatedby the output of fuzzy controller,

(22)

and where are the PI controller gains, and is theoutput of the controller. From (21) and (22)

(23)


with . The chainrule is used to rewrite, the partial differential equation for

in (18) can be rewritten as

(24)

From (14) and (23), we can get

(25)

and

(26)

Therefore, (25) and (26) are substituted into (24) and (19), andthen the parameters of fuzzy controller described by (14) canbe adjusted using the following expression:

(27)

Because the motor parameter is not easily to determined, sothe is used in (27). It is unity because is positive. The

represents the sign operator.

C. Proposed FPGA-Based Control IC for PMSM Drive

Fig. 2 illustrates the internal architecture of the proposedFPGA-based speed control IC for PMSM drive. The speedcontrol IC, which comprises a Nios II embedded processor IPand an application IP, is designed based on a SoPC technology,which is developed by Altera Cooperation. The FPGA chipadopted herein is a Cyclone EP1C20, which has 20 060 LEs,maximum 301 user I/O pins and total 294 912 b of RAM.The Nios II embedded processor has a 32-b configurable CPUcore, 16 M byte Flash memory, 1 M byte SRAM and 16 Mbyte SDRAM. A custom software development kit (SDK)consists of a compiled library of software routines for the SoPCdesign, a Make-file for rebuilding the library, and C header filescontaining structures for each peripheral.

The Nios II processor IP depicted in Fig. 2 performs the func-tion of an adaptive fuzzy control in speed loop of PMSM drivein software. The clock frequency of the Nios II processor is50 MHz. Fig. 3 illustrates the flow charts of the main programand the interrupt service routine (ISR) for adaptive fuzzy con-trol, where the interrupt interval is designed with 500 s. Allprograms are coded in the C programming language in Fig. 3.Then, through the complier and linker operation in the Nios IIIntegrated Development Environment (IDE), the execution codeis produced and can be downloaded to the external Flash orSDRAM via JTAG interface. Finally, this execution code canbe read by Nios II processor IP via bus interface in Fig. 2. Thecomputation time in Nios II processor for executing the adap-tive fuzzy control algorithm in speed loop is 120 s. Using theC language to develop the control algorithm not only has theportable merit but also is easier to transfer the mature code,

Fig. 6. (a) Circuit of SVPWM generation and (b) circuit of QEP detection andtransformation.

which has been well-developed in other devices such as DSPdevice or PC-based system, to the Nios II processor.

The application IP implemented by hardware, as depicted inFig. 2, is adopted to realize the current vector control of PMSMdrive. In addition, its circuits include frequency divider, currentcontrollers and coordinate transformation (CCCT), SVPWMgeneration, QEP detection and transformation, ADC read inand transformation, etc. The sampling frequency of currentcontrol is designed with 16 kHz. The operating clock rate of thedesigned FPGA controller is 50 MHz and the frequency dividergenerates 50 Mhz (Clk), 25 MHz (Clk-sp) and 16 kHz (Clk-ctr)clock to supply all module circuits of application IP in Fig. 2.The internal circuit of CCCT in Fig. 2 performs the function oftwo PI controllers, table look-up for function and thecoordinate transformation for Clark, Park, inverse Park, modi-fied inverse Clarke. However, these formulations have a heavycomputational load. Herein, two kinds of design method thatone is parallel processing method and the other is finite statemachine (FSM) method are introduced to realize the CCCTcircuit. In the former method, the designed CCCT circuit isshown in Fig. 4, that the circuits of -axis PI controller, -axisPI controller, Clarke, Park, inverse Park, modified inverseClarke, and table look-up for function, will operatecontinuously and simultaneously. In Fig. 4, the data type is 12-blength with Q11 format and 2’s complement operation. Eachcircuit of PI controller includes three adders, two multipliersand two D-type flip-flops. The circuit of Park or inverse Parktransformation also needs two adders and four multipliers.Under this designed methodology, the resource usage of CCCTcircuit needs 3 659 Logic Elements (LEs) and 24 576 RAM bitsand it is shown in the gray-filled part of Table I(a). Althoughthe parallel processing method has fast computation ability, itconsumes much more FPGA resources. To reduce the resource


TABLE IUTILITY EVALUATION OF SPEED CONTROL IC FOR PMSM DRIVE IN FPGA FOR

THE DESIGNED CCCT CIRCUIT IN FIG. 2 BY USING (a) PARALLEL

PROCESSING METHOD and (b) FSM METHOD

usage in FPGA, the designed CCCT circuit adopted by usingthe FSM method is proposed and shown in Fig. 5, which usesone adder, one multiplier, an 1-b left shifter, a look-up-tableand manipulates 23 steps machine to carry out the overallcomputation of CCCT in Fig. 2. The data type in Fig. 5 is 12-blength and Q11 format. In Fig. 5, steps s0–s1 is for the look-up

table; steps s2–s4 and s5–s7 are for the computation ofd-axis and q-axis PI controller, respectively; and steps s8–s12,s13–s16, s16–s18 and s19–s23 represent the transformationof inverse Park, modified inverse Clarke, Clarke, and Park,respectively. In Fig. 5, the operation of each step in FPGAcan be completed within 40 ns (25 MHz clock); thereforetotal 23 steps need 0.92 s operation time. Although the FSMmethod needs more operation time than the parallel processingmethod in executing CCCT circuit, it doesn’t loss any controlperformance at overall system because the 0.92 s operationtime is much less than the designed sampling interval, 62.5 s(16 kHz) of current control loop in Fig. 2. Furthermore, fromthe gray-filled part of Table I(b), it is shown that the resourceusage of CCCT circuit designed by the FSM method is 864 LEsand 24 576 RAM b; therefore, the FSM method, comparingwith the parallel processing method, spends only 1/4 timesresource usages (LEs) in FPGA. With exception of the CCCTcircuit in Fig. 2, others circuit design like SVPWM and QEPare presented in Fig. 6(a) and (b), respectively. The SVPWMcircuit herein is designed to be 16 kHz frequency and 1 s

Fig. 7. (a) Experimental system for SVPWM generation, (b) experiment resultwithout load connection, and (c) experiment result with RC circuit connection.

dead-band. Related design method of SVPWM circuit in FPGArefers to [12].

Finally, the FPGA utility of the speed control IC in Fig. 2is evaluated and the result is listed in Table I. The resourceusage of the controller architecture, where the CCCT circuit isadopted by the FSM method in Fig. 2, is presented in Table I(b),which shows that the overall circuits of the proposed speed con-trol IC included a Nios II embedded processor IP (3 440 LEsand 49 920 RAM b) and an application IP (2 335 LEs and24 576 RAM b), use 28.7% LEs resource and 25.3% RAMresource of Cyclone EP1C20. Compared with Table I(a), theproposed FSM method in Table I(b) economizes the use of2 795 LEs in the overall circuits.

III. EXPERIMENTS AND RESULTS

The overall experimental system is depicted in Fig. 1, and itincludes an FPGA (Cyclone EP1C20), a voltage source insu-lated gate bipolar transistor (IGBT) inverter and a PMSM. Thepower of the PMSM is 2200 W, the rating speed is 2000 rpm, andthe torque magnitude of the brake is adjustable in the range of0.2 to 3 N*m. The parameters of the motor as stator resistance

, stator inductance , torque constant and rated


Fig. 8. (a) Three phase waveforms (b) i ; i and i ; i response in currentcontrol loop.

stator current are 0.63 , 2.77 mH, 1.1 Kg-m/A and 12 A, re-spectively. An incremental optical encoder (2 500 ppr) attachedto PMSM is used as the rotor’s position sensor. The inverter hassix sets of IGBT type power transistors. The collector-emittervoltage of the IGBT is rating 600 V, the gate-emitter voltage israting 20 V, and the collector current in dc is rating 25 A andin short time (1 ms) is 50 A. The photo-IC, Toshiba TLP250,is used for gate driving circuit of IGBT. Input signals of the in-verter are PWM signals from FPGA device. For the implement,the PWM switching frequency of inverter, dead-band and thecontrol sampling frequency of current and speed loop are de-signed to 16 kHz, 1 s, 16 kHz, and 2 kHz, respectively. In theproposed FPGA-based speed control IC, the current controlleris implemented by using PLD hardware and the adaptive fuzzyspeed controller is realized by using software in the Nios II em-bedded processor. The fuzzy controller in this study uses sin-gleton fuzzifier, triangular membership function, product-infer-ence rule and central average defuzzifier method. The parameteradjustment mechanism is based on the gradient descent method.The transfer function of the reference model in Fig. 1 is chosenby a second order system with the natural frequency of 50 rad/sand the damping ratio of 1. After applying the bilinear transfor-mation with sampling frequency by 2 kHz, the parameters of dif-ference equation in (17) are obtained by 0.0001520.000306 0.000152 1. 950617 0.951227.

To verify the correctness of SVPWM generation function inFig. 1, an experimental block diagram is constructed in Fig. 7(a).The input signal is set to a constant voltage and the is setto zero in Fig. 7(a), then PWM1–PWM6 outputs can be gen-erated through the transformation of inverse Park, modified in-verse Clarke and SVPWM. When the experimental system is

Fig. 9. Step response of rotor speed and control effort operated at1200–1500 rpm square wave command and 0.2 N*m load torque undercase of: (a) without adaptation, (b) with adaptation by learning rate 0.05,(c) with adaptation by learning rate 0.1.

without load connection, PWM1 and PWM2 signals are mea-sured and show the results of 16 kHz switching frequency and1 s dead-band in Fig. 7(b). When the experimental system isserially connected to a RC circuit with 10 resistor and 47 fcapacitor, the results show the measured PWM1 and PWM3 as asaddle waveform in Fig. 7(c). Furthermore, to validate the effec-tiveness of the current vector control in Fig. 1, the input currentcommand, is set, and the measured currentsof and corresponding currents in - - axes are shown in


Fig. 10. Step response of rotor speed and control effort operated at 0–300 rpmsquare wave command and 1.2 N*m load torque under case of (a) without adap-tation, (b) with adaptation by learning rate 0.05, and (c) with adaptation bylearning rate 0.1.

Fig. 8. The load torque of brake is set to 2 N*m. In Fig. 8, the re-sults present that the measured current tracks current commandperfectly. The experimental results validate the success of cur-rent vector control, and will make the PMSM decouple.

Having confirmed the effectiveness of the current vectorcontrol, the dynamic performance of PMSM drive is evaluatedwhile the adaptive fuzzy controller is applied in speed control

Fig. 11. Frequency response of a 2 Hz sinusoid input signal with 1.0 N*m loadtorque under using the (a) fuzzy controller and (b) adaptive fuzzy controller.

loop of Fig. 1. The step response under two tested cases is firstevaluated. The first case is motor running at the light-load con-dition that the amplitude of speed command is 1200–1500 rpmsquare wave and the external load torque is 0.2 N*m. Thesecond case is motor running at the heavy-load condition thatthe amplitude of speed command is 0–300 rpm square waveand the external load torque is 1.2 N*m. In addition, the per-formance of using different control laws by PI controller only,PID type fuzzy controller and the proposed adaptive fuzzycontroller are compared. At the light-load condition, when thePI controller (PI gains: 0.61 and 0.015) is onlyused in the speed loop of Fig. 1, the step response is shownin Fig. 9(a). It reveals a bad tracking result with overshootand oscillation. However, when the fuzzy controller is seriallyconnected to the PI controller (called PID type fuzzy controller)in Fig. 1, the experiment is done again and the step response isalso shown in Fig. 9(a). It is obvious that although the dynamicis improved in Fig. 9(a) by using the PID type fuzzy controller,the rotor speed is still can’t follow the output of the referencemodel. However, when the proposed adaptive fuzzy controlleris presented in Fig. 1, and the learning rate are chosen by 0.05or 0.1, its tracking results are highly improved and presented inFig. 9(b) and (c). At initial, the rotor speed tracks the output of


Fig. 12. Frequency response of a 2 Hz sinusoid input signal with 2.0 N*m loadtorque under using the (a) fuzzy controller and (b) adaptive fuzzy controller.

reference model with oscillation; at the meanwhile, the param-eters of fuzzy controller are tuned toward reducing the error,which is the output of the reference model and the rotor speed,at each control sampling interval. After one or two squarewave command tracking, the parameters of fuzzy controllerare tuned to an adequate value, and the actual rotor speed canget a good following with the output of the reference model.Similarity, the proposed adaptive fuzzy controller demonstratesthe same adaptation ability at heavy-load condition, and thetracking results are shown in Fig. 10. Secondly, the frequencyresponse is considered to evaluate the performance of theproposed controller. A tested input signal of the sinusoid wavewith 1,350 150 rpm amplitude and a frequency of 2 Hz underdifferent load torque by 1.0N*m and 2.0N*m are provided. Inthis design, the frequency tracking response and the trackingerror of the PMSM without and with adaptation are shown inFigs. 11 and 12. In the case of light-load torque with 1.0N*m,it reveal that the 20 rpm amplitude tracking error obtainedby using the adaptive fuzzy controller (learning rate 0.1) isbetter than the 34 rpm tracking error obtained by only usingthe fuzzy controller in Fig. 11(a) and (b). Similarly, in the caseof heavy-load torque with 2.0 N*m, although the tracking error

with 62 rpm in Fig. 12(a) is worsen than the case of light-loadtorque by only using the fuzzy controller, the rotor speed can betuned to the same 20 rpm amplitude tracking error after usingthe adaptive fuzzy controller (learning rate 0.1) in Fig. 12(b).Therefore, the experimental results in Figs. 7–12 demonstratethat the proposed FPGA-based speed control IC for PMSMdrive is correctness and effectiveness.

IV. CONCLUSION

A speed control IC for PMSM drive based on the novel FPGAtechnology is successfully demonstrated in this paper. First, avector control in the current loop of the PMSM drive is usedto decouple the nonlinear and coupled characteristics of PMSMand an adaptive fuzzy controller in the speed loop of the PMSMdrive is applied to cope with the dynamic uncertainty and ex-ternal torque effect. Secondly, a speed control IC based on anFPGA and a Nios II embedded processor is designed to realizethe aforementioned control algorithms for ensuring high perfor-mance. The current vector control algorithm is implemented byhardware in FPGA and the adaptive fuzzy controller algorithmis implemented in software by using Nios II embedded pro-cessor. Therefore, all functionalities, which are based on soft-ware/hardware co-design, required to build a fully digital speedcontrol for PMSM drive have been integrated in one FPGA chip.In addition, a finite state machine (FSM) method is also pre-sented in this paper, and given the results that the total resourceusages save 2 795 LEs of FPGA in the overall circuits. Com-pared with DSP, using FPGA in the proposed control architec-ture has two benefits, which are described as follows.

1) Current controller implemented by hardware and speedcontroller implemented by software can all be pro-grammable design. Therefore, the flexibility of designinga specified function of PMSM drive is greatly increased.

2) Parallel processing of current loop vector controller andspeed loop adaptive controller makes the dynamic perfor-mance of the PMSM drive improvable.

Finally, the performance of the proposed controller is val-idated by the experimental results of the step and frequencycommand responses. In the test of the step command response,the adaptive fuzzy controller used in the speed loop of thePMSM drive, compared with the PI controller and fuzzycontroller, is demonstrated to be the best tracking result at theprescribed dynamic response under the different external loadcondition.

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Ying-Shieh Kung (M’03) was born in Taiwan,R.O.C., in 1957. He received the B.S. degree inaeronautical engineering from National ChengKung University, Tainan, Taiwan, in 1980, the M.S.degree in mechanical engineering from NationalTaiwan University, Taipei, Taiwan, in 1982, and thePh.D. degree in power mechanical engineering fromNational Tsing Hua University, Hsinchu, Taiwan, in1993.

From 1983 to 1996, he was an Engineer and fo-cused on the research in the field of automatic con-

trol of machine system at the Industrial Technology Research Institute, Hsinchu.Since 1996, he has been an Associate Professor with the Department of Elec-trical Engineering, Southern Taiwan University (STU), Tainan. He is currentlya Professor at STU. His areas of research interest are controller design for acmotor drives and linear motor drives, robot control, intelligent control, and dig-ital control using the DSP and FPGA implementations.

Ming-Hung Tsai was born in Taipei, Taiwan,R.O.C., in 1978. He received the B.S. degree inelectrical engineering from Minghsin University ofScience and Technology, Hsinchu, Taiwan, in 2001and the M.S. degree in electrical engineering fromSouthern Taiwan University, Tainan, Taiwan, in 2004where he is currently pursuing the Ph.D. degree.

His research interests are in the areas of ac motorcontrol, fuzzy control, FPGA controller realization,and FPGA-based control ICs for motor drives.

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